Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44		83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	217147902	10139562	0	0
boot_gen_cmd_rd_A	217147902	49585	0	0
boot_ins_cmd_rd_A	217147902	57358	0	0
ctrl_rd_A	217147902	50065	0	0
err_code_test_rd_A	217147902	56041	0	0
intr_enable_rd_A	217147902	54466	0	0
max_num_reqs_between_reseeds_rd_A	217147902	51526	0	0
regwen_rd_A	217147902	57121	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217147902	10139562	0	0
T3	881249	492373	0	0
T4	785	0	0	0
T5	42388	0	0	0
T9	3004	0	0	0
T16	1281	0	0	0
T21	3012	0	0	0
T22	3396	0	0	0
T23	1188	0	0	0
T27	3509	0	0	0
T100	4935	0	0	0
T101	0	227242	0	0
T111	0	92696	0	0
T148	0	239256	0	0
T187	0	311467	0	0
T188	0	48114	0	0
T189	0	86988	0	0
T190	0	114981	0	0
T191	0	39436	0	0
T192	0	257037	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217147902	49585	0	0
T151	2702	0	0	0
T155	3950	0	0	0
T190	329488	3530	0	0
T191	946831	0	0	0
T193	0	6754	0	0
T194	0	3460	0	0
T195	0	2163	0	0
T196	0	495	0	0
T197	0	3105	0	0
T198	0	11839	0	0
T199	0	6767	0	0
T200	0	4241	0	0
T201	0	5474	0	0
T202	2915	0	0	0
T203	2022	0	0	0
T204	2097	0	0	0
T205	5663	0	0	0
T206	5873	0	0	0
T207	2159	0	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217147902	57358	0	0
T151	2702	0	0	0
T155	3950	0	0	0
T190	329488	3908	0	0
T191	946831	0	0	0
T193	0	7631	0	0
T194	0	3904	0	0
T195	0	2235	0	0
T196	0	741	0	0
T197	0	3688	0	0
T198	0	13965	0	0
T199	0	8214	0	0
T200	0	4637	0	0
T201	0	6619	0	0
T202	2915	0	0	0
T203	2022	0	0	0
T204	2097	0	0	0
T205	5663	0	0	0
T206	5873	0	0	0
T207	2159	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217147902	50065	0	0
T4	785	5	0	0
T5	42388	0	0	0
T16	1281	0	0	0
T21	3012	0	0	0
T22	3396	0	0	0
T23	1188	0	0	0
T24	1306	0	0	0
T25	0	1	0	0
T27	3509	0	0	0
T100	4935	0	0	0
T101	399742	0	0	0
T104	0	3	0	0
T144	0	3	0	0
T190	0	3133	0	0
T193	0	6742	0	0
T208	0	3	0	0
T209	0	3	0	0
T210	0	5	0	0
T211	0	4	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217147902	56041	0	0
T151	2702	0	0	0
T155	3950	0	0	0
T190	329488	3970	0	0
T191	946831	0	0	0
T193	0	7329	0	0
T194	0	3897	0	0
T195	0	2407	0	0
T196	0	611	0	0
T197	0	3585	0	0
T198	0	13671	0	0
T199	0	7655	0	0
T200	0	4598	0	0
T201	0	6320	0	0
T202	2915	0	0	0
T203	2022	0	0	0
T204	2097	0	0	0
T205	5663	0	0	0
T206	5873	0	0	0
T207	2159	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217147902	54466	0	0
T30	1795	0	0	0
T75	1130	0	0	0
T105	1947	0	0	0
T111	160263	0	0	0
T117	853	0	0	0
T128	3534	0	0	0
T144	33961	42	0	0
T190	0	3768	0	0
T193	0	6837	0	0
T194	0	3396	0	0
T195	0	2145	0	0
T196	0	841	0	0
T197	0	3304	0	0
T211	0	44	0	0
T212	0	53	0	0
T213	0	31	0	0
T214	5020	0	0	0
T215	2079	0	0	0
T216	1870	0	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217147902	51526	0	0
T151	2702	0	0	0
T155	3950	0	0	0
T190	329488	3595	0	0
T191	946831	0	0	0
T193	0	6650	0	0
T194	0	3071	0	0
T195	0	2178	0	0
T196	0	693	0	0
T197	0	3367	0	0
T198	0	12193	0	0
T199	0	6975	0	0
T200	0	4092	0	0
T201	0	5961	0	0
T202	2915	0	0	0
T203	2022	0	0	0
T204	2097	0	0	0
T205	5663	0	0	0
T206	5873	0	0	0
T207	2159	0	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217147902	57121	0	0
T151	2702	0	0	0
T155	3950	0	0	0
T190	329488	4149	0	0
T191	946831	0	0	0
T193	0	7106	0	0
T194	0	3918	0	0
T195	0	2545	0	0
T196	0	737	0	0
T197	0	3520	0	0
T198	0	13358	0	0
T199	0	7930	0	0
T200	0	4687	0	0
T201	0	6250	0	0
T202	2915	0	0	0
T203	2022	0	0	0
T204	2097	0	0	0
T205	5663	0	0	0
T206	5873	0	0	0
T207	2159	0	0	0