Unified Coverage Report :: Module :: edn

Module : edn

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	94.44		83.33	100.00			100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.43	98.24	93.82	97.07	80.92	96.76	99.77

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
edn_csr_assert	100.00						100.00
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_edn_core	92.43	99.92	92.48	82.84	80.92	99.52	98.88
u_edn_cov_if	25.00	50.00	0.00
u_reg	96.95	95.02	97.57	100.00		92.16	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Cond Coverage for Module : edn

	Total	Covered	Percent
Conditions	6	5	83.33
Logical	6	5	83.33
Non-Logical	0	0
Event	0	0

 LINE       98
 EXPRESSION (alert[0] || intg_err_alert[0])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T9,T29,T30

 LINE       98
 EXPRESSION (alert[1] || intg_err_alert[1])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T15,T17
1	0	Covered	T4,T5,T16

---

Toggle Coverage for Module : edn

	Total	Covered	Percent
Totals	69	69	100.00
Total Bits	1172	1172	100.00
Total Bits 0->1	586	586	100.00
Total Bits 1->0	586	586	100.00

Ports	69	69	100.00
Port Bits	1172	1172	100.00
Port Bits 0->1	586	586	100.00
Port Bits 1->0	586	586	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T3,T4,T5	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T3,T9,T4	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T2,T3,T21	Yes	T2,T3,T21	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T3,T101,T111	Yes	T3,T101,T111	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T3,T9	Yes	T1,T3,T9	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i[0].edn_req	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
edn_i[1].edn_req	Yes	Yes	T1,T2,T22	Yes	T1,T2,T22	INPUT
edn_i[2].edn_req	Yes	Yes	T9,T21,T27	Yes	T9,T21,T27	INPUT
edn_i[3].edn_req	Yes	Yes	T1,T2,T21	Yes	T1,T2,T21	INPUT
edn_i[4].edn_req	Yes	Yes	T21,T22,T112	Yes	T21,T22,T112	INPUT
edn_i[5].edn_req	Yes	Yes	T2,T22,T112	Yes	T2,T22,T112	INPUT
edn_i[6].edn_req	Yes	Yes	T2,T16,T24	Yes	T2,T16,T24	INPUT
edn_o[0].edn_bus[31:0]	Yes	Yes	T1,T3,T21	Yes	T1,T3,T21	OUTPUT
edn_o[0].edn_fips	Yes	Yes	T3,T21,T22	Yes	T3,T21,T22	OUTPUT
edn_o[0].edn_ack	Yes	Yes	T1,T3,T21	Yes	T1,T3,T21	OUTPUT
edn_o[1].edn_bus[31:0]	Yes	Yes	T1,T2,T22	Yes	T1,T2,T22	OUTPUT
edn_o[1].edn_fips	Yes	Yes	T1,T2,T22	Yes	T1,T2,T22	OUTPUT
edn_o[1].edn_ack	Yes	Yes	T1,T2,T22	Yes	T1,T2,T22	OUTPUT
edn_o[2].edn_bus[31:0]	Yes	Yes	T21,T27,T112	Yes	T9,T21,T27	OUTPUT
edn_o[2].edn_fips	Yes	Yes	T21,T27,T113	Yes	T21,T27,T113	OUTPUT
edn_o[2].edn_ack	Yes	Yes	T9,T21,T27	Yes	T9,T21,T27	OUTPUT
edn_o[3].edn_bus[31:0]	Yes	Yes	T1,T2,T21	Yes	T1,T2,T21	OUTPUT
edn_o[3].edn_fips	Yes	Yes	T2,T21,T12	Yes	T1,T2,T21	OUTPUT
edn_o[3].edn_ack	Yes	Yes	T1,T2,T21	Yes	T1,T2,T21	OUTPUT
edn_o[4].edn_bus[31:0]	Yes	Yes	T21,T22,T112	Yes	T21,T22,T112	OUTPUT
edn_o[4].edn_fips	Yes	Yes	T21,T22,T112	Yes	T21,T22,T112	OUTPUT
edn_o[4].edn_ack	Yes	Yes	T21,T22,T112	Yes	T21,T22,T112	OUTPUT
edn_o[5].edn_bus[31:0]	Yes	Yes	T2,T22,T112	Yes	T2,T22,T112	OUTPUT
edn_o[5].edn_fips	Yes	Yes	T22,T112,T12	Yes	T2,T22,T112	OUTPUT
edn_o[5].edn_ack	Yes	Yes	T2,T22,T112	Yes	T2,T22,T112	OUTPUT
edn_o[6].edn_bus[31:0]	Yes	Yes	T2,T24,T112	Yes	T2,T24,T112	OUTPUT
edn_o[6].edn_fips	Yes	Yes	T2,T113,T114	Yes	T2,T112,T113	OUTPUT
edn_o[6].edn_ack	Yes	Yes	T2,T16,T24	Yes	T2,T16,T24	OUTPUT
csrng_cmd_o.genbits_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_bus[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_i.genbits_bus[127:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.genbits_fips	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.genbits_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_rsp_sts[2:0]	Yes	Yes	T97,T35,T72	Yes	T97,T35,T72	INPUT
csrng_cmd_i.csrng_rsp_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_req_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T9,T115,T116	Yes	T9,T115,T116	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T4,T5,T16	Yes	T4,T5,T16	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T9,T115,T116	Yes	T9,T115,T116	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T4,T5,T16	Yes	T4,T5,T16	OUTPUT
intr_edn_cmd_req_done_o	Yes	Yes	T3,T100,T101	Yes	T3,T100,T101	OUTPUT
intr_edn_fatal_err_o	Yes	Yes	T3,T16,T23	Yes	T3,T16,T23	OUTPUT

*Tests covering at least one bit in the range

---

Assert Coverage for Module : edn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	47	47	100.00	47	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	47	47	100.00	47	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxKnownO_A	216639762	216453429	0	0
CsrngAppIfOut_A	216639762	216453429	0	0
FpvSecCmCntAlertCheck_A	216639762	130	0	0
FpvSecCmGenCmdFifoRptrCheck_A	216639762	90	0	0
FpvSecCmGenCmdFifoWptrCheck_A	216639762	90	0	0
FpvSecCmMainFsmCheck_A	216639762	90	0	0
FpvSecCmRegWeOnehotCheck_A	216639762	90	0	0
FpvSecCmResCmdFifoRptrCheck_A	216639762	90	0	0
FpvSecCmResCmdFifoWptrCheck_A	216639762	90	0	0
IntrEdnCmdReqDoneKnownO_A	216639762	216453429	0	0
TlAReadyKnownO_A	216639762	216453429	0	0
TlDValidKnownO_A	216639762	216453429	0	0
gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A	216639762	90	0	0
gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A	216639762	90	0	0
gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A	216639762	90	0	0
gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A	216639762	90	0	0
gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A	216639762	90	0	0
gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A	216639762	90	0	0
gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A	216639762	90	0	0
gen_edn_if_asserts[0].EdnDataStableDisable_A	216639762	572053	0	314
gen_edn_if_asserts[0].EdnDataStable_A	216639762	75397	0	356
gen_edn_if_asserts[0].EdnEndPointOut_A	216639762	216453429	0	0
gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A	216639762	151554	0	0
gen_edn_if_asserts[1].EdnDataStableDisable_A	216639762	572053	0	314
gen_edn_if_asserts[1].EdnDataStable_A	216639762	5217	0	95
gen_edn_if_asserts[1].EdnEndPointOut_A	216639762	216453429	0	0
gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A	216639762	151554	0	0
gen_edn_if_asserts[2].EdnDataStableDisable_A	216639762	572053	0	314
gen_edn_if_asserts[2].EdnDataStable_A	216639762	3049	0	100
gen_edn_if_asserts[2].EdnEndPointOut_A	216639762	216453429	0	0
gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A	216639762	151554	0	0
gen_edn_if_asserts[3].EdnDataStableDisable_A	216639762	572053	0	314
gen_edn_if_asserts[3].EdnDataStable_A	216639762	4041	0	93
gen_edn_if_asserts[3].EdnEndPointOut_A	216639762	216453429	0	0
gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A	216639762	151554	0	0
gen_edn_if_asserts[4].EdnDataStableDisable_A	216639762	572053	0	314
gen_edn_if_asserts[4].EdnDataStable_A	216639762	1933	0	85
gen_edn_if_asserts[4].EdnEndPointOut_A	216639762	216453429	0	0
gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A	216639762	151554	0	0
gen_edn_if_asserts[5].EdnDataStableDisable_A	216639762	572053	0	314
gen_edn_if_asserts[5].EdnDataStable_A	216639762	2490	0	82
gen_edn_if_asserts[5].EdnEndPointOut_A	216639762	216453429	0	0
gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A	216639762	151554	0	0
gen_edn_if_asserts[6].EdnDataStableDisable_A	216639762	572053	0	314
gen_edn_if_asserts[6].EdnDataStable_A	216639762	3095	0	79
gen_edn_if_asserts[6].EdnEndPointOut_A	216639762	216453429	0	0
gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A	216639762	151554	0	0

AlertTxKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216639762	216453429	0	0
T1	3949	3884	0	0
T2	2156	2092	0	0
T3	881249	881234	0	0
T4	785	646	0	0
T5	42388	21482	0	0
T9	3004	2943	0	0
T16	1281	1138	0	0
T21	3012	2929	0	0
T22	3396	3308	0	0
T23	1188	1025	0	0

CsrngAppIfOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216639762	216453429	0	0
T1	3949	3884	0	0
T2	2156	2092	0	0
T3	881249	881234	0	0
T4	785	646	0	0
T5	42388	21482	0	0
T9	3004	2943	0	0
T16	1281	1138	0	0
T21	3012	2929	0	0
T22	3396	3308	0	0
T23	1188	1025	0	0

FpvSecCmCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216639762	130	0	0
T4	785	1	0	0
T5	42388	20	0	0
T8	0	1	0	0
T15	0	20	0	0
T16	1281	0	0	0
T21	3012	0	0	0
T22	3396	0	0	0
T23	1188	0	0	0
T24	1306	0	0	0
T27	3509	0	0	0
T65	0	1	0	0
T67	0	1	0	0
T99	0	1	0	0
T100	4935	0	0	0
T101	399742	0	0	0
T117	0	1	0	0
T118	0	1	0	0
T119	0	1	0	0

FpvSecCmGenCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216639762	90	0	0
T5	42388	20	0	0
T10	3174	0	0	0
T15	0	20	0	0
T16	1281	0	0	0
T17	0	20	0	0
T21	3012	0	0	0
T22	3396	0	0	0
T23	1188	0	0	0
T24	1306	0	0	0
T27	3509	0	0	0
T100	4935	0	0	0
T101	399742	0	0	0
T120	0	10	0	0
T121	0	20	0	0

FpvSecCmGenCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216639762	90	0	0
T5	42388	20	0	0
T10	3174	0	0	0
T15	0	20	0	0
T16	1281	0	0	0
T17	0	20	0	0
T21	3012	0	0	0
T22	3396	0	0	0
T23	1188	0	0	0
T24	1306	0	0	0
T27	3509	0	0	0
T100	4935	0	0	0
T101	399742	0	0	0
T120	0	10	0	0
T121	0	20	0	0

FpvSecCmMainFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216639762	90	0	0
T5	42388	20	0	0
T10	3174	0	0	0
T15	0	20	0	0
T16	1281	0	0	0
T17	0	20	0	0
T21	3012	0	0	0
T22	3396	0	0	0
T23	1188	0	0	0
T24	1306	0	0	0
T27	3509	0	0	0
T100	4935	0	0	0
T101	399742	0	0	0
T120	0	10	0	0
T121	0	20	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216639762	90	0	0
T5	42388	20	0	0
T10	3174	0	0	0
T15	0	20	0	0
T16	1281	0	0	0
T17	0	20	0	0
T21	3012	0	0	0
T22	3396	0	0	0
T23	1188	0	0	0
T24	1306	0	0	0
T27	3509	0	0	0
T100	4935	0	0	0
T101	399742	0	0	0
T120	0	10	0	0
T121	0	20	0	0

FpvSecCmResCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216639762	90	0	0
T5	42388	20	0	0
T10	3174	0	0	0
T15	0	20	0	0
T16	1281	0	0	0
T17	0	20	0	0
T21	3012	0	0	0
T22	3396	0	0	0
T23	1188	0	0	0
T24	1306	0	0	0
T27	3509	0	0	0
T100	4935	0	0	0
T101	399742	0	0	0
T120	0	10	0	0
T121	0	20	0	0

FpvSecCmResCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216639762	90	0	0
T5	42388	20	0	0
T10	3174	0	0	0
T15	0	20	0	0
T16	1281	0	0	0
T17	0	20	0	0
T21	3012	0	0	0
T22	3396	0	0	0
T23	1188	0	0	0
T24	1306	0	0	0
T27	3509	0	0	0
T100	4935	0	0	0
T101	399742	0	0	0
T120	0	10	0	0
T121	0	20	0	0

IntrEdnCmdReqDoneKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216639762	216453429	0	0
T1	3949	3884	0	0
T2	2156	2092	0	0
T3	881249	881234	0	0
T4	785	646	0	0
T5	42388	21482	0	0
T9	3004	2943	0	0
T16	1281	1138	0	0
T21	3012	2929	0	0
T22	3396	3308	0	0
T23	1188	1025	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216639762	216453429	0	0
T1	3949	3884	0	0
T2	2156	2092	0	0
T3	881249	881234	0	0
T4	785	646	0	0
T5	42388	21482	0	0
T9	3004	2943	0	0
T16	1281	1138	0	0
T21	3012	2929	0	0
T22	3396	3308	0	0
T23	1188	1025	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216639762	216453429	0	0
T1	3949	3884	0	0
T2	2156	2092	0	0
T3	881249	881234	0	0
T4	785	646	0	0
T5	42388	21482	0	0
T9	3004	2943	0	0
T16	1281	1138	0	0
T21	3012	2929	0	0
T22	3396	3308	0	0
T23	1188	1025	0	0

gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216639762	90	0	0
T5	42388	20	0	0
T10	3174	0	0	0
T15	0	20	0	0
T16	1281	0	0	0
T17	0	20	0	0
T21	3012	0	0	0
T22	3396	0	0	0
T23	1188	0	0	0
T24	1306	0	0	0
T27	3509	0	0	0
T100	4935	0	0	0
T101	399742	0	0	0
T120	0	10	0	0
T121	0	20	0	0

gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216639762	90	0	0
T5	42388	20	0	0
T10	3174	0	0	0
T15	0	20	0	0
T16	1281	0	0	0
T17	0	20	0	0
T21	3012	0	0	0
T22	3396	0	0	0
T23	1188	0	0	0
T24	1306	0	0	0
T27	3509	0	0	0
T100	4935	0	0	0
T101	399742	0	0	0
T120	0	10	0	0
T121	0	20	0	0

gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216639762	90	0	0
T5	42388	20	0	0
T10	3174	0	0	0
T15	0	20	0	0
T16	1281	0	0	0
T17	0	20	0	0
T21	3012	0	0	0
T22	3396	0	0	0
T23	1188	0	0	0
T24	1306	0	0	0
T27	3509	0	0	0
T100	4935	0	0	0
T101	399742	0	0	0
T120	0	10	0	0
T121	0	20	0	0

gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216639762	90	0	0
T5	42388	20	0	0
T10	3174	0	0	0
T15	0	20	0	0
T16	1281	0	0	0
T17	0	20	0	0
T21	3012	0	0	0
T22	3396	0	0	0
T23	1188	0	0	0
T24	1306	0	0	0
T27	3509	0	0	0
T100	4935	0	0	0
T101	399742	0	0	0
T120	0	10	0	0
T121	0	20	0	0

gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216639762	90	0	0
T5	42388	20	0	0
T10	3174	0	0	0
T15	0	20	0	0
T16	1281	0	0	0
T17	0	20	0	0
T21	3012	0	0	0
T22	3396	0	0	0
T23	1188	0	0	0
T24	1306	0	0	0
T27	3509	0	0	0
T100	4935	0	0	0
T101	399742	0	0	0
T120	0	10	0	0
T121	0	20	0	0

gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216639762	90	0	0
T5	42388	20	0	0
T10	3174	0	0	0
T15	0	20	0	0
T16	1281	0	0	0
T17	0	20	0	0
T21	3012	0	0	0
T22	3396	0	0	0
T23	1188	0	0	0
T24	1306	0	0	0
T27	3509	0	0	0
T100	4935	0	0	0
T101	399742	0	0	0
T120	0	10	0	0
T121	0	20	0	0

gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216639762	90	0	0
T5	42388	20	0	0
T10	3174	0	0	0
T15	0	20	0	0
T16	1281	0	0	0
T17	0	20	0	0
T21	3012	0	0	0
T22	3396	0	0	0
T23	1188	0	0	0
T24	1306	0	0	0
T27	3509	0	0	0
T100	4935	0	0	0
T101	399742	0	0	0
T120	0	10	0	0
T121	0	20	0	0

gen_edn_if_asserts[0].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216639762	572053	0	314
T1	3949	13	0	0
T2	2156	12	0	0
T3	881249	1607	0	2
T4	785	329	0	0
T5	42388	16988	0	2
T9	3004	235	0	0
T15	0	0	0	2
T16	1281	522	0	0
T19	0	0	0	2
T21	3012	38	0	0
T22	3396	19	0	0
T23	1188	505	0	0
T28	0	0	0	2
T33	0	0	0	2
T115	0	0	0	2
T116	0	0	0	2
T122	0	0	0	2
T123	0	0	0	2

gen_edn_if_asserts[0].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216639762	75397	0	356
T1	3949	10	0	1
T2	2156	0	0	0
T3	881249	119	0	0
T4	785	0	0	0
T5	42388	0	0	0
T9	3004	0	0	0
T10	0	15	0	1
T11	0	15	0	1
T16	1281	0	0	0
T18	0	3	0	1
T21	3012	18	0	1
T22	3396	53	0	1
T23	1188	0	0	0
T100	0	6	0	1
T101	0	53	0	1
T124	0	3	0	1
T125	0	0	0	1

gen_edn_if_asserts[0].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216639762	216453429	0	0
T1	3949	3884	0	0
T2	2156	2092	0	0
T3	881249	881234	0	0
T4	785	646	0	0
T5	42388	21482	0	0
T9	3004	2943	0	0
T16	1281	1138	0	0
T21	3012	2929	0	0
T22	3396	3308	0	0
T23	1188	1025	0	0

gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216639762	151554	0	0
T4	785	418	0	0
T5	42388	14557	0	0
T6	0	375	0	0
T15	0	14630	0	0
T16	1281	24	0	0
T21	3012	0	0	0
T22	3396	0	0	0
T23	1188	590	0	0
T24	1306	0	0	0
T25	0	638	0	0
T26	0	642	0	0
T27	3509	0	0	0
T65	0	1147	0	0
T99	0	664	0	0
T100	4935	0	0	0
T101	399742	0	0	0

gen_edn_if_asserts[1].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216639762	572053	0	314
T1	3949	13	0	0
T2	2156	12	0	0
T3	881249	1607	0	2
T4	785	329	0	0
T5	42388	16988	0	2
T9	3004	235	0	0
T15	0	0	0	2
T16	1281	522	0	0
T19	0	0	0	2
T21	3012	38	0	0
T22	3396	19	0	0
T23	1188	505	0	0
T28	0	0	0	2
T33	0	0	0	2
T115	0	0	0	2
T116	0	0	0	2
T122	0	0	0	2
T123	0	0	0	2

gen_edn_if_asserts[1].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216639762	5217	0	95
T1	3949	30	0	1
T2	2156	37	0	1
T3	881249	0	0	0
T4	785	0	0	0
T5	42388	0	0	0
T9	3004	0	0	0
T16	1281	0	0	0
T18	0	15	0	1
T21	3012	0	0	0
T22	3396	7	0	1
T23	1188	1	0	0
T28	0	1	0	0
T113	0	3	0	1
T114	0	0	0	1
T126	0	43	0	1
T127	0	35	0	1
T128	0	14	0	1
T129	0	0	0	1

gen_edn_if_asserts[1].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216639762	216453429	0	0
T1	3949	3884	0	0
T2	2156	2092	0	0
T3	881249	881234	0	0
T4	785	646	0	0
T5	42388	21482	0	0
T9	3004	2943	0	0
T16	1281	1138	0	0
T21	3012	2929	0	0
T22	3396	3308	0	0
T23	1188	1025	0	0

gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216639762	151554	0	0
T4	785	418	0	0
T5	42388	14557	0	0
T6	0	375	0	0
T15	0	14630	0	0
T16	1281	24	0	0
T21	3012	0	0	0
T22	3396	0	0	0
T23	1188	590	0	0
T24	1306	0	0	0
T25	0	638	0	0
T26	0	642	0	0
T27	3509	0	0	0
T65	0	1147	0	0
T99	0	664	0	0
T100	4935	0	0	0
T101	399742	0	0	0

gen_edn_if_asserts[2].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216639762	572053	0	314
T1	3949	13	0	0
T2	2156	12	0	0
T3	881249	1607	0	2
T4	785	329	0	0
T5	42388	16988	0	2
T9	3004	235	0	0
T15	0	0	0	2
T16	1281	522	0	0
T19	0	0	0	2
T21	3012	38	0	0
T22	3396	19	0	0
T23	1188	505	0	0
T28	0	0	0	2
T33	0	0	0	2
T115	0	0	0	2
T116	0	0	0	2
T122	0	0	0	2
T123	0	0	0	2

gen_edn_if_asserts[2].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216639762	3049	0	100
T4	785	0	0	0
T5	42388	0	0	0
T9	3004	4	0	1
T16	1281	0	0	0
T21	3012	56	0	1
T22	3396	0	0	0
T23	1188	0	0	0
T27	3509	58	0	1
T100	4935	0	0	0
T101	399742	0	0	0
T112	0	3	0	1
T113	0	9	0	1
T126	0	3	0	1
T127	0	9	0	1
T129	0	62	0	1
T130	0	3	0	1
T131	0	17	0	1

gen_edn_if_asserts[2].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216639762	216453429	0	0
T1	3949	3884	0	0
T2	2156	2092	0	0
T3	881249	881234	0	0
T4	785	646	0	0
T5	42388	21482	0	0
T9	3004	2943	0	0
T16	1281	1138	0	0
T21	3012	2929	0	0
T22	3396	3308	0	0
T23	1188	1025	0	0

gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216639762	151554	0	0
T4	785	418	0	0
T5	42388	14557	0	0
T6	0	375	0	0
T15	0	14630	0	0
T16	1281	24	0	0
T21	3012	0	0	0
T22	3396	0	0	0
T23	1188	590	0	0
T24	1306	0	0	0
T25	0	638	0	0
T26	0	642	0	0
T27	3509	0	0	0
T65	0	1147	0	0
T99	0	664	0	0
T100	4935	0	0	0
T101	399742	0	0	0

gen_edn_if_asserts[3].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216639762	572053	0	314
T1	3949	13	0	0
T2	2156	12	0	0
T3	881249	1607	0	2
T4	785	329	0	0
T5	42388	16988	0	2
T9	3004	235	0	0
T15	0	0	0	2
T16	1281	522	0	0
T19	0	0	0	2
T21	3012	38	0	0
T22	3396	19	0	0
T23	1188	505	0	0
T28	0	0	0	2
T33	0	0	0	2
T115	0	0	0	2
T116	0	0	0	2
T122	0	0	0	2
T123	0	0	0	2

gen_edn_if_asserts[3].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216639762	4041	0	93
T1	3949	3	0	1
T2	2156	19	0	1
T3	881249	0	0	0
T4	785	0	0	0
T5	42388	0	0	0
T9	3004	0	0	0
T12	0	58	0	1
T16	1281	0	0	0
T18	0	3	0	1
T21	3012	34	0	1
T22	3396	11	0	1
T23	1188	0	0	0
T27	0	15	0	1
T112	0	3	0	1
T113	0	39	0	1
T130	0	3	0	1

gen_edn_if_asserts[3].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216639762	216453429	0	0
T1	3949	3884	0	0
T2	2156	2092	0	0
T3	881249	881234	0	0
T4	785	646	0	0
T5	42388	21482	0	0
T9	3004	2943	0	0
T16	1281	1138	0	0
T21	3012	2929	0	0
T22	3396	3308	0	0
T23	1188	1025	0	0

gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216639762	151554	0	0
T4	785	418	0	0
T5	42388	14557	0	0
T6	0	375	0	0
T15	0	14630	0	0
T16	1281	24	0	0
T21	3012	0	0	0
T22	3396	0	0	0
T23	1188	590	0	0
T24	1306	0	0	0
T25	0	638	0	0
T26	0	642	0	0
T27	3509	0	0	0
T65	0	1147	0	0
T99	0	664	0	0
T100	4935	0	0	0
T101	399742	0	0	0

gen_edn_if_asserts[4].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216639762	572053	0	314
T1	3949	13	0	0
T2	2156	12	0	0
T3	881249	1607	0	2
T4	785	329	0	0
T5	42388	16988	0	2
T9	3004	235	0	0
T15	0	0	0	2
T16	1281	522	0	0
T19	0	0	0	2
T21	3012	38	0	0
T22	3396	19	0	0
T23	1188	505	0	0
T28	0	0	0	2
T33	0	0	0	2
T115	0	0	0	2
T116	0	0	0	2
T122	0	0	0	2
T123	0	0	0	2

gen_edn_if_asserts[4].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216639762	1933	0	85
T10	3174	0	0	0
T12	0	15	0	1
T15	43563	0	0	0
T16	1281	0	0	0
T19	0	4	0	0
T21	3012	26	0	1
T22	3396	53	0	1
T23	1188	0	0	0
T24	1306	0	0	0
T27	3509	0	0	0
T28	0	4	0	0
T100	4935	0	0	0
T101	399742	0	0	0
T112	0	53	0	1
T113	0	3	0	1
T126	0	3	0	1
T127	0	0	0	1
T130	0	32	0	1
T131	0	0	0	1
T132	0	7	0	1

gen_edn_if_asserts[4].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216639762	216453429	0	0
T1	3949	3884	0	0
T2	2156	2092	0	0
T3	881249	881234	0	0
T4	785	646	0	0
T5	42388	21482	0	0
T9	3004	2943	0	0
T16	1281	1138	0	0
T21	3012	2929	0	0
T22	3396	3308	0	0
T23	1188	1025	0	0

gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216639762	151554	0	0
T4	785	418	0	0
T5	42388	14557	0	0
T6	0	375	0	0
T15	0	14630	0	0
T16	1281	24	0	0
T21	3012	0	0	0
T22	3396	0	0	0
T23	1188	590	0	0
T24	1306	0	0	0
T25	0	638	0	0
T26	0	642	0	0
T27	3509	0	0	0
T65	0	1147	0	0
T99	0	664	0	0
T100	4935	0	0	0
T101	399742	0	0	0

gen_edn_if_asserts[5].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216639762	572053	0	314
T1	3949	13	0	0
T2	2156	12	0	0
T3	881249	1607	0	2
T4	785	329	0	0
T5	42388	16988	0	2
T9	3004	235	0	0
T15	0	0	0	2
T16	1281	522	0	0
T19	0	0	0	2
T21	3012	38	0	0
T22	3396	19	0	0
T23	1188	505	0	0
T28	0	0	0	2
T33	0	0	0	2
T115	0	0	0	2
T116	0	0	0	2
T122	0	0	0	2
T123	0	0	0	2

gen_edn_if_asserts[5].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216639762	2490	0	82
T2	2156	23	0	1
T3	881249	0	0	0
T4	785	0	0	0
T5	42388	0	0	0
T9	3004	0	0	0
T12	0	61	0	1
T13	0	75	0	1
T16	1281	0	0	0
T21	3012	0	0	0
T22	3396	27	0	1
T23	1188	0	0	0
T97	0	4	0	0
T100	4935	0	0	0
T112	0	11	0	1
T114	0	3	0	1
T129	0	3	0	1
T130	0	41	0	1
T133	0	975	0	1
T134	0	0	0	1

gen_edn_if_asserts[5].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216639762	216453429	0	0
T1	3949	3884	0	0
T2	2156	2092	0	0
T3	881249	881234	0	0
T4	785	646	0	0
T5	42388	21482	0	0
T9	3004	2943	0	0
T16	1281	1138	0	0
T21	3012	2929	0	0
T22	3396	3308	0	0
T23	1188	1025	0	0

gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216639762	151554	0	0
T4	785	418	0	0
T5	42388	14557	0	0
T6	0	375	0	0
T15	0	14630	0	0
T16	1281	24	0	0
T21	3012	0	0	0
T22	3396	0	0	0
T23	1188	590	0	0
T24	1306	0	0	0
T25	0	638	0	0
T26	0	642	0	0
T27	3509	0	0	0
T65	0	1147	0	0
T99	0	664	0	0
T100	4935	0	0	0
T101	399742	0	0	0

gen_edn_if_asserts[6].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216639762	572053	0	314
T1	3949	13	0	0
T2	2156	12	0	0
T3	881249	1607	0	2
T4	785	329	0	0
T5	42388	16988	0	2
T9	3004	235	0	0
T15	0	0	0	2
T16	1281	522	0	0
T19	0	0	0	2
T21	3012	38	0	0
T22	3396	19	0	0
T23	1188	505	0	0
T28	0	0	0	2
T33	0	0	0	2
T115	0	0	0	2
T116	0	0	0	2
T122	0	0	0	2
T123	0	0	0	2

gen_edn_if_asserts[6].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216639762	3095	0	79
T2	2156	35	0	1
T3	881249	0	0	0
T4	785	0	0	0
T5	42388	0	0	0
T9	3004	0	0	0
T16	1281	1	0	0
T21	3012	0	0	0
T22	3396	0	0	0
T23	1188	0	0	0
T24	0	4	0	0
T100	4935	0	0	0
T112	0	3	0	1
T113	0	699	0	1
T114	0	43	0	1
T129	0	3	0	1
T130	0	3	0	1
T131	0	3	0	1
T133	0	55	0	1
T135	0	0	0	1
T136	0	0	0	1

gen_edn_if_asserts[6].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216639762	216453429	0	0
T1	3949	3884	0	0
T2	2156	2092	0	0
T3	881249	881234	0	0
T4	785	646	0	0
T5	42388	21482	0	0
T9	3004	2943	0	0
T16	1281	1138	0	0
T21	3012	2929	0	0
T22	3396	3308	0	0
T23	1188	1025	0	0

gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216639762	151554	0	0
T4	785	418	0	0
T5	42388	14557	0	0
T6	0	375	0	0
T15	0	14630	0	0
T16	1281	24	0	0
T21	3012	0	0	0
T22	3396	0	0	0
T23	1188	590	0	0
T24	1306	0	0	0
T25	0	638	0	0
T26	0	642	0	0
T27	3509	0	0	0
T65	0	1147	0	0
T99	0	664	0	0
T100	4935	0	0	0
T101	399742	0	0	0