Unified Coverage Report :: Module :: edn_ack_sm

Module : edn_ack_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.58	100.00	90.30			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.58	100.00	90.30			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.58	100.00	90.30			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.58	100.00	90.30			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.58	100.00	90.30			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.58	100.00	90.30			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.58	100.00	90.30			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_ack_sm

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T9,T16,T24

---

FSM Coverage for Module : edn_ack_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T1,T2,T3
DataWait	75	Covered	T1,T2,T3
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T4,T5,T23
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T94,T96
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T1,T2,T3
DataWait->AckPls	80	Covered	T1,T2,T3
DataWait->Disabled	107	Covered	T28,T33,T84
DataWait->Error	99	Covered	T4,T25,T26
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T5,T15,T17
EndPointClear->Disabled	107	Covered	T153,T90,T154
EndPointClear->Error	99	Covered	T5,T15,T78
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T1,T2,T3
Idle->Disabled	107	Covered	T3,T9,T5
Idle->Error	99	Covered	T4,T23,T99

---

Branch Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T1,T2,T3
Idle	-	1	0	-	Covered	T1,T2,T3
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T1,T2,T3
DataWait	-	-	-	0	Covered	T1,T2,T3
AckPls	-	-	-	-	Covered	T1,T2,T3
Error	-	-	-	-	Covered	T4,T5,T23
default	-	-	-	-	Covered	T5,T23,T15

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T23
0	1	Covered	T9,T16,T24
0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_ack_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	1516478334	1038030	0	0
FpvSecCmErrorStEscalate_A	1516478334	1047109	0	0
u_state_regs_A	1516443796	1515139465	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1516478334	1038030	0	0
T4	5495	2912	0	0
T5	296716	98259	0	0
T6	0	2561	0	0
T7	0	4200	0	0
T15	0	98770	0	0
T16	8967	0	0	0
T21	21084	0	0	0
T22	23772	0	0	0
T23	8316	4066	0	0
T24	9142	0	0	0
T25	0	4452	0	0
T26	0	4430	0	0
T27	24563	0	0	0
T65	0	8015	0	0
T99	0	4634	0	0
T100	34545	0	0	0
T101	2798194	0	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1516478334	1047109	0	0
T4	5495	2919	0	0
T5	296716	100079	0	0
T6	0	2568	0	0
T7	0	4207	0	0
T15	0	100590	0	0
T16	8967	0	0	0
T21	21084	0	0	0
T22	23772	0	0	0
T23	8316	4073	0	0
T24	9142	0	0	0
T25	0	4459	0	0
T26	0	4437	0	0
T27	24563	0	0	0
T65	0	8022	0	0
T99	0	4641	0	0
T100	34545	0	0	0
T101	2798194	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1516443796	1515139465	0	0
T1	27643	27188	0	0
T2	15092	14644	0	0
T3	6168743	6168638	0	0
T4	5291	4318	0	0
T5	296716	150374	0	0
T9	21028	20601	0	0
T16	8911	7910	0	0
T21	21084	20503	0	0
T22	23772	23156	0	0
T23	8204	7063	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T9,T16,T24

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T1,T3,T21
DataWait	75	Covered	T1,T3,T4
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T4,T5,T23
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T1,T3,T21
DataWait->AckPls	80	Covered	T1,T3,T21
DataWait->Disabled	107	Covered	T57,T155,T85
DataWait->Error	99	Covered	T4,T65,T7
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T5,T15,T17
EndPointClear->Disabled	107	Covered	T153,T90,T154
EndPointClear->Error	99	Covered	T5,T15,T78
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T1,T3,T4
Idle->Disabled	107	Covered	T3,T9,T5
Idle->Error	99	Covered	T99,T25,T156

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T1,T3,T21
Idle	-	1	0	-	Covered	T1,T3,T4
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T1,T3,T21
DataWait	-	-	-	0	Covered	T1,T3,T4
AckPls	-	-	-	-	Covered	T1,T3,T21
Error	-	-	-	-	Covered	T4,T5,T23
default	-	-	-	-	Covered	T5,T23,T15

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T23
0	1	Covered	T9,T16,T24
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	216639762	146490	0	0
FpvSecCmErrorStEscalate_A	216639762	147787	0	0
u_state_regs_A	216605224	216418891	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216639762	146490	0	0
T4	785	416	0	0
T5	42388	14037	0	0
T6	0	323	0	0
T7	0	600	0	0
T15	0	14110	0	0
T16	1281	0	0	0
T21	3012	0	0	0
T22	3396	0	0	0
T23	1188	538	0	0
T24	1306	0	0	0
T25	0	636	0	0
T26	0	590	0	0
T27	3509	0	0	0
T65	0	1145	0	0
T99	0	662	0	0
T100	4935	0	0	0
T101	399742	0	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216639762	147787	0	0
T4	785	417	0	0
T5	42388	14297	0	0
T6	0	324	0	0
T7	0	601	0	0
T15	0	14370	0	0
T16	1281	0	0	0
T21	3012	0	0	0
T22	3396	0	0	0
T23	1188	539	0	0
T24	1306	0	0	0
T25	0	637	0	0
T26	0	591	0	0
T27	3509	0	0	0
T65	0	1146	0	0
T99	0	663	0	0
T100	4935	0	0	0
T101	399742	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216605224	216418891	0	0
T1	3949	3884	0	0
T2	2156	2092	0	0
T3	881249	881234	0	0
T4	581	442	0	0
T5	42388	21482	0	0
T9	3004	2943	0	0
T16	1225	1082	0	0
T21	3012	2929	0	0
T22	3396	3308	0	0
T23	1076	913	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T9,T16,T24

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T1,T2,T22
DataWait	75	Covered	T1,T2,T22
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T4,T5,T23
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T1,T2,T22
DataWait->AckPls	80	Covered	T1,T2,T22
DataWait->Disabled	107	Covered	T28,T84,T157
DataWait->Error	99	Covered	T25,T53,T82
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T5,T15,T17
EndPointClear->Disabled	107	Covered	T153,T90,T154
EndPointClear->Error	99	Covered	T5,T15,T78
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T1,T2,T22
Idle->Disabled	107	Covered	T3,T9,T5
Idle->Error	99	Covered	T4,T23,T99

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T1,T2,T22
Idle	-	1	0	-	Covered	T1,T2,T22
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T1,T2,T22
DataWait	-	-	-	0	Covered	T1,T2,T22
AckPls	-	-	-	-	Covered	T1,T2,T22
Error	-	-	-	-	Covered	T4,T5,T23
default	-	-	-	-	Covered	T5,T15,T17

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T23
0	1	Covered	T9,T16,T24
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	216639762	148590	0	0
FpvSecCmErrorStEscalate_A	216639762	149887	0	0
u_state_regs_A	216639762	216453429	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216639762	148590	0	0
T4	785	416	0	0
T5	42388	14037	0	0
T6	0	373	0	0
T7	0	600	0	0
T15	0	14110	0	0
T16	1281	0	0	0
T21	3012	0	0	0
T22	3396	0	0	0
T23	1188	588	0	0
T24	1306	0	0	0
T25	0	636	0	0
T26	0	640	0	0
T27	3509	0	0	0
T65	0	1145	0	0
T99	0	662	0	0
T100	4935	0	0	0
T101	399742	0	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216639762	149887	0	0
T4	785	417	0	0
T5	42388	14297	0	0
T6	0	374	0	0
T7	0	601	0	0
T15	0	14370	0	0
T16	1281	0	0	0
T21	3012	0	0	0
T22	3396	0	0	0
T23	1188	589	0	0
T24	1306	0	0	0
T25	0	637	0	0
T26	0	641	0	0
T27	3509	0	0	0
T65	0	1146	0	0
T99	0	663	0	0
T100	4935	0	0	0
T101	399742	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216639762	216453429	0	0
T1	3949	3884	0	0
T2	2156	2092	0	0
T3	881249	881234	0	0
T4	785	646	0	0
T5	42388	21482	0	0
T9	3004	2943	0	0
T16	1281	1138	0	0
T21	3012	2929	0	0
T22	3396	3308	0	0
T23	1188	1025	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T9,T16,T24

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T1,T2,T21
DataWait	75	Covered	T1,T2,T21
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T4,T5,T23
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T1,T2,T21
DataWait->AckPls	80	Covered	T1,T2,T21
DataWait->Disabled	107	Covered	T158,T159,T160
DataWait->Error	99	Covered	T26,T67,T161
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T5,T15,T17
EndPointClear->Disabled	107	Covered	T153,T90,T154
EndPointClear->Error	99	Covered	T5,T15,T78
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T1,T2,T21
Idle->Disabled	107	Covered	T3,T9,T5
Idle->Error	99	Covered	T4,T23,T99

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T1,T2,T21
Idle	-	1	0	-	Covered	T1,T2,T21
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T1,T2,T21
DataWait	-	-	-	0	Covered	T1,T2,T21
AckPls	-	-	-	-	Covered	T1,T2,T21
Error	-	-	-	-	Covered	T4,T5,T23
default	-	-	-	-	Covered	T5,T15,T17

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T23
0	1	Covered	T9,T16,T24
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	216639762	148590	0	0
FpvSecCmErrorStEscalate_A	216639762	149887	0	0
u_state_regs_A	216639762	216453429	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216639762	148590	0	0
T4	785	416	0	0
T5	42388	14037	0	0
T6	0	373	0	0
T7	0	600	0	0
T15	0	14110	0	0
T16	1281	0	0	0
T21	3012	0	0	0
T22	3396	0	0	0
T23	1188	588	0	0
T24	1306	0	0	0
T25	0	636	0	0
T26	0	640	0	0
T27	3509	0	0	0
T65	0	1145	0	0
T99	0	662	0	0
T100	4935	0	0	0
T101	399742	0	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216639762	149887	0	0
T4	785	417	0	0
T5	42388	14297	0	0
T6	0	374	0	0
T7	0	601	0	0
T15	0	14370	0	0
T16	1281	0	0	0
T21	3012	0	0	0
T22	3396	0	0	0
T23	1188	589	0	0
T24	1306	0	0	0
T25	0	637	0	0
T26	0	641	0	0
T27	3509	0	0	0
T65	0	1146	0	0
T99	0	663	0	0
T100	4935	0	0	0
T101	399742	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216639762	216453429	0	0
T1	3949	3884	0	0
T2	2156	2092	0	0
T3	881249	881234	0	0
T4	785	646	0	0
T5	42388	21482	0	0
T9	3004	2943	0	0
T16	1281	1138	0	0
T21	3012	2929	0	0
T22	3396	3308	0	0
T23	1188	1025	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T9,T16,T24

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T21,T22,T112
DataWait	75	Covered	T21,T22,T112
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T4,T5,T23
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T21,T22,T112
DataWait->AckPls	80	Covered	T21,T22,T112
DataWait->Disabled	107	Covered	T33,T162,T37
DataWait->Error	99	Covered	T163,T31,T164
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T5,T15,T17
EndPointClear->Disabled	107	Covered	T153,T90,T154
EndPointClear->Error	99	Covered	T5,T15,T78
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T21,T22,T112
Idle->Disabled	107	Covered	T3,T9,T5
Idle->Error	99	Covered	T4,T23,T99

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T21,T22,T112
Idle	-	1	0	-	Covered	T21,T22,T112
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T21,T22,T112
DataWait	-	-	-	0	Covered	T21,T22,T112
AckPls	-	-	-	-	Covered	T21,T22,T112
Error	-	-	-	-	Covered	T4,T5,T23
default	-	-	-	-	Covered	T5,T15,T17

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T23
0	1	Covered	T9,T16,T24
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	216639762	148590	0	0
FpvSecCmErrorStEscalate_A	216639762	149887	0	0
u_state_regs_A	216639762	216453429	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216639762	148590	0	0
T4	785	416	0	0
T5	42388	14037	0	0
T6	0	373	0	0
T7	0	600	0	0
T15	0	14110	0	0
T16	1281	0	0	0
T21	3012	0	0	0
T22	3396	0	0	0
T23	1188	588	0	0
T24	1306	0	0	0
T25	0	636	0	0
T26	0	640	0	0
T27	3509	0	0	0
T65	0	1145	0	0
T99	0	662	0	0
T100	4935	0	0	0
T101	399742	0	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216639762	149887	0	0
T4	785	417	0	0
T5	42388	14297	0	0
T6	0	374	0	0
T7	0	601	0	0
T15	0	14370	0	0
T16	1281	0	0	0
T21	3012	0	0	0
T22	3396	0	0	0
T23	1188	589	0	0
T24	1306	0	0	0
T25	0	637	0	0
T26	0	641	0	0
T27	3509	0	0	0
T65	0	1146	0	0
T99	0	663	0	0
T100	4935	0	0	0
T101	399742	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216639762	216453429	0	0
T1	3949	3884	0	0
T2	2156	2092	0	0
T3	881249	881234	0	0
T4	785	646	0	0
T5	42388	21482	0	0
T9	3004	2943	0	0
T16	1281	1138	0	0
T21	3012	2929	0	0
T22	3396	3308	0	0
T23	1188	1025	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T9,T16,T24

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T2,T22,T112
DataWait	75	Covered	T2,T22,T112
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T4,T5,T23
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T2,T22,T112
DataWait->AckPls	80	Covered	T2,T22,T112
DataWait->Disabled	107	Covered	T165,T166,T167
DataWait->Error	99	Covered	T168
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T5,T15,T17
EndPointClear->Disabled	107	Covered	T153,T90,T154
EndPointClear->Error	99	Covered	T5,T15,T78
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T2,T22,T112
Idle->Disabled	107	Covered	T3,T9,T5
Idle->Error	99	Covered	T4,T23,T99

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T2,T22,T112
Idle	-	1	0	-	Covered	T2,T22,T112
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T2,T22,T112
DataWait	-	-	-	0	Covered	T2,T22,T112
AckPls	-	-	-	-	Covered	T2,T22,T112
Error	-	-	-	-	Covered	T4,T5,T23
default	-	-	-	-	Covered	T5,T15,T17

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T23
0	1	Covered	T9,T16,T24
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	216639762	148590	0	0
FpvSecCmErrorStEscalate_A	216639762	149887	0	0
u_state_regs_A	216639762	216453429	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216639762	148590	0	0
T4	785	416	0	0
T5	42388	14037	0	0
T6	0	373	0	0
T7	0	600	0	0
T15	0	14110	0	0
T16	1281	0	0	0
T21	3012	0	0	0
T22	3396	0	0	0
T23	1188	588	0	0
T24	1306	0	0	0
T25	0	636	0	0
T26	0	640	0	0
T27	3509	0	0	0
T65	0	1145	0	0
T99	0	662	0	0
T100	4935	0	0	0
T101	399742	0	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216639762	149887	0	0
T4	785	417	0	0
T5	42388	14297	0	0
T6	0	374	0	0
T7	0	601	0	0
T15	0	14370	0	0
T16	1281	0	0	0
T21	3012	0	0	0
T22	3396	0	0	0
T23	1188	589	0	0
T24	1306	0	0	0
T25	0	637	0	0
T26	0	641	0	0
T27	3509	0	0	0
T65	0	1146	0	0
T99	0	663	0	0
T100	4935	0	0	0
T101	399742	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216639762	216453429	0	0
T1	3949	3884	0	0
T2	2156	2092	0	0
T3	881249	881234	0	0
T4	785	646	0	0
T5	42388	21482	0	0
T9	3004	2943	0	0
T16	1281	1138	0	0
T21	3012	2929	0	0
T22	3396	3308	0	0
T23	1188	1025	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T9,T16,T24

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T9,T21,T27
DataWait	75	Covered	T9,T21,T27
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T4,T5,T23
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T94
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T9,T21,T27
DataWait->AckPls	80	Covered	T9,T21,T27
DataWait->Disabled	107	Covered	T169,T170
DataWait->Error	99	Covered	T171,T46,T172
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T5,T15,T17
EndPointClear->Disabled	107	Covered	T153,T90,T154
EndPointClear->Error	99	Covered	T5,T15,T78
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T9,T21,T27
Idle->Disabled	107	Covered	T3,T9,T5
Idle->Error	99	Covered	T4,T23,T99

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T9,T21,T27
Idle	-	1	0	-	Covered	T9,T21,T27
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T9,T21,T27
DataWait	-	-	-	0	Covered	T9,T21,T27
AckPls	-	-	-	-	Covered	T9,T21,T27
Error	-	-	-	-	Covered	T4,T5,T23
default	-	-	-	-	Covered	T5,T15,T17

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T23
0	1	Covered	T9,T16,T24
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	216639762	148590	0	0
FpvSecCmErrorStEscalate_A	216639762	149887	0	0
u_state_regs_A	216639762	216453429	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216639762	148590	0	0
T4	785	416	0	0
T5	42388	14037	0	0
T6	0	373	0	0
T7	0	600	0	0
T15	0	14110	0	0
T16	1281	0	0	0
T21	3012	0	0	0
T22	3396	0	0	0
T23	1188	588	0	0
T24	1306	0	0	0
T25	0	636	0	0
T26	0	640	0	0
T27	3509	0	0	0
T65	0	1145	0	0
T99	0	662	0	0
T100	4935	0	0	0
T101	399742	0	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216639762	149887	0	0
T4	785	417	0	0
T5	42388	14297	0	0
T6	0	374	0	0
T7	0	601	0	0
T15	0	14370	0	0
T16	1281	0	0	0
T21	3012	0	0	0
T22	3396	0	0	0
T23	1188	589	0	0
T24	1306	0	0	0
T25	0	637	0	0
T26	0	641	0	0
T27	3509	0	0	0
T65	0	1146	0	0
T99	0	663	0	0
T100	4935	0	0	0
T101	399742	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216639762	216453429	0	0
T1	3949	3884	0	0
T2	2156	2092	0	0
T3	881249	881234	0	0
T4	785	646	0	0
T5	42388	21482	0	0
T9	3004	2943	0	0
T16	1281	1138	0	0
T21	3012	2929	0	0
T22	3396	3308	0	0
T23	1188	1025	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T9,T16,T24

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T2,T16,T24
DataWait	75	Covered	T2,T16,T24
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T4,T5,T23
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T96
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T2,T16,T24
DataWait->AckPls	80	Covered	T2,T16,T24
DataWait->Disabled	107	Covered	T58,T173,T174
DataWait->Error	99	Covered	T175,T176,T177
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T5,T15,T17
EndPointClear->Disabled	107	Covered	T153,T90,T154
EndPointClear->Error	99	Covered	T5,T15,T78
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T2,T16,T24
Idle->Disabled	107	Covered	T3,T9,T5
Idle->Error	99	Covered	T4,T23,T99

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T2,T16,T24
Idle	-	1	0	-	Covered	T2,T16,T24
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T2,T16,T24
DataWait	-	-	-	0	Covered	T2,T24,T112
AckPls	-	-	-	-	Covered	T2,T16,T24
Error	-	-	-	-	Covered	T4,T5,T23
default	-	-	-	-	Covered	T5,T15,T17

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T23
0	1	Covered	T9,T16,T24
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

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Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	216639762	148590	0	0
FpvSecCmErrorStEscalate_A	216639762	149887	0	0
u_state_regs_A	216639762	216453429	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216639762	148590	0	0
T4	785	416	0	0
T5	42388	14037	0	0
T6	0	373	0	0
T7	0	600	0	0
T15	0	14110	0	0
T16	1281	0	0	0
T21	3012	0	0	0
T22	3396	0	0	0
T23	1188	588	0	0
T24	1306	0	0	0
T25	0	636	0	0
T26	0	640	0	0
T27	3509	0	0	0
T65	0	1145	0	0
T99	0	662	0	0
T100	4935	0	0	0
T101	399742	0	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216639762	149887	0	0
T4	785	417	0	0
T5	42388	14297	0	0
T6	0	374	0	0
T7	0	601	0	0
T15	0	14370	0	0
T16	1281	0	0	0
T21	3012	0	0	0
T22	3396	0	0	0
T23	1188	589	0	0
T24	1306	0	0	0
T25	0	637	0	0
T26	0	641	0	0
T27	3509	0	0	0
T65	0	1146	0	0
T99	0	663	0	0
T100	4935	0	0	0
T101	399742	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216639762	216453429	0	0
T1	3949	3884	0	0
T2	2156	2092	0	0
T3	881249	881234	0	0
T4	785	646	0	0
T5	42388	21482	0	0
T9	3004	2943	0	0
T16	1281	1138	0	0
T21	3012	2929	0	0
T22	3396	3308	0	0
T23	1188	1025	0	0