Module Definition
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Module : edn_core
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.58 100.00 90.30 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_core.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_edn_core 97.58 100.00 90.30 100.00 100.00



Module Instance : tb.dut.u_edn_core

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.58 100.00 90.30 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.43 99.92 92.48 82.84 80.92 99.52 98.88


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.44 83.33 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_ep_blk[0].u_edn_ack_sm_ep 97.14 100.00 100.00 85.71 100.00 100.00
gen_ep_blk[0].u_prim_packer_fifo_ep 98.81 100.00 95.24 100.00 100.00
gen_ep_blk[1].u_edn_ack_sm_ep 97.14 100.00 100.00 85.71 100.00 100.00
gen_ep_blk[1].u_prim_packer_fifo_ep 98.81 100.00 95.24 100.00 100.00
gen_ep_blk[2].u_edn_ack_sm_ep 98.57 100.00 100.00 92.86 100.00 100.00
gen_ep_blk[2].u_prim_packer_fifo_ep 98.81 100.00 95.24 100.00 100.00
gen_ep_blk[3].u_edn_ack_sm_ep 97.14 100.00 100.00 85.71 100.00 100.00
gen_ep_blk[3].u_prim_packer_fifo_ep 98.81 100.00 95.24 100.00 100.00
gen_ep_blk[4].u_edn_ack_sm_ep 97.14 100.00 100.00 85.71 100.00 100.00
gen_ep_blk[4].u_prim_packer_fifo_ep 98.81 100.00 95.24 100.00 100.00
gen_ep_blk[5].u_edn_ack_sm_ep 97.14 100.00 100.00 85.71 100.00 100.00
gen_ep_blk[5].u_prim_packer_fifo_ep 98.81 100.00 95.24 100.00 100.00
gen_ep_blk[6].u_edn_ack_sm_ep 98.57 100.00 100.00 92.86 100.00 100.00
gen_ep_blk[6].u_prim_packer_fifo_ep 98.81 100.00 95.24 100.00 100.00
u_edn_main_sm 94.40 100.00 100.00 72.00 100.00 100.00
u_intr_hw_edn_cmd_req_done 100.00 100.00 100.00 100.00 100.00
u_intr_hw_edn_fatal_err 100.00 100.00 100.00 100.00 100.00
u_prim_arbiter_ppc_packer_arb 95.16 95.00 92.31 100.00 93.33
u_prim_count_max_reqs_cntr 71.29 71.29
u_prim_edge_detector_recov_alert 100.00 100.00 100.00 100.00
u_prim_fifo_sync_gencmd 98.38 100.00 91.89 100.00 100.00 100.00
u_prim_fifo_sync_rescmd 98.38 100.00 91.89 100.00 100.00 100.00
u_prim_mubi4_sync_auto_req_mode 100.00 100.00 100.00
u_prim_mubi4_sync_boot_req_mode 100.00 100.00 100.00
u_prim_mubi4_sync_cmd_fifo_rst 100.00 100.00 100.00
u_prim_mubi4_sync_edn_enable 100.00 100.00 100.00
u_prim_packer_fifo_cs 95.24 100.00 95.24 85.71 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : edn_core
Line No.TotalCoveredPercent
TOTAL253253100.00
ALWAYS2173636100.00
CONT_ASSIGN29211100.00
CONT_ASSIGN29711100.00
CONT_ASSIGN30411100.00
CONT_ASSIGN31011100.00
CONT_ASSIGN31211100.00
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CONT_ASSIGN31811100.00
CONT_ASSIGN32111100.00
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CONT_ASSIGN33711100.00
CONT_ASSIGN34011100.00
CONT_ASSIGN34311100.00
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CONT_ASSIGN35111100.00
CONT_ASSIGN35211100.00
CONT_ASSIGN35711100.00
CONT_ASSIGN36011100.00
CONT_ASSIGN36311100.00
CONT_ASSIGN36811100.00
CONT_ASSIGN36811100.00
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CONT_ASSIGN37211100.00
CONT_ASSIGN37411100.00
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CONT_ASSIGN37811100.00
CONT_ASSIGN39711100.00
CONT_ASSIGN40011100.00
CONT_ASSIGN40411100.00
CONT_ASSIGN41311100.00
CONT_ASSIGN41411100.00
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CONT_ASSIGN41611100.00
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CONT_ASSIGN41911100.00
CONT_ASSIGN41911100.00
CONT_ASSIGN43411100.00
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CONT_ASSIGN44011100.00
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CONT_ASSIGN59911100.00
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CONT_ASSIGN60611100.00
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CONT_ASSIGN61611100.00
CONT_ASSIGN61711100.00
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CONT_ASSIGN66011100.00
CONT_ASSIGN66411100.00
CONT_ASSIGN66611100.00
CONT_ASSIGN66811100.00
CONT_ASSIGN69711100.00
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CONT_ASSIGN70711100.00
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CONT_ASSIGN91911100.00
CONT_ASSIGN91911100.00
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CONT_ASSIGN92011100.00
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CONT_ASSIGN92011100.00
CONT_ASSIGN92011100.00
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CONT_ASSIGN93011100.00
CONT_ASSIGN93011100.00
CONT_ASSIGN93011100.00
CONT_ASSIGN93011100.00
CONT_ASSIGN93011100.00
CONT_ASSIGN93011100.00
CONT_ASSIGN93011100.00
CONT_ASSIGN95011100.00
CONT_ASSIGN96611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_core.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_core.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
217 1 1
218 1 1
219 1 1
220 1 1
221 1 1
222 1 1
223 1 1
224 1 1
225 1 1
226 1 1
227 1 1
228 1 1
229 1 1
230 1 1
231 1 1
232 1 1
233 1 1
234 1 1
236 1 1
237 1 1
238 1 1
239 1 1
240 1 1
241 1 1
242 1 1
243 1 1
244 1 1
245 1 1
246 1 1
247 1 1
248 1 1
249 1 1
250 1 1
251 1 1
252 1 1
253 1 1
292 1 1
297 1 1
304 1 1
310 1 1
312 1 1
314 1 1
316 1 1
318 1 1
321 1 1
325 1 1
329 1 1
337 1 1
340 1 1
343 1 1
346 1 1
349 1 1
351 1 1
352 1 1
357 1 1
360 1 1
363 1 1
368 31 31
372 1 1
374 1 1
375 1 1
378 1 1
397 1 1
400 1 1
404 1 1
413 1 1
414 1 1
415 1 1
416 1 1
419 19 19
434 1 1
435 1 1
436 1 1
437 1 1
440 3 3
454 1 1
461 1 1
462 1 1
463 1 1
464 1 1
465 1 1
480 1 1
481 1 1
483 1 1
484 1 1
486 1 1
487 1 1
489 1 1
490 1 1
492 1 1
493 1 1
494 1 1
497 1 1
506 1 1
513 1 1
517 1 1
533 1 1
541 1 1
542 1 1
547 1 1
548 1 1
552 1 1
562 1 1
563 1 1
573 1 1
574 1 1
581 1 1
582 1 1
593 1 1
594 1 1
599 1 1
600 1 1
606 1 1
607 1 1
616 1 1
617 1 1
626 1 1
627 1 1
654 1 1
656 1 1
660 1 1
664 1 1
666 1 1
668 1 1
697 1 1
699 1 1
703 1 1
707 1 1
709 1 1
711 1 1
770 1 1
774 1 1
777 1 1
787 1 1
792 1 1
793 1 1
794 1 1
795 1 1
798 1 1
834 7 7
858 1 1
859 1 1
861 1 1
862 1 1
863 1 1
864 1 1
866 1 1
881 1 1
883 1 1
885 1 1
891 1 1
894 1 1
895 1 1
919 7 7
920 7 7
923 7 7
926 7 7
929 7 7
930 7 7
950 1 1
966 1 1


Cond Coverage for Module : edn_core
TotalCoveredPercent
Conditions62956890.30
Logical62956890.30
Non-Logical00
Event00

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.
Line numbersPercent
292-70791.59
707-96687.30

Branch Coverage for Module : edn_core
Line No.TotalCoveredPercent
Branches 104 104 100.00
TERNARY 497 6 6 100.00
TERNARY 506 4 4 100.00
TERNARY 517 7 7 100.00
TERNARY 533 5 5 100.00
TERNARY 552 6 6 100.00
TERNARY 563 6 6 100.00
TERNARY 574 3 3 100.00
TERNARY 582 4 4 100.00
TERNARY 594 3 3 100.00
TERNARY 600 3 3 100.00
TERNARY 607 5 5 100.00
TERNARY 617 5 5 100.00
TERNARY 627 2 2 100.00
TERNARY 656 2 2 100.00
TERNARY 660 2 2 100.00
TERNARY 699 2 2 100.00
TERNARY 703 2 2 100.00
TERNARY 777 6 6 100.00
TERNARY 866 3 3 100.00
TERNARY 883 2 2 100.00
TERNARY 885 3 3 100.00
TERNARY 923 3 3 100.00
TERNARY 923 3 3 100.00
TERNARY 923 3 3 100.00
TERNARY 923 3 3 100.00
TERNARY 923 3 3 100.00
TERNARY 923 3 3 100.00
TERNARY 923 3 3 100.00
IF 217 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_core.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_core.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 497 ((!edn_enable_fo[CsrngCmdReq])) ? -2-: 497 (boot_wr_ins_cmd) ? -3-: 497 (boot_wr_gen_cmd) ? -4-: 497 (boot_wr_uni_cmd) ? -5-: 497 (sw_cmd_req_load) ?

Branches:
-1--2--3--4--5-StatusTests
1 - - - - Covered T1,T2,T3
0 1 - - - Covered T21,T22,T27
0 0 1 - - Covered T21,T22,T27
0 0 0 1 - Covered T21,T22,T27
0 0 0 0 1 Covered T1,T2,T3
0 0 0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 506 ((!edn_enable_fo[CsrngCmdReqValid])) ? -2-: 506 (cs_cmd_handshake) ? -3-: 506 ((((sw_cmd_req_load || boot_wr_ins_cmd) || boot_wr_gen_cmd) || boot_wr_uni_cmd)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 517 ((!edn_enable_fo[CsrngCmdReqOut])) ? -2-: 517 ((send_rescmd || capt_rescmd_fifo_cnt)) ? -3-: 517 (sfifo_rescmd_pop) ? -4-: 517 ((send_gencmd || capt_gencmd_fifo_cnt)) ? -5-: 517 (sfifo_gencmd_pop) ? -6-: 517 ((cs_cmd_req_vld_q && (!cs_cmd_handshake))) ?

Branches:
-1--2--3--4--5--6-StatusTests
1 - - - - - Covered T1,T2,T3
0 1 1 - - - Covered T10,T11,T18
0 1 0 - - - Covered T10,T11,T18
0 0 - 1 1 - Covered T9,T10,T11
0 0 - 1 0 - Covered T9,T10,T11
0 0 - 0 - 1 Covered T1,T2,T3
0 0 - 0 - 0 Covered T1,T2,T3


LineNo. Expression -1-: 533 ((!edn_enable_fo[CsrngCmdReqValidOut])) ? -2-: 533 (cmd_sent) ? -3-: 533 ((send_rescmd || capt_rescmd_fifo_cnt)) ? -4-: 533 ((send_gencmd || capt_gencmd_fifo_cnt)) ?

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Covered T9,T10,T11
0 0 1 - Covered T10,T11,T18
0 0 0 1 Covered T9,T10,T11
0 0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 552 ((!edn_enable_fo[SwCmdSts])) ? -2-: 552 ((!sw_cmd_valid)) ? -3-: 552 (sw_cmd_req_load) ? -4-: 552 (accept_sw_cmds_pulse) ? -5-: 552 (csrng_cmd_i.csrng_rsp_ack) ?

Branches:
-1--2--3--4--5-StatusTests
1 - - - - Covered T1,T2,T3
0 1 - - - Covered T9,T4,T5
0 0 1 - - Covered T1,T2,T3
0 0 0 1 - Covered T1,T2,T3
0 0 0 0 1 Covered T1,T2,T3
0 0 0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 563 ((!edn_enable_fo[SwCmdSts])) ? -2-: 563 ((!sw_cmd_valid)) ? -3-: 563 (sw_cmd_req_load) ? -4-: 563 (accept_sw_cmds_pulse) ? -5-: 563 (cs_cmd_handshake) ?

Branches:
-1--2--3--4--5-StatusTests
1 - - - - Covered T1,T2,T3
0 1 - - - Covered T9,T4,T5
0 0 1 - - Covered T1,T2,T3
0 0 0 1 - Covered T1,T2,T3
0 0 0 0 1 Covered T1,T2,T3
0 0 0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 574 ((!edn_enable_fo[SwCmdSts])) ? -2-: 574 ((csrng_cmd_i.csrng_rsp_ack && sw_cmd_valid)) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 582 ((!edn_enable_fo[SwCmdSts])) ? -2-: 582 (sw_cmd_req_load) ? -3-: 582 ((csrng_cmd_i.csrng_rsp_ack && sw_cmd_valid)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 594 ((main_sm_done_pulse || (!edn_enable_fo[HwCmdSts]))) ? -2-: 594 (boot_wr_ins_cmd) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T21,T22,T27
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 600 ((main_sm_done_pulse || (!edn_enable_fo[HwCmdSts]))) ? -2-: 600 (auto_req_mode_busy) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T9,T10,T11
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 607 ((!edn_enable_fo[HwCmdSts])) ? -2-: 607 (sw_cmd_valid) ? -3-: 607 ((cs_cmd_req_vld_out_q && csrng_cmd_i.csrng_req_ready)) ? -4-: 607 ((csrng_cmd_i.csrng_rsp_ack && csrng_cmd_i.csrng_rsp_sts)) ?

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Covered T1,T2,T3
0 0 1 - Covered T9,T21,T22
0 0 0 1 Covered T9,T29,T30
0 0 0 0 Covered T9,T4,T5


LineNo. Expression -1-: 617 ((!edn_enable_fo[HwCmdSts])) ? -2-: 617 (sw_cmd_valid) ? -3-: 617 ((cs_cmd_req_vld_out_q && csrng_cmd_i.csrng_req_ready)) ? -4-: 617 (csrng_cmd_i.csrng_rsp_ack) ?

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Covered T1,T2,T3
0 0 1 - Covered T9,T21,T22
0 0 0 1 Covered T9,T21,T22
0 0 0 0 Covered T9,T4,T5


LineNo. Expression -1-: 627 ((((edn_enable_fo[HwCmdSts] && (!sw_cmd_valid)) && cs_cmd_req_vld_out_q) && csrng_cmd_i.csrng_req_ready)) ?

Branches:
-1-StatusTests
1 Covered T9,T21,T22
0 Covered T1,T2,T3


LineNo. Expression -1-: 656 (rescmd_handshake) ?

Branches:
-1-StatusTests
1 Covered T10,T11,T18
0 Covered T1,T2,T3


LineNo. Expression -1-: 660 (auto_req_mode_busy) ?

Branches:
-1-StatusTests
1 Covered T9,T10,T11
0 Covered T1,T2,T3


LineNo. Expression -1-: 699 (gencmd_handshake) ?

Branches:
-1-StatusTests
1 Covered T9,T10,T11
0 Covered T1,T2,T3


LineNo. Expression -1-: 703 (auto_req_mode_busy) ?

Branches:
-1-StatusTests
1 Covered T9,T10,T11
0 Covered T1,T2,T3


LineNo. Expression -1-: 777 ((!edn_enable_fo[CmdFifoCnt])) ? -2-: 777 ((cmd_fifo_rst_fo[3] || main_sm_done_pulse)) ? -3-: 777 (capt_gencmd_fifo_cnt) ? -4-: 777 (capt_rescmd_fifo_cnt) ? -5-: 777 ((sfifo_gencmd_pop || sfifo_rescmd_pop)) ?

Branches:
-1--2--3--4--5-StatusTests
1 - - - - Covered T1,T2,T3
0 1 - - - Covered T1,T2,T3
0 0 1 - - Covered T9,T10,T11
0 0 0 1 - Covered T10,T11,T18
0 0 0 0 1 Covered T10,T11,T18
0 0 0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 866 ((!edn_enable_fo[CsrngFipsEn])) ? -2-: 866 ((packer_cs_push && packer_cs_wready)) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 883 (cs_rdata_capt_vld) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 885 ((!edn_enable_fo[CsrngDataVld])) ? -2-: 885 (cs_rdata_capt_vld) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 923 (packer_ep_clr[0]) ? -2-: 923 ((packer_ep_push[0] && packer_ep_wready[0])) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T3,T21
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 923 (packer_ep_clr[1]) ? -2-: 923 ((packer_ep_push[1] && packer_ep_wready[1])) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T22
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 923 (packer_ep_clr[2]) ? -2-: 923 ((packer_ep_push[2] && packer_ep_wready[2])) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T9,T21,T27
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 923 (packer_ep_clr[3]) ? -2-: 923 ((packer_ep_push[3] && packer_ep_wready[3])) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T21
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 923 (packer_ep_clr[4]) ? -2-: 923 ((packer_ep_push[4] && packer_ep_wready[4])) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T21,T22,T112
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 923 (packer_ep_clr[5]) ? -2-: 923 ((packer_ep_push[5] && packer_ep_wready[5])) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T2,T22,T112
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 923 (packer_ep_clr[6]) ? -2-: 923 ((packer_ep_push[6] && packer_ep_wready[6])) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T2,T16,T24
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 217 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Module : edn_core
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CsErrAcceptNoEntropy_A 216639762 6761 0 0
CsErrIssueNoCommands_A 216639762 6761 0 0


CsErrAcceptNoEntropy_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 216639762 6761 0 0
T4 785 0 0 0
T5 42388 0 0 0
T9 3004 159 0 0
T16 1281 0 0 0
T21 3012 0 0 0
T22 3396 0 0 0
T23 1188 0 0 0
T27 3509 0 0 0
T29 0 144 0 0
T30 0 141 0 0
T34 0 138 0 0
T35 0 117 0 0
T72 0 129 0 0
T79 0 117 0 0
T97 0 153 0 0
T98 0 129 0 0
T100 4935 0 0 0
T101 399742 0 0 0
T149 0 117 0 0

CsErrIssueNoCommands_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 216639762 6761 0 0
T4 785 0 0 0
T5 42388 0 0 0
T9 3004 159 0 0
T16 1281 0 0 0
T21 3012 0 0 0
T22 3396 0 0 0
T23 1188 0 0 0
T27 3509 0 0 0
T29 0 144 0 0
T30 0 141 0 0
T34 0 138 0 0
T35 0 117 0 0
T72 0 129 0 0
T79 0 117 0 0
T97 0 153 0 0
T98 0 129 0 0
T100 4935 0 0 0
T101 399742 0 0 0
T149 0 117 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%