Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_prim_fifo_sync_rescmd	94.64	100.00	78.57			100.00	100.00
tb.dut.u_edn_core.u_prim_fifo_sync_gencmd	94.64	100.00	78.57			100.00	100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.38	100.00	91.89	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.58	100.00	90.30			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.38	100.00	91.89	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.58	100.00	90.30			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Module : prim_fifo_sync

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T16,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T9,T4,T5

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T16,T106,T107
1	1	0	Not Covered
1	1	1	Covered	T9,T4,T16

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T108,T109,T110
1	0	1	Covered	T9,T4,T5
1	1	0	Not Covered
1	1	1	Covered	T9,T10,T11

---

Branch Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T9,T4,T16
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	432398058	992213	0	0
DepthKnown_A	433279524	432906858	0	0
RvalidKnown_A	433279524	432906858	0	0
WreadyKnown_A	433279524	432906858	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	432763998	1080652	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432398058	992213	0	0
T4	240	0	0	0
T5	2140	0	0	0
T6	0	172	0	0
T7	0	47	0	0
T9	6008	667	0	0
T10	0	1225	0	0
T11	0	723	0	0
T12	0	2435	0	0
T16	820	0	0	0
T18	0	1484	0	0
T19	0	3209	0	0
T20	0	1351	0	0
T21	6024	0	0	0
T22	6792	0	0	0
T23	506	0	0	0
T27	7018	0	0	0
T28	0	3837	0	0
T100	9870	0	0	0
T101	799484	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433279524	432906858	0	0
T1	7898	7768	0	0
T2	4312	4184	0	0
T3	1762498	1762468	0	0
T4	1570	1292	0	0
T5	84776	42964	0	0
T9	6008	5886	0	0
T16	2562	2276	0	0
T21	6024	5858	0	0
T22	6792	6616	0	0
T23	2376	2050	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433279524	432906858	0	0
T1	7898	7768	0	0
T2	4312	4184	0	0
T3	1762498	1762468	0	0
T4	1570	1292	0	0
T5	84776	42964	0	0
T9	6008	5886	0	0
T16	2562	2276	0	0
T21	6024	5858	0	0
T22	6792	6616	0	0
T23	2376	2050	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433279524	432906858	0	0
T1	7898	7768	0	0
T2	4312	4184	0	0
T3	1762498	1762468	0	0
T4	1570	1292	0	0
T5	84776	42964	0	0
T9	6008	5886	0	0
T16	2562	2276	0	0
T21	6024	5858	0	0
T22	6792	6616	0	0
T23	2376	2050	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	432763998	1080652	0	0
T4	1570	304	0	0
T5	2140	0	0	0
T9	6008	667	0	0
T10	0	1225	0	0
T11	0	723	0	0
T16	2562	24	0	0
T18	0	1484	0	0
T19	0	1591	0	0
T20	0	1351	0	0
T21	6024	0	0	0
T22	6792	0	0	0
T23	2376	0	0	0
T25	0	2278	0	0
T27	7018	0	0	0
T28	0	3837	0	0
T99	0	285	0	0
T100	9870	0	0	0
T101	799484	0	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T15,T19
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T9,T4,T5

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T106,T107
1	1	0	Not Covered
1	1	1	Covered	T9,T4,T10

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T108,T109,T137
1	0	1	Covered	T9,T4,T5
1	1	0	Not Covered
1	1	1	Covered	T10,T11,T18

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T9,T4,T10
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	216199029	491075	0	0
DepthKnown_A	216639762	216453429	0	0
RvalidKnown_A	216639762	216453429	0	0
WreadyKnown_A	216639762	216453429	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	216381999	535124	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216199029	491075	0	0
T4	120	0	0	0
T5	1070	0	0	0
T6	0	56	0	0
T7	0	11	0	0
T9	3004	341	0	0
T10	0	582	0	0
T11	0	357	0	0
T12	0	1202	0	0
T16	410	0	0	0
T18	0	728	0	0
T19	0	1591	0	0
T20	0	664	0	0
T21	3012	0	0	0
T22	3396	0	0	0
T23	253	0	0	0
T27	3509	0	0	0
T28	0	1865	0	0
T100	4935	0	0	0
T101	399742	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216639762	216453429	0	0
T1	3949	3884	0	0
T2	2156	2092	0	0
T3	881249	881234	0	0
T4	785	646	0	0
T5	42388	21482	0	0
T9	3004	2943	0	0
T16	1281	1138	0	0
T21	3012	2929	0	0
T22	3396	3308	0	0
T23	1188	1025	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216639762	216453429	0	0
T1	3949	3884	0	0
T2	2156	2092	0	0
T3	881249	881234	0	0
T4	785	646	0	0
T5	42388	21482	0	0
T9	3004	2943	0	0
T16	1281	1138	0	0
T21	3012	2929	0	0
T22	3396	3308	0	0
T23	1188	1025	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216639762	216453429	0	0
T1	3949	3884	0	0
T2	2156	2092	0	0
T3	881249	881234	0	0
T4	785	646	0	0
T5	42388	21482	0	0
T9	3004	2943	0	0
T16	1281	1138	0	0
T21	3012	2929	0	0
T22	3396	3308	0	0
T23	1188	1025	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	216381999	535124	0	0
T4	785	158	0	0
T5	1070	0	0	0
T9	3004	341	0	0
T10	0	582	0	0
T11	0	357	0	0
T16	1281	0	0	0
T18	0	728	0	0
T19	0	1591	0	0
T20	0	664	0	0
T21	3012	0	0	0
T22	3396	0	0	0
T23	1188	0	0	0
T25	0	1145	0	0
T27	3509	0	0	0
T28	0	1865	0	0
T99	0	148	0	0
T100	4935	0	0	0
T101	399742	0	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T16,T10,T15
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T9,T4,T5

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T16,T138,T139
1	1	0	Not Covered
1	1	1	Covered	T9,T4,T16

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T110
1	0	1	Covered	T9,T4,T5
1	1	0	Not Covered
1	1	1	Covered	T9,T10,T11

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T9,T4,T16
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	216199029	501138	0	0
DepthKnown_A	216639762	216453429	0	0
RvalidKnown_A	216639762	216453429	0	0
WreadyKnown_A	216639762	216453429	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	216381999	545528	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216199029	501138	0	0
T4	120	0	0	0
T5	1070	0	0	0
T6	0	116	0	0
T7	0	36	0	0
T9	3004	326	0	0
T10	0	643	0	0
T11	0	366	0	0
T12	0	1233	0	0
T16	410	0	0	0
T18	0	756	0	0
T19	0	1618	0	0
T20	0	687	0	0
T21	3012	0	0	0
T22	3396	0	0	0
T23	253	0	0	0
T27	3509	0	0	0
T28	0	1972	0	0
T100	4935	0	0	0
T101	399742	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216639762	216453429	0	0
T1	3949	3884	0	0
T2	2156	2092	0	0
T3	881249	881234	0	0
T4	785	646	0	0
T5	42388	21482	0	0
T9	3004	2943	0	0
T16	1281	1138	0	0
T21	3012	2929	0	0
T22	3396	3308	0	0
T23	1188	1025	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216639762	216453429	0	0
T1	3949	3884	0	0
T2	2156	2092	0	0
T3	881249	881234	0	0
T4	785	646	0	0
T5	42388	21482	0	0
T9	3004	2943	0	0
T16	1281	1138	0	0
T21	3012	2929	0	0
T22	3396	3308	0	0
T23	1188	1025	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216639762	216453429	0	0
T1	3949	3884	0	0
T2	2156	2092	0	0
T3	881249	881234	0	0
T4	785	646	0	0
T5	42388	21482	0	0
T9	3004	2943	0	0
T16	1281	1138	0	0
T21	3012	2929	0	0
T22	3396	3308	0	0
T23	1188	1025	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	216381999	545528	0	0
T4	785	146	0	0
T5	1070	0	0	0
T9	3004	326	0	0
T10	0	643	0	0
T11	0	366	0	0
T16	1281	24	0	0
T18	0	756	0	0
T20	0	687	0	0
T21	3012	0	0	0
T22	3396	0	0	0
T23	1188	0	0	0
T25	0	1133	0	0
T27	3509	0	0	0
T28	0	1972	0	0
T99	0	137	0	0
T100	4935	0	0	0
T101	399742	0	0	0