Unified Coverage Report :: Module :: edn

Module : edn

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	94.44		83.33	100.00			100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.86	98.24	93.80	97.02	83.72	96.62	99.77

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
edn_csr_assert	100.00						100.00
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_edn_core	92.80	99.92	92.46	82.54	83.72	99.28	98.88
u_edn_cov_if	25.00	50.00	0.00
u_reg	96.95	95.02	97.57	100.00		92.16	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Cond Coverage for Module : edn

	Total	Covered	Percent
Conditions	6	5	83.33
Logical	6	5	83.33
Non-Logical	0	0
Event	0	0

 LINE       98
 EXPRESSION (alert[0] || intg_err_alert[0])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T21,T19,T23

 LINE       98
 EXPRESSION (alert[1] || intg_err_alert[1])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T15,T16,T17
1	0	Covered	T4,T5,T24

---

Toggle Coverage for Module : edn

	Total	Covered	Percent
Totals	69	69	100.00
Total Bits	1172	1172	100.00
Total Bits 0->1	586	586	100.00
Total Bits 1->0	586	586	100.00

Ports	69	69	100.00
Port Bits	1172	1172	100.00
Port Bits 0->1	586	586	100.00
Port Bits 1->0	586	586	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T8	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T2,T3,T10	Yes	T2,T3,T10	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T115,T116,T117	Yes	T115,T116,T117	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T3,T8	Yes	T1,T3,T8	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T3,T8	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T3,*T8	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i[0].edn_req	Yes	Yes	T3,T9,T10	Yes	T3,T9,T10	INPUT
edn_i[1].edn_req	Yes	Yes	T8,T9,T10	Yes	T8,T9,T10	INPUT
edn_i[2].edn_req	Yes	Yes	T9,T10,T104	Yes	T9,T10,T104	INPUT
edn_i[3].edn_req	Yes	Yes	T2,T9,T10	Yes	T2,T9,T10	INPUT
edn_i[4].edn_req	Yes	Yes	T9,T10,T104	Yes	T9,T10,T104	INPUT
edn_i[5].edn_req	Yes	Yes	T4,T9,T10	Yes	T4,T9,T10	INPUT
edn_i[6].edn_req	Yes	Yes	T9,T10,T5	Yes	T9,T10,T5	INPUT
edn_o[0].edn_bus[31:0]	Yes	Yes	T3,T9,T10	Yes	T3,T9,T10	OUTPUT
edn_o[0].edn_fips	Yes	Yes	T9,T11,T24	Yes	T3,T9,T10	OUTPUT
edn_o[0].edn_ack	Yes	Yes	T3,T9,T10	Yes	T3,T9,T10	OUTPUT
edn_o[1].edn_bus[31:0]	Yes	Yes	T8,T9,T10	Yes	T8,T9,T10	OUTPUT
edn_o[1].edn_fips	Yes	Yes	T104,T118,T119	Yes	T8,T10,T104	OUTPUT
edn_o[1].edn_ack	Yes	Yes	T8,T9,T10	Yes	T8,T9,T10	OUTPUT
edn_o[2].edn_bus[31:0]	Yes	Yes	T9,T10,T104	Yes	T9,T10,T104	OUTPUT
edn_o[2].edn_fips	Yes	Yes	T10,T25,T119	Yes	T10,T25,T119	OUTPUT
edn_o[2].edn_ack	Yes	Yes	T9,T10,T104	Yes	T9,T10,T104	OUTPUT
edn_o[3].edn_bus[31:0]	Yes	Yes	T2,T9,T10	Yes	T2,T9,T10	OUTPUT
edn_o[3].edn_fips	Yes	Yes	T10,T25,T94	Yes	T2,T9,T10	OUTPUT
edn_o[3].edn_ack	Yes	Yes	T2,T9,T10	Yes	T2,T9,T10	OUTPUT
edn_o[4].edn_bus[31:0]	Yes	Yes	T9,T10,T104	Yes	T9,T10,T104	OUTPUT
edn_o[4].edn_fips	Yes	Yes	T9,T10,T104	Yes	T9,T10,T104	OUTPUT
edn_o[4].edn_ack	Yes	Yes	T9,T10,T104	Yes	T9,T10,T104	OUTPUT
edn_o[5].edn_bus[31:0]	Yes	Yes	T9,T104,T25	Yes	T9,T10,T104	OUTPUT
edn_o[5].edn_fips	Yes	Yes	T104,T120,T121	Yes	T9,T10,T104	OUTPUT
edn_o[5].edn_ack	Yes	Yes	T9,T10,T104	Yes	T9,T10,T104	OUTPUT
edn_o[6].edn_bus[31:0]	Yes	Yes	T9,T10,T25	Yes	T9,T10,T104	OUTPUT
edn_o[6].edn_fips	Yes	Yes	T25,T109,T122	Yes	T10,T123,T25	OUTPUT
edn_o[6].edn_ack	Yes	Yes	T9,T10,T5	Yes	T9,T10,T5	OUTPUT
csrng_cmd_o.genbits_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_bus[31:0]	Yes	Yes	T1,T2,T8	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_i.genbits_bus[127:0]	Yes	Yes	T8,T9,T10	Yes	T8,T9,T10	INPUT
csrng_cmd_i.genbits_fips	Yes	Yes	T8,T9,T10	Yes	T8,T9,T10	INPUT
csrng_cmd_i.genbits_valid	Yes	Yes	T2,T3,T8	Yes	T2,T3,T8	INPUT
csrng_cmd_i.csrng_rsp_sts[2:0]	Yes	Yes	T19,T30,T67	Yes	T19,T30,T67	INPUT
csrng_cmd_i.csrng_rsp_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_req_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T18,T21,T19	Yes	T18,T21,T19	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T4,T18,T5	Yes	T4,T18,T5	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T18,T21,T19	Yes	T18,T21,T19	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T4,T18,T5	Yes	T4,T18,T5	OUTPUT
intr_edn_cmd_req_done_o	Yes	Yes	T99,T115,T124	Yes	T99,T115,T124	OUTPUT
intr_edn_fatal_err_o	Yes	Yes	T5,T24,T99	Yes	T5,T24,T99	OUTPUT

*Tests covering at least one bit in the range

---

Assert Coverage for Module : edn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	47	47	100.00	47	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	47	47	100.00	47	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxKnownO_A	231613028	231433921	0	0
CsrngAppIfOut_A	231613028	231433921	0	0
FpvSecCmCntAlertCheck_A	231613028	118	0	0
FpvSecCmGenCmdFifoRptrCheck_A	231613028	80	0	0
FpvSecCmGenCmdFifoWptrCheck_A	231613028	80	0	0
FpvSecCmMainFsmCheck_A	231613028	80	0	0
FpvSecCmRegWeOnehotCheck_A	231613028	80	0	0
FpvSecCmResCmdFifoRptrCheck_A	231613028	80	0	0
FpvSecCmResCmdFifoWptrCheck_A	231613028	80	0	0
IntrEdnCmdReqDoneKnownO_A	231613028	231433921	0	0
TlAReadyKnownO_A	231613028	231433921	0	0
TlDValidKnownO_A	231613028	231433921	0	0
gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A	231613028	80	0	0
gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A	231613028	80	0	0
gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A	231613028	80	0	0
gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A	231613028	80	0	0
gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A	231613028	80	0	0
gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A	231613028	80	0	0
gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A	231613028	80	0	0
gen_edn_if_asserts[0].EdnDataStableDisable_A	231613028	535458	0	318
gen_edn_if_asserts[0].EdnDataStable_A	231613028	78377	0	355
gen_edn_if_asserts[0].EdnEndPointOut_A	231613028	231433921	0	0
gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A	231613028	157484	0	0
gen_edn_if_asserts[1].EdnDataStableDisable_A	231613028	535458	0	318
gen_edn_if_asserts[1].EdnDataStable_A	231613028	6735	0	110
gen_edn_if_asserts[1].EdnEndPointOut_A	231613028	231433921	0	0
gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A	231613028	157484	0	0
gen_edn_if_asserts[2].EdnDataStableDisable_A	231613028	535458	0	318
gen_edn_if_asserts[2].EdnDataStable_A	231613028	4427	0	111
gen_edn_if_asserts[2].EdnEndPointOut_A	231613028	231433921	0	0
gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A	231613028	157484	0	0
gen_edn_if_asserts[3].EdnDataStableDisable_A	231613028	535458	0	318
gen_edn_if_asserts[3].EdnDataStable_A	231613028	2675	0	93
gen_edn_if_asserts[3].EdnEndPointOut_A	231613028	231433921	0	0
gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A	231613028	157484	0	0
gen_edn_if_asserts[4].EdnDataStableDisable_A	231613028	535458	0	318
gen_edn_if_asserts[4].EdnDataStable_A	231613028	52667	0	86
gen_edn_if_asserts[4].EdnEndPointOut_A	231613028	231433921	0	0
gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A	231613028	157484	0	0
gen_edn_if_asserts[5].EdnDataStableDisable_A	231613028	535458	0	318
gen_edn_if_asserts[5].EdnDataStable_A	231613028	3291	0	80
gen_edn_if_asserts[5].EdnEndPointOut_A	231613028	231433921	0	0
gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A	231613028	157484	0	0
gen_edn_if_asserts[6].EdnDataStableDisable_A	231613028	535458	0	318
gen_edn_if_asserts[6].EdnDataStable_A	231613028	4247	0	76
gen_edn_if_asserts[6].EdnEndPointOut_A	231613028	231433921	0	0
gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A	231613028	157484	0	0

AlertTxKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	231613028	231433921	0	0
T1	1827	1671	0	0
T2	1013	928	0	0
T3	1395	1320	0	0
T4	1365	1237	0	0
T5	1986	1844	0	0
T8	2363	2284	0	0
T9	2251	2166	0	0
T10	3684	3587	0	0
T11	2064	1979	0	0
T18	1351	1262	0	0

CsrngAppIfOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	231613028	231433921	0	0
T1	1827	1671	0	0
T2	1013	928	0	0
T3	1395	1320	0	0
T4	1365	1237	0	0
T5	1986	1844	0	0
T8	2363	2284	0	0
T9	2251	2166	0	0
T10	3684	3587	0	0
T11	2064	1979	0	0
T18	1351	1262	0	0

FpvSecCmCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	231613028	118	0	0
T6	1787	1	0	0
T13	2308	1	0	0
T14	0	1	0	0
T15	0	20	0	0
T23	2423	0	0	0
T37	0	1	0	0
T62	0	1	0	0
T73	0	1	0	0
T98	0	1	0	0
T121	2732	0	0	0
T124	27951	0	0	0
T125	0	1	0	0
T126	0	1	0	0
T127	1445	0	0	0
T128	5709	0	0	0
T129	3078	0	0	0
T130	3335	0	0	0
T131	2498	0	0	0

FpvSecCmGenCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	231613028	80	0	0
T15	45016	20	0	0
T16	0	20	0	0
T17	0	20	0	0
T32	1482	0	0	0
T40	2643	0	0	0
T43	1176	0	0	0
T67	2022	0	0	0
T73	1082	0	0	0
T125	1173	0	0	0
T126	2596	0	0	0
T132	0	10	0	0
T133	0	10	0	0
T134	2974	0	0	0
T135	2367	0	0	0

FpvSecCmGenCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	231613028	80	0	0
T15	45016	20	0	0
T16	0	20	0	0
T17	0	20	0	0
T32	1482	0	0	0
T40	2643	0	0	0
T43	1176	0	0	0
T67	2022	0	0	0
T73	1082	0	0	0
T125	1173	0	0	0
T126	2596	0	0	0
T132	0	10	0	0
T133	0	10	0	0
T134	2974	0	0	0
T135	2367	0	0	0

FpvSecCmMainFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	231613028	80	0	0
T15	45016	20	0	0
T16	0	20	0	0
T17	0	20	0	0
T32	1482	0	0	0
T40	2643	0	0	0
T43	1176	0	0	0
T67	2022	0	0	0
T73	1082	0	0	0
T125	1173	0	0	0
T126	2596	0	0	0
T132	0	10	0	0
T133	0	10	0	0
T134	2974	0	0	0
T135	2367	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	231613028	80	0	0
T15	45016	20	0	0
T16	0	20	0	0
T17	0	20	0	0
T32	1482	0	0	0
T40	2643	0	0	0
T43	1176	0	0	0
T67	2022	0	0	0
T73	1082	0	0	0
T125	1173	0	0	0
T126	2596	0	0	0
T132	0	10	0	0
T133	0	10	0	0
T134	2974	0	0	0
T135	2367	0	0	0

FpvSecCmResCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	231613028	80	0	0
T15	45016	20	0	0
T16	0	20	0	0
T17	0	20	0	0
T32	1482	0	0	0
T40	2643	0	0	0
T43	1176	0	0	0
T67	2022	0	0	0
T73	1082	0	0	0
T125	1173	0	0	0
T126	2596	0	0	0
T132	0	10	0	0
T133	0	10	0	0
T134	2974	0	0	0
T135	2367	0	0	0

FpvSecCmResCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	231613028	80	0	0
T15	45016	20	0	0
T16	0	20	0	0
T17	0	20	0	0
T32	1482	0	0	0
T40	2643	0	0	0
T43	1176	0	0	0
T67	2022	0	0	0
T73	1082	0	0	0
T125	1173	0	0	0
T126	2596	0	0	0
T132	0	10	0	0
T133	0	10	0	0
T134	2974	0	0	0
T135	2367	0	0	0

IntrEdnCmdReqDoneKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	231613028	231433921	0	0
T1	1827	1671	0	0
T2	1013	928	0	0
T3	1395	1320	0	0
T4	1365	1237	0	0
T5	1986	1844	0	0
T8	2363	2284	0	0
T9	2251	2166	0	0
T10	3684	3587	0	0
T11	2064	1979	0	0
T18	1351	1262	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	231613028	231433921	0	0
T1	1827	1671	0	0
T2	1013	928	0	0
T3	1395	1320	0	0
T4	1365	1237	0	0
T5	1986	1844	0	0
T8	2363	2284	0	0
T9	2251	2166	0	0
T10	3684	3587	0	0
T11	2064	1979	0	0
T18	1351	1262	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	231613028	231433921	0	0
T1	1827	1671	0	0
T2	1013	928	0	0
T3	1395	1320	0	0
T4	1365	1237	0	0
T5	1986	1844	0	0
T8	2363	2284	0	0
T9	2251	2166	0	0
T10	3684	3587	0	0
T11	2064	1979	0	0
T18	1351	1262	0	0

gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	231613028	80	0	0
T15	45016	20	0	0
T16	0	20	0	0
T17	0	20	0	0
T32	1482	0	0	0
T40	2643	0	0	0
T43	1176	0	0	0
T67	2022	0	0	0
T73	1082	0	0	0
T125	1173	0	0	0
T126	2596	0	0	0
T132	0	10	0	0
T133	0	10	0	0
T134	2974	0	0	0
T135	2367	0	0	0

gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	231613028	80	0	0
T15	45016	20	0	0
T16	0	20	0	0
T17	0	20	0	0
T32	1482	0	0	0
T40	2643	0	0	0
T43	1176	0	0	0
T67	2022	0	0	0
T73	1082	0	0	0
T125	1173	0	0	0
T126	2596	0	0	0
T132	0	10	0	0
T133	0	10	0	0
T134	2974	0	0	0
T135	2367	0	0	0

gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	231613028	80	0	0
T15	45016	20	0	0
T16	0	20	0	0
T17	0	20	0	0
T32	1482	0	0	0
T40	2643	0	0	0
T43	1176	0	0	0
T67	2022	0	0	0
T73	1082	0	0	0
T125	1173	0	0	0
T126	2596	0	0	0
T132	0	10	0	0
T133	0	10	0	0
T134	2974	0	0	0
T135	2367	0	0	0

gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	231613028	80	0	0
T15	45016	20	0	0
T16	0	20	0	0
T17	0	20	0	0
T32	1482	0	0	0
T40	2643	0	0	0
T43	1176	0	0	0
T67	2022	0	0	0
T73	1082	0	0	0
T125	1173	0	0	0
T126	2596	0	0	0
T132	0	10	0	0
T133	0	10	0	0
T134	2974	0	0	0
T135	2367	0	0	0

gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	231613028	80	0	0
T15	45016	20	0	0
T16	0	20	0	0
T17	0	20	0	0
T32	1482	0	0	0
T40	2643	0	0	0
T43	1176	0	0	0
T67	2022	0	0	0
T73	1082	0	0	0
T125	1173	0	0	0
T126	2596	0	0	0
T132	0	10	0	0
T133	0	10	0	0
T134	2974	0	0	0
T135	2367	0	0	0

gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	231613028	80	0	0
T15	45016	20	0	0
T16	0	20	0	0
T17	0	20	0	0
T32	1482	0	0	0
T40	2643	0	0	0
T43	1176	0	0	0
T67	2022	0	0	0
T73	1082	0	0	0
T125	1173	0	0	0
T126	2596	0	0	0
T132	0	10	0	0
T133	0	10	0	0
T134	2974	0	0	0
T135	2367	0	0	0

gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	231613028	80	0	0
T15	45016	20	0	0
T16	0	20	0	0
T17	0	20	0	0
T32	1482	0	0	0
T40	2643	0	0	0
T43	1176	0	0	0
T67	2022	0	0	0
T73	1082	0	0	0
T125	1173	0	0	0
T126	2596	0	0	0
T132	0	10	0	0
T133	0	10	0	0
T134	2974	0	0	0
T135	2367	0	0	0

gen_edn_if_asserts[0].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	231613028	535458	0	318
T1	1827	25	0	0
T2	1013	67	0	0
T3	1395	10	0	0
T4	1365	899	0	0
T5	1986	989	0	0
T8	2363	1164	0	2
T9	2251	69	0	0
T10	3684	339	0	0
T11	2064	85	0	0
T15	0	0	0	2
T18	1351	1260	0	2
T22	0	0	0	2
T29	0	0	0	2
T53	0	0	0	2
T99	0	0	0	2
T115	0	0	0	2
T136	0	0	0	2
T137	0	0	0	2

gen_edn_if_asserts[0].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	231613028	78377	0	355
T3	1395	3	0	1
T4	1365	0	0	0
T5	1986	0	0	0
T8	2363	0	0	0
T9	2251	31	0	1
T10	3684	3	0	1
T11	2064	61	0	1
T18	1351	0	0	0
T19	0	0	0	1
T20	0	45	0	1
T21	0	0	0	1
T24	1154	1	0	0
T99	0	12	0	0
T100	0	1	0	0
T104	2620	0	0	0
T105	0	3	0	1
T138	0	15	0	1
T139	0	0	0	1

gen_edn_if_asserts[0].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	231613028	231433921	0	0
T1	1827	1671	0	0
T2	1013	928	0	0
T3	1395	1320	0	0
T4	1365	1237	0	0
T5	1986	1844	0	0
T8	2363	2284	0	0
T9	2251	2166	0	0
T10	3684	3587	0	0
T11	2064	1979	0	0
T18	1351	1262	0	0

gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	231613028	157484	0	0
T4	1365	541	0	0
T5	1986	1070	0	0
T6	0	665	0	0
T9	2251	0	0	0
T10	3684	0	0	0
T11	2064	0	0	0
T13	0	1151	0	0
T14	0	1151	0	0
T18	1351	0	0	0
T24	1154	520	0	0
T99	20531	0	0	0
T100	0	16	0	0
T102	0	1072	0	0
T104	2620	0	0	0
T105	1662	0	0	0
T109	0	22	0	0
T110	0	29	0	0

gen_edn_if_asserts[1].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	231613028	535458	0	318
T1	1827	25	0	0
T2	1013	67	0	0
T3	1395	10	0	0
T4	1365	899	0	0
T5	1986	989	0	0
T8	2363	1164	0	2
T9	2251	69	0	0
T10	3684	339	0	0
T11	2064	85	0	0
T15	0	0	0	2
T18	1351	1260	0	2
T22	0	0	0	2
T29	0	0	0	2
T53	0	0	0	2
T99	0	0	0	2
T115	0	0	0	2
T136	0	0	0	2
T137	0	0	0	2

gen_edn_if_asserts[1].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	231613028	6735	0	110
T4	1365	0	0	0
T5	1986	0	0	0
T8	2363	4	0	0
T9	2251	3	0	1
T10	3684	3	0	1
T11	2064	0	0	0
T18	1351	0	0	0
T24	1154	0	0	0
T94	0	3	0	1
T99	20531	0	0	0
T104	2620	45	0	1
T118	0	5	0	1
T119	0	45	0	1
T120	0	3	0	1
T121	0	3	0	1
T129	0	0	0	1
T140	0	12	0	1

gen_edn_if_asserts[1].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	231613028	231433921	0	0
T1	1827	1671	0	0
T2	1013	928	0	0
T3	1395	1320	0	0
T4	1365	1237	0	0
T5	1986	1844	0	0
T8	2363	2284	0	0
T9	2251	2166	0	0
T10	3684	3587	0	0
T11	2064	1979	0	0
T18	1351	1262	0	0

gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	231613028	157484	0	0
T4	1365	541	0	0
T5	1986	1070	0	0
T6	0	665	0	0
T9	2251	0	0	0
T10	3684	0	0	0
T11	2064	0	0	0
T13	0	1151	0	0
T14	0	1151	0	0
T18	1351	0	0	0
T24	1154	520	0	0
T99	20531	0	0	0
T100	0	16	0	0
T102	0	1072	0	0
T104	2620	0	0	0
T105	1662	0	0	0
T109	0	22	0	0
T110	0	29	0	0

gen_edn_if_asserts[2].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	231613028	535458	0	318
T1	1827	25	0	0
T2	1013	67	0	0
T3	1395	10	0	0
T4	1365	899	0	0
T5	1986	989	0	0
T8	2363	1164	0	2
T9	2251	69	0	0
T10	3684	339	0	0
T11	2064	85	0	0
T15	0	0	0	2
T18	1351	1260	0	2
T22	0	0	0	2
T29	0	0	0	2
T53	0	0	0	2
T99	0	0	0	2
T115	0	0	0	2
T136	0	0	0	2
T137	0	0	0	2

gen_edn_if_asserts[2].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	231613028	4427	0	111
T5	1986	0	0	0
T9	2251	3	0	1
T10	3684	44	0	1
T11	2064	0	0	0
T18	1351	0	0	0
T22	2900	0	0	0
T23	0	4	0	1
T24	1154	0	0	0
T25	0	25	0	1
T99	20531	0	0	0
T104	2620	3	0	1
T105	1662	0	0	0
T119	0	42	0	1
T121	0	6	0	1
T123	0	3	0	1
T139	0	22	0	1
T140	0	3	0	1

gen_edn_if_asserts[2].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	231613028	231433921	0	0
T1	1827	1671	0	0
T2	1013	928	0	0
T3	1395	1320	0	0
T4	1365	1237	0	0
T5	1986	1844	0	0
T8	2363	2284	0	0
T9	2251	2166	0	0
T10	3684	3587	0	0
T11	2064	1979	0	0
T18	1351	1262	0	0

gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	231613028	157484	0	0
T4	1365	541	0	0
T5	1986	1070	0	0
T6	0	665	0	0
T9	2251	0	0	0
T10	3684	0	0	0
T11	2064	0	0	0
T13	0	1151	0	0
T14	0	1151	0	0
T18	1351	0	0	0
T24	1154	520	0	0
T99	20531	0	0	0
T100	0	16	0	0
T102	0	1072	0	0
T104	2620	0	0	0
T105	1662	0	0	0
T109	0	22	0	0
T110	0	29	0	0

gen_edn_if_asserts[3].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	231613028	535458	0	318
T1	1827	25	0	0
T2	1013	67	0	0
T3	1395	10	0	0
T4	1365	899	0	0
T5	1986	989	0	0
T8	2363	1164	0	2
T9	2251	69	0	0
T10	3684	339	0	0
T11	2064	85	0	0
T15	0	0	0	2
T18	1351	1260	0	2
T22	0	0	0	2
T29	0	0	0	2
T53	0	0	0	2
T99	0	0	0	2
T115	0	0	0	2
T136	0	0	0	2
T137	0	0	0	2

gen_edn_if_asserts[3].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	231613028	2675	0	93
T2	1013	3	0	1
T3	1395	0	0	0
T4	1365	0	0	0
T5	1986	0	0	0
T8	2363	0	0	0
T9	2251	33	0	1
T10	3684	32	0	1
T11	2064	0	0	0
T18	1351	0	0	0
T22	0	4	0	0
T25	0	39	0	1
T94	0	11	0	1
T104	2620	3	0	1
T119	0	37	0	1
T120	0	0	0	1
T139	0	3	0	1
T140	0	49	0	1

gen_edn_if_asserts[3].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	231613028	231433921	0	0
T1	1827	1671	0	0
T2	1013	928	0	0
T3	1395	1320	0	0
T4	1365	1237	0	0
T5	1986	1844	0	0
T8	2363	2284	0	0
T9	2251	2166	0	0
T10	3684	3587	0	0
T11	2064	1979	0	0
T18	1351	1262	0	0

gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	231613028	157484	0	0
T4	1365	541	0	0
T5	1986	1070	0	0
T6	0	665	0	0
T9	2251	0	0	0
T10	3684	0	0	0
T11	2064	0	0	0
T13	0	1151	0	0
T14	0	1151	0	0
T18	1351	0	0	0
T24	1154	520	0	0
T99	20531	0	0	0
T100	0	16	0	0
T102	0	1072	0	0
T104	2620	0	0	0
T105	1662	0	0	0
T109	0	22	0	0
T110	0	29	0	0

gen_edn_if_asserts[4].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	231613028	535458	0	318
T1	1827	25	0	0
T2	1013	67	0	0
T3	1395	10	0	0
T4	1365	899	0	0
T5	1986	989	0	0
T8	2363	1164	0	2
T9	2251	69	0	0
T10	3684	339	0	0
T11	2064	85	0	0
T15	0	0	0	2
T18	1351	1260	0	2
T22	0	0	0	2
T29	0	0	0	2
T53	0	0	0	2
T99	0	0	0	2
T115	0	0	0	2
T136	0	0	0	2
T137	0	0	0	2

gen_edn_if_asserts[4].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	231613028	52667	0	86
T5	1986	0	0	0
T9	2251	24	0	1
T10	3684	26	0	1
T11	2064	0	0	0
T18	1351	0	0	0
T21	0	4	0	0
T22	2900	0	0	0
T24	1154	0	0	0
T25	0	54	0	1
T99	20531	0	0	0
T104	2620	30	0	1
T105	1662	0	0	0
T119	0	3	0	1
T120	0	3	0	1
T121	0	3	0	1
T129	0	35	0	1
T130	0	0	0	1
T140	0	19	0	1

gen_edn_if_asserts[4].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	231613028	231433921	0	0
T1	1827	1671	0	0
T2	1013	928	0	0
T3	1395	1320	0	0
T4	1365	1237	0	0
T5	1986	1844	0	0
T8	2363	2284	0	0
T9	2251	2166	0	0
T10	3684	3587	0	0
T11	2064	1979	0	0
T18	1351	1262	0	0

gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	231613028	157484	0	0
T4	1365	541	0	0
T5	1986	1070	0	0
T6	0	665	0	0
T9	2251	0	0	0
T10	3684	0	0	0
T11	2064	0	0	0
T13	0	1151	0	0
T14	0	1151	0	0
T18	1351	0	0	0
T24	1154	520	0	0
T99	20531	0	0	0
T100	0	16	0	0
T102	0	1072	0	0
T104	2620	0	0	0
T105	1662	0	0	0
T109	0	22	0	0
T110	0	29	0	0

gen_edn_if_asserts[5].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	231613028	535458	0	318
T1	1827	25	0	0
T2	1013	67	0	0
T3	1395	10	0	0
T4	1365	899	0	0
T5	1986	989	0	0
T8	2363	1164	0	2
T9	2251	69	0	0
T10	3684	339	0	0
T11	2064	85	0	0
T15	0	0	0	2
T18	1351	1260	0	2
T22	0	0	0	2
T29	0	0	0	2
T53	0	0	0	2
T99	0	0	0	2
T115	0	0	0	2
T136	0	0	0	2
T137	0	0	0	2

gen_edn_if_asserts[5].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	231613028	3291	0	80
T5	1986	0	0	0
T9	2251	3	0	1
T10	3684	3	0	1
T11	2064	0	0	0
T18	1351	0	0	0
T22	2900	0	0	0
T24	1154	0	0	0
T25	0	3	0	1
T99	20531	0	0	0
T104	2620	30	0	1
T105	1662	0	0	0
T119	0	3	0	1
T120	0	891	0	1
T121	0	63	0	1
T130	0	11	0	1
T140	0	3	0	1
T141	0	3	0	1

gen_edn_if_asserts[5].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	231613028	231433921	0	0
T1	1827	1671	0	0
T2	1013	928	0	0
T3	1395	1320	0	0
T4	1365	1237	0	0
T5	1986	1844	0	0
T8	2363	2284	0	0
T9	2251	2166	0	0
T10	3684	3587	0	0
T11	2064	1979	0	0
T18	1351	1262	0	0

gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	231613028	157484	0	0
T4	1365	541	0	0
T5	1986	1070	0	0
T6	0	665	0	0
T9	2251	0	0	0
T10	3684	0	0	0
T11	2064	0	0	0
T13	0	1151	0	0
T14	0	1151	0	0
T18	1351	0	0	0
T24	1154	520	0	0
T99	20531	0	0	0
T100	0	16	0	0
T102	0	1072	0	0
T104	2620	0	0	0
T105	1662	0	0	0
T109	0	22	0	0
T110	0	29	0	0

gen_edn_if_asserts[6].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	231613028	535458	0	318
T1	1827	25	0	0
T2	1013	67	0	0
T3	1395	10	0	0
T4	1365	899	0	0
T5	1986	989	0	0
T8	2363	1164	0	2
T9	2251	69	0	0
T10	3684	339	0	0
T11	2064	85	0	0
T15	0	0	0	2
T18	1351	1260	0	2
T22	0	0	0	2
T29	0	0	0	2
T53	0	0	0	2
T99	0	0	0	2
T115	0	0	0	2
T136	0	0	0	2
T137	0	0	0	2

gen_edn_if_asserts[6].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	231613028	4247	0	76
T5	1986	1	0	0
T9	2251	9	0	1
T10	3684	15	0	1
T11	2064	0	0	0
T18	1351	0	0	0
T22	2900	1	0	0
T24	1154	0	0	0
T25	0	31	0	1
T99	20531	0	0	0
T104	2620	3	0	1
T105	1662	0	0	0
T109	0	1	0	0
T121	0	0	0	1
T122	0	1081	0	1
T123	0	3	0	1
T129	0	0	0	1
T130	0	0	0	1
T140	0	3	0	1

gen_edn_if_asserts[6].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	231613028	231433921	0	0
T1	1827	1671	0	0
T2	1013	928	0	0
T3	1395	1320	0	0
T4	1365	1237	0	0
T5	1986	1844	0	0
T8	2363	2284	0	0
T9	2251	2166	0	0
T10	3684	3587	0	0
T11	2064	1979	0	0
T18	1351	1262	0	0

gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	231613028	157484	0	0
T4	1365	541	0	0
T5	1986	1070	0	0
T6	0	665	0	0
T9	2251	0	0	0
T10	3684	0	0	0
T11	2064	0	0	0
T13	0	1151	0	0
T14	0	1151	0	0
T18	1351	0	0	0
T24	1154	520	0	0
T99	20531	0	0	0
T100	0	16	0	0
T102	0	1072	0	0
T104	2620	0	0	0
T105	1662	0	0	0
T109	0	22	0	0
T110	0	29	0	0