Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44		83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	232089016	10409877	0	0
boot_gen_cmd_rd_A	232089016	63369	0	0
boot_ins_cmd_rd_A	232089016	73971	0	0
ctrl_rd_A	232089016	64997	0	0
err_code_test_rd_A	232089016	73556	0	0
intr_enable_rd_A	232089016	70846	0	0
max_num_reqs_between_reseeds_rd_A	232089016	65278	0	0
regwen_rd_A	232089016	73592	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	232089016	10409877	0	0
T6	1787	0	0	0
T13	2308	0	0	0
T23	2423	0	0	0
T115	499476	277415	0	0
T116	0	358948	0	0
T117	0	279305	0	0
T120	5573	0	0	0
T121	2732	0	0	0
T127	1445	0	0	0
T128	5709	0	0	0
T140	2208	0	0	0
T147	6629	0	0	0
T152	0	466698	0	0
T188	0	411158	0	0
T189	0	20496	0	0
T190	0	31927	0	0
T191	0	310347	0	0
T192	0	74076	0	0
T193	0	127461	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	232089016	63369	0	0
T145	2028	0	0	0
T166	1442	0	0	0
T189	607011	718	0	0
T190	859468	963	0	0
T192	0	2420	0	0
T194	0	8349	0	0
T195	0	5198	0	0
T196	0	4435	0	0
T197	0	10234	0	0
T198	0	2752	0	0
T199	0	2442	0	0
T200	0	3817	0	0
T201	6535	0	0	0
T202	2316	0	0	0
T203	7320	0	0	0
T204	1875	0	0	0
T205	4888	0	0	0
T206	6670	0	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	232089016	73971	0	0
T145	2028	0	0	0
T166	1442	0	0	0
T189	607011	837	0	0
T190	859468	981	0	0
T192	0	2416	0	0
T194	0	9495	0	0
T195	0	6115	0	0
T196	0	5020	0	0
T197	0	11711	0	0
T198	0	3201	0	0
T199	0	2977	0	0
T200	0	4714	0	0
T201	6535	0	0	0
T202	2316	0	0	0
T203	7320	0	0	0
T204	1875	0	0	0
T205	4888	0	0	0
T206	6670	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	232089016	64997	0	0
T6	1787	0	0	0
T13	2308	0	0	0
T14	0	2	0	0
T23	2423	0	0	0
T106	0	7	0	0
T107	0	9	0	0
T115	499476	0	0	0
T120	5573	0	0	0
T121	2732	0	0	0
T127	1445	0	0	0
T128	0	1	0	0
T140	2208	0	0	0
T146	3178	3	0	0
T147	6629	0	0	0
T189	0	680	0	0
T190	0	1043	0	0
T192	0	2249	0	0
T207	0	7	0	0
T208	0	5	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	232089016	73556	0	0
T145	2028	0	0	0
T166	1442	0	0	0
T189	607011	825	0	0
T190	859468	1124	0	0
T192	0	2587	0	0
T194	0	9489	0	0
T195	0	6038	0	0
T196	0	5055	0	0
T197	0	12310	0	0
T198	0	3022	0	0
T199	0	2630	0	0
T200	0	4743	0	0
T201	6535	0	0	0
T202	2316	0	0	0
T203	7320	0	0	0
T204	1875	0	0	0
T205	4888	0	0	0
T206	6670	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	232089016	70846	0	0
T20	2344	0	0	0
T21	2585	0	0	0
T22	2900	0	0	0
T99	20531	90	0	0
T100	831	0	0	0
T102	1753	0	0	0
T105	1662	0	0	0
T118	3916	0	0	0
T123	1989	0	0	0
T138	2664	0	0	0
T161	0	22	0	0
T189	0	749	0	0
T190	0	1077	0	0
T192	0	2534	0	0
T194	0	9559	0	0
T195	0	5851	0	0
T209	0	83	0	0
T210	0	10	0	0
T211	0	39	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	232089016	65278	0	0
T145	2028	0	0	0
T166	1442	0	0	0
T189	607011	647	0	0
T190	859468	1010	0	0
T192	0	2475	0	0
T194	0	8057	0	0
T195	0	5195	0	0
T196	0	4673	0	0
T197	0	10448	0	0
T198	0	2816	0	0
T199	0	2332	0	0
T200	0	4603	0	0
T201	6535	0	0	0
T202	2316	0	0	0
T203	7320	0	0	0
T204	1875	0	0	0
T205	4888	0	0	0
T206	6670	0	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	232089016	73592	0	0
T145	2028	0	0	0
T166	1442	0	0	0
T189	607011	564	0	0
T190	859468	1009	0	0
T192	0	2619	0	0
T194	0	9391	0	0
T195	0	6087	0	0
T196	0	5061	0	0
T197	0	12065	0	0
T198	0	3075	0	0
T199	0	2867	0	0
T200	0	4586	0	0
T201	6535	0	0	0
T202	2316	0	0	0
T203	7320	0	0	0
T204	1875	0	0	0
T205	4888	0	0	0
T206	6670	0	0	0