Unified Coverage Report :: Module :: edn

Module : edn

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	94.44		83.33	100.00			100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.86	98.24	93.80	97.02	83.72	96.62	99.77

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
edn_csr_assert	100.00						100.00
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_edn_core	92.80	99.92	92.46	82.54	83.72	99.28	98.88
u_edn_cov_if	25.00	50.00	0.00
u_reg	96.95	95.02	97.57	100.00		92.16	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Cond Coverage for Module : edn

	Total	Covered	Percent
Conditions	6	5	83.33
Logical	6	5	83.33
Non-Logical	0	0
Event	0	0

 LINE       98
 EXPRESSION (alert[0] || intg_err_alert[0])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T14,T25,T26

 LINE       98
 EXPRESSION (alert[1] || intg_err_alert[1])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T16,T17,T18
1	0	Covered	T3,T4,T5

---

Toggle Coverage for Module : edn

	Total	Covered	Percent
Totals	69	69	100.00
Total Bits	1172	1172	100.00
Total Bits 0->1	586	586	100.00
Total Bits 1->0	586	586	100.00

Ports	69	69	100.00
Port Bits	1172	1172	100.00
Port Bits 0->1	586	586	100.00
Port Bits 1->0	586	586	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T3,T4,T5	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T3,T19	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T3,T8,T20	Yes	T3,T8,T20	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T3,T19	Yes	T1,T3,T19	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T99,T113,T114	Yes	T99,T113,T114	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T3,T19	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i[0].edn_req	Yes	Yes	T1,T2,T19	Yes	T1,T2,T19	INPUT
edn_i[1].edn_req	Yes	Yes	T115,T5,T116	Yes	T115,T5,T116	INPUT
edn_i[2].edn_req	Yes	Yes	T20,T115,T6	Yes	T20,T115,T6	INPUT
edn_i[3].edn_req	Yes	Yes	T22,T115,T117	Yes	T22,T115,T117	INPUT
edn_i[4].edn_req	Yes	Yes	T8,T11,T115	Yes	T8,T11,T115	INPUT
edn_i[5].edn_req	Yes	Yes	T3,T4,T9	Yes	T3,T4,T9	INPUT
edn_i[6].edn_req	Yes	Yes	T10,T118,T119	Yes	T10,T118,T119	INPUT
edn_o[0].edn_bus[31:0]	Yes	Yes	T1,T21,T11	Yes	T1,T2,T21	OUTPUT
edn_o[0].edn_fips	Yes	Yes	T1,T21,T11	Yes	T1,T21,T11	OUTPUT
edn_o[0].edn_ack	Yes	Yes	T1,T2,T19	Yes	T1,T2,T19	OUTPUT
edn_o[1].edn_bus[31:0]	Yes	Yes	T118,T120,T119	Yes	T115,T116,T118	OUTPUT
edn_o[1].edn_fips	Yes	Yes	T119,T121,T122	Yes	T123,T120,T119	OUTPUT
edn_o[1].edn_ack	Yes	Yes	T115,T116,T118	Yes	T115,T116,T118	OUTPUT
edn_o[2].edn_bus[31:0]	Yes	Yes	T20,T118,T123	Yes	T20,T115,T116	OUTPUT
edn_o[2].edn_fips	Yes	Yes	T118,T123,T124	Yes	T115,T118,T123	OUTPUT
edn_o[2].edn_ack	Yes	Yes	T20,T115,T116	Yes	T20,T115,T116	OUTPUT
edn_o[3].edn_bus[31:0]	Yes	Yes	T22,T115,T117	Yes	T22,T115,T117	OUTPUT
edn_o[3].edn_fips	Yes	Yes	T117,T118,T119	Yes	T117,T118,T123	OUTPUT
edn_o[3].edn_ack	Yes	Yes	T22,T115,T117	Yes	T22,T115,T117	OUTPUT
edn_o[4].edn_bus[31:0]	Yes	Yes	T8,T11,T115	Yes	T8,T11,T115	OUTPUT
edn_o[4].edn_fips	Yes	Yes	T8,T11,T117	Yes	T8,T11,T117	OUTPUT
edn_o[4].edn_ack	Yes	Yes	T8,T11,T115	Yes	T8,T11,T115	OUTPUT
edn_o[5].edn_bus[31:0]	Yes	Yes	T4,T9,T118	Yes	T4,T9,T118	OUTPUT
edn_o[5].edn_fips	Yes	Yes	T9,T123,T121	Yes	T9,T118,T123	OUTPUT
edn_o[5].edn_ack	Yes	Yes	T4,T9,T118	Yes	T4,T9,T118	OUTPUT
edn_o[6].edn_bus[31:0]	Yes	Yes	T118,T119,T124	Yes	T10,T118,T119	OUTPUT
edn_o[6].edn_fips	Yes	Yes	T119,T125,T126	Yes	T119,T28,T121	OUTPUT
edn_o[6].edn_ack	Yes	Yes	T10,T118,T119	Yes	T10,T118,T119	OUTPUT
csrng_cmd_o.genbits_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_bus[31:0]	Yes	Yes	T1,T2,T19	Yes	T1,T2,T19	OUTPUT
csrng_cmd_o.csrng_req_valid	Yes	Yes	T1,T2,T19	Yes	T1,T2,T19	OUTPUT
csrng_cmd_i.genbits_bus[127:0]	Yes	Yes	T1,T8,T21	Yes	T1,T8,T20	INPUT
csrng_cmd_i.genbits_fips	Yes	Yes	T1,T8,T21	Yes	T1,T8,T21	INPUT
csrng_cmd_i.genbits_valid	Yes	Yes	T1,T2,T19	Yes	T1,T2,T19	INPUT
csrng_cmd_i.csrng_rsp_sts[2:0]	Yes	Yes	T14,T25,T127	Yes	T14,T25,T127	INPUT
csrng_cmd_i.csrng_rsp_ack	Yes	Yes	T1,T2,T19	Yes	T1,T2,T19	INPUT
csrng_cmd_i.csrng_req_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T128,T129,T130	Yes	T128,T129,T130	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T3,T4,T128	Yes	T3,T4,T128	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T128,T129,T130	Yes	T128,T129,T130	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T3,T4,T128	Yes	T3,T4,T128	OUTPUT
intr_edn_cmd_req_done_o	Yes	Yes	T99,T100,T113	Yes	T99,T100,T113	OUTPUT
intr_edn_fatal_err_o	Yes	Yes	T4,T98,T99	Yes	T4,T98,T99	OUTPUT

*Tests covering at least one bit in the range

---

Assert Coverage for Module : edn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	47	47	100.00	47	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	47	47	100.00	47	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxKnownO_A	217121993	216942292	0	0
CsrngAppIfOut_A	217121993	216942292	0	0
FpvSecCmCntAlertCheck_A	217121993	124	0	0
FpvSecCmGenCmdFifoRptrCheck_A	217121993	80	0	0
FpvSecCmGenCmdFifoWptrCheck_A	217121993	80	0	0
FpvSecCmMainFsmCheck_A	217121993	80	0	0
FpvSecCmRegWeOnehotCheck_A	217121993	80	0	0
FpvSecCmResCmdFifoRptrCheck_A	217121993	80	0	0
FpvSecCmResCmdFifoWptrCheck_A	217121993	80	0	0
IntrEdnCmdReqDoneKnownO_A	217121993	216942292	0	0
TlAReadyKnownO_A	217121993	216942292	0	0
TlDValidKnownO_A	217121993	216942292	0	0
gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A	217121993	80	0	0
gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A	217121993	80	0	0
gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A	217121993	80	0	0
gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A	217121993	80	0	0
gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A	217121993	80	0	0
gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A	217121993	80	0	0
gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A	217121993	80	0	0
gen_edn_if_asserts[0].EdnDataStableDisable_A	217121993	543620	0	316
gen_edn_if_asserts[0].EdnDataStable_A	217121993	23622	0	342
gen_edn_if_asserts[0].EdnEndPointOut_A	217121993	216942292	0	0
gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A	217121993	149817	0	0
gen_edn_if_asserts[1].EdnDataStableDisable_A	217121993	543620	0	316
gen_edn_if_asserts[1].EdnDataStable_A	217121993	2836	0	117
gen_edn_if_asserts[1].EdnEndPointOut_A	217121993	216942292	0	0
gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A	217121993	149817	0	0
gen_edn_if_asserts[2].EdnDataStableDisable_A	217121993	543620	0	316
gen_edn_if_asserts[2].EdnDataStable_A	217121993	4132	0	102
gen_edn_if_asserts[2].EdnEndPointOut_A	217121993	216942292	0	0
gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A	217121993	149817	0	0
gen_edn_if_asserts[3].EdnDataStableDisable_A	217121993	543620	0	316
gen_edn_if_asserts[3].EdnDataStable_A	217121993	6279	0	112
gen_edn_if_asserts[3].EdnEndPointOut_A	217121993	216942292	0	0
gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A	217121993	149817	0	0
gen_edn_if_asserts[4].EdnDataStableDisable_A	217121993	543620	0	316
gen_edn_if_asserts[4].EdnDataStable_A	217121993	5309	0	101
gen_edn_if_asserts[4].EdnEndPointOut_A	217121993	216942292	0	0
gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A	217121993	149817	0	0
gen_edn_if_asserts[5].EdnDataStableDisable_A	217121993	543620	0	316
gen_edn_if_asserts[5].EdnDataStable_A	217121993	2245	0	82
gen_edn_if_asserts[5].EdnEndPointOut_A	217121993	216942292	0	0
gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A	217121993	149817	0	0
gen_edn_if_asserts[6].EdnDataStableDisable_A	217121993	543620	0	316
gen_edn_if_asserts[6].EdnDataStable_A	217121993	3528	0	75
gen_edn_if_asserts[6].EdnEndPointOut_A	217121993	216942292	0	0
gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A	217121993	149817	0	0

AlertTxKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217121993	216942292	0	0
T1	2340	2263	0	0
T2	1278	1183	0	0
T3	1181	1017	0	0
T8	5491	5418	0	0
T11	2254	2157	0	0
T19	2149	2095	0	0
T20	1401	1312	0	0
T21	2236	2171	0	0
T22	1087	1034	0	0
T23	2736	2637	0	0

CsrngAppIfOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217121993	216942292	0	0
T1	2340	2263	0	0
T2	1278	1183	0	0
T3	1181	1017	0	0
T8	5491	5418	0	0
T11	2254	2157	0	0
T19	2149	2095	0	0
T20	1401	1312	0	0
T21	2236	2171	0	0
T22	1087	1034	0	0
T23	2736	2637	0	0

FpvSecCmCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217121993	124	0	0
T6	860	1	0	0
T7	1992	0	0	0
T14	0	1	0	0
T15	0	1	0	0
T24	1951	0	0	0
T35	0	1	0	0
T36	0	1	0	0
T62	0	1	0	0
T63	0	1	0	0
T68	0	1	0	0
T78	721	0	0	0
T98	1953	0	0	0
T99	549293	0	0	0
T116	3296	0	0	0
T118	3289	0	0	0
T129	1568	0	0	0
T131	0	1	0	0
T132	0	1	0	0
T133	1902	0	0	0

FpvSecCmGenCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217121993	80	0	0
T16	22162	10	0	0
T17	0	20	0	0
T18	0	20	0	0
T47	1485	0	0	0
T57	3381	0	0	0
T73	2316	0	0	0
T134	0	10	0	0
T135	0	20	0	0
T136	3672	0	0	0
T137	1149	0	0	0
T138	1745	0	0	0
T139	1280	0	0	0
T140	702	0	0	0
T141	1823	0	0	0

FpvSecCmGenCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217121993	80	0	0
T16	22162	10	0	0
T17	0	20	0	0
T18	0	20	0	0
T47	1485	0	0	0
T57	3381	0	0	0
T73	2316	0	0	0
T134	0	10	0	0
T135	0	20	0	0
T136	3672	0	0	0
T137	1149	0	0	0
T138	1745	0	0	0
T139	1280	0	0	0
T140	702	0	0	0
T141	1823	0	0	0

FpvSecCmMainFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217121993	80	0	0
T16	22162	10	0	0
T17	0	20	0	0
T18	0	20	0	0
T47	1485	0	0	0
T57	3381	0	0	0
T73	2316	0	0	0
T134	0	10	0	0
T135	0	20	0	0
T136	3672	0	0	0
T137	1149	0	0	0
T138	1745	0	0	0
T139	1280	0	0	0
T140	702	0	0	0
T141	1823	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217121993	80	0	0
T16	22162	10	0	0
T17	0	20	0	0
T18	0	20	0	0
T47	1485	0	0	0
T57	3381	0	0	0
T73	2316	0	0	0
T134	0	10	0	0
T135	0	20	0	0
T136	3672	0	0	0
T137	1149	0	0	0
T138	1745	0	0	0
T139	1280	0	0	0
T140	702	0	0	0
T141	1823	0	0	0

FpvSecCmResCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217121993	80	0	0
T16	22162	10	0	0
T17	0	20	0	0
T18	0	20	0	0
T47	1485	0	0	0
T57	3381	0	0	0
T73	2316	0	0	0
T134	0	10	0	0
T135	0	20	0	0
T136	3672	0	0	0
T137	1149	0	0	0
T138	1745	0	0	0
T139	1280	0	0	0
T140	702	0	0	0
T141	1823	0	0	0

FpvSecCmResCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217121993	80	0	0
T16	22162	10	0	0
T17	0	20	0	0
T18	0	20	0	0
T47	1485	0	0	0
T57	3381	0	0	0
T73	2316	0	0	0
T134	0	10	0	0
T135	0	20	0	0
T136	3672	0	0	0
T137	1149	0	0	0
T138	1745	0	0	0
T139	1280	0	0	0
T140	702	0	0	0
T141	1823	0	0	0

IntrEdnCmdReqDoneKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217121993	216942292	0	0
T1	2340	2263	0	0
T2	1278	1183	0	0
T3	1181	1017	0	0
T8	5491	5418	0	0
T11	2254	2157	0	0
T19	2149	2095	0	0
T20	1401	1312	0	0
T21	2236	2171	0	0
T22	1087	1034	0	0
T23	2736	2637	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217121993	216942292	0	0
T1	2340	2263	0	0
T2	1278	1183	0	0
T3	1181	1017	0	0
T8	5491	5418	0	0
T11	2254	2157	0	0
T19	2149	2095	0	0
T20	1401	1312	0	0
T21	2236	2171	0	0
T22	1087	1034	0	0
T23	2736	2637	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217121993	216942292	0	0
T1	2340	2263	0	0
T2	1278	1183	0	0
T3	1181	1017	0	0
T8	5491	5418	0	0
T11	2254	2157	0	0
T19	2149	2095	0	0
T20	1401	1312	0	0
T21	2236	2171	0	0
T22	1087	1034	0	0
T23	2736	2637	0	0

gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217121993	80	0	0
T16	22162	10	0	0
T17	0	20	0	0
T18	0	20	0	0
T47	1485	0	0	0
T57	3381	0	0	0
T73	2316	0	0	0
T134	0	10	0	0
T135	0	20	0	0
T136	3672	0	0	0
T137	1149	0	0	0
T138	1745	0	0	0
T139	1280	0	0	0
T140	702	0	0	0
T141	1823	0	0	0

gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217121993	80	0	0
T16	22162	10	0	0
T17	0	20	0	0
T18	0	20	0	0
T47	1485	0	0	0
T57	3381	0	0	0
T73	2316	0	0	0
T134	0	10	0	0
T135	0	20	0	0
T136	3672	0	0	0
T137	1149	0	0	0
T138	1745	0	0	0
T139	1280	0	0	0
T140	702	0	0	0
T141	1823	0	0	0

gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217121993	80	0	0
T16	22162	10	0	0
T17	0	20	0	0
T18	0	20	0	0
T47	1485	0	0	0
T57	3381	0	0	0
T73	2316	0	0	0
T134	0	10	0	0
T135	0	20	0	0
T136	3672	0	0	0
T137	1149	0	0	0
T138	1745	0	0	0
T139	1280	0	0	0
T140	702	0	0	0
T141	1823	0	0	0

gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217121993	80	0	0
T16	22162	10	0	0
T17	0	20	0	0
T18	0	20	0	0
T47	1485	0	0	0
T57	3381	0	0	0
T73	2316	0	0	0
T134	0	10	0	0
T135	0	20	0	0
T136	3672	0	0	0
T137	1149	0	0	0
T138	1745	0	0	0
T139	1280	0	0	0
T140	702	0	0	0
T141	1823	0	0	0

gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217121993	80	0	0
T16	22162	10	0	0
T17	0	20	0	0
T18	0	20	0	0
T47	1485	0	0	0
T57	3381	0	0	0
T73	2316	0	0	0
T134	0	10	0	0
T135	0	20	0	0
T136	3672	0	0	0
T137	1149	0	0	0
T138	1745	0	0	0
T139	1280	0	0	0
T140	702	0	0	0
T141	1823	0	0	0

gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217121993	80	0	0
T16	22162	10	0	0
T17	0	20	0	0
T18	0	20	0	0
T47	1485	0	0	0
T57	3381	0	0	0
T73	2316	0	0	0
T134	0	10	0	0
T135	0	20	0	0
T136	3672	0	0	0
T137	1149	0	0	0
T138	1745	0	0	0
T139	1280	0	0	0
T140	702	0	0	0
T141	1823	0	0	0

gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217121993	80	0	0
T16	22162	10	0	0
T17	0	20	0	0
T18	0	20	0	0
T47	1485	0	0	0
T57	3381	0	0	0
T73	2316	0	0	0
T134	0	10	0	0
T135	0	20	0	0
T136	3672	0	0	0
T137	1149	0	0	0
T138	1745	0	0	0
T139	1280	0	0	0
T140	702	0	0	0
T141	1823	0	0	0

gen_edn_if_asserts[0].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217121993	543620	0	316
T1	2340	42	0	0
T2	1278	12	0	0
T3	1181	595	0	0
T8	5491	245	0	0
T10	0	0	0	2
T11	2254	200	0	0
T19	2149	34	0	0
T20	1401	44	0	0
T21	2236	24	0	0
T22	1087	100	0	0
T23	2736	22	0	0
T28	0	0	0	2
T29	0	0	0	2
T99	0	0	0	2
T113	0	0	0	2
T114	0	0	0	2
T128	0	0	0	2
T129	0	0	0	2
T130	0	0	0	2
T142	0	0	0	2

gen_edn_if_asserts[0].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217121993	23622	0	342
T1	2340	19	0	1
T2	1278	3	0	1
T3	1181	0	0	0
T8	5491	0	0	0
T10	0	4	0	0
T11	2254	55	0	1
T19	2149	3	0	1
T20	1401	0	0	0
T21	2236	19	0	1
T22	1087	0	0	0
T23	2736	14	0	1
T27	0	18	0	1
T143	0	3	0	1
T144	0	15	0	1
T145	0	0	0	1

gen_edn_if_asserts[0].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217121993	216942292	0	0
T1	2340	2263	0	0
T2	1278	1183	0	0
T3	1181	1017	0	0
T8	5491	5418	0	0
T11	2254	2157	0	0
T19	2149	2095	0	0
T20	1401	1312	0	0
T21	2236	2171	0	0
T22	1087	1034	0	0
T23	2736	2637	0	0

gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217121993	149817	0	0
T3	1181	636	0	0
T4	1243	560	0	0
T5	0	394	0	0
T6	0	364	0	0
T7	0	1072	0	0
T8	5491	0	0	0
T9	2117	0	0	0
T11	2254	0	0	0
T14	0	364	0	0
T19	2149	0	0	0
T20	1401	0	0	0
T21	2236	0	0	0
T22	1087	0	0	0
T23	2736	0	0	0
T24	0	1113	0	0
T70	0	332	0	0
T78	0	373	0	0
T98	0	7	0	0

gen_edn_if_asserts[1].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217121993	543620	0	316
T1	2340	42	0	0
T2	1278	12	0	0
T3	1181	595	0	0
T8	5491	245	0	0
T10	0	0	0	2
T11	2254	200	0	0
T19	2149	34	0	0
T20	1401	44	0	0
T21	2236	24	0	0
T22	1087	100	0	0
T23	2736	22	0	0
T28	0	0	0	2
T29	0	0	0	2
T99	0	0	0	2
T113	0	0	0	2
T114	0	0	0	2
T128	0	0	0	2
T129	0	0	0	2
T130	0	0	0	2
T142	0	0	0	2

gen_edn_if_asserts[1].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217121993	2836	0	117
T5	1363	0	0	0
T6	860	0	0	0
T10	3586	0	0	0
T27	1838	0	0	0
T28	0	1	0	0
T115	2863	3	0	1
T116	0	3	0	1
T117	2744	0	0	0
T118	0	3	0	1
T119	0	32	0	1
T120	0	3	0	1
T121	0	25	0	1
T122	0	0	0	1
T123	0	3	0	1
T124	0	3	0	1
T128	1187	0	0	0
T143	1467	0	0	0
T144	3683	0	0	0
T145	2688	0	0	0
T146	0	3	0	1

gen_edn_if_asserts[1].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217121993	216942292	0	0
T1	2340	2263	0	0
T2	1278	1183	0	0
T3	1181	1017	0	0
T8	5491	5418	0	0
T11	2254	2157	0	0
T19	2149	2095	0	0
T20	1401	1312	0	0
T21	2236	2171	0	0
T22	1087	1034	0	0
T23	2736	2637	0	0

gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217121993	149817	0	0
T3	1181	636	0	0
T4	1243	560	0	0
T5	0	394	0	0
T6	0	364	0	0
T7	0	1072	0	0
T8	5491	0	0	0
T9	2117	0	0	0
T11	2254	0	0	0
T14	0	364	0	0
T19	2149	0	0	0
T20	1401	0	0	0
T21	2236	0	0	0
T22	1087	0	0	0
T23	2736	0	0	0
T24	0	1113	0	0
T70	0	332	0	0
T78	0	373	0	0
T98	0	7	0	0

gen_edn_if_asserts[2].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217121993	543620	0	316
T1	2340	42	0	0
T2	1278	12	0	0
T3	1181	595	0	0
T8	5491	245	0	0
T10	0	0	0	2
T11	2254	200	0	0
T19	2149	34	0	0
T20	1401	44	0	0
T21	2236	24	0	0
T22	1087	100	0	0
T23	2736	22	0	0
T28	0	0	0	2
T29	0	0	0	2
T99	0	0	0	2
T113	0	0	0	2
T114	0	0	0	2
T128	0	0	0	2
T129	0	0	0	2
T130	0	0	0	2
T142	0	0	0	2

gen_edn_if_asserts[2].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217121993	4132	0	102
T4	1243	0	0	0
T9	2117	0	0	0
T11	2254	0	0	0
T20	1401	4	0	0
T21	2236	0	0	0
T22	1087	0	0	0
T23	2736	0	0	0
T29	0	4	0	0
T115	2863	3	0	1
T116	0	3	0	1
T118	0	40	0	1
T120	0	3	0	1
T121	0	3	0	1
T123	0	11	0	1
T124	0	21	0	1
T128	1187	0	0	0
T143	1467	0	0	0
T146	0	3	0	1
T147	0	0	0	1
T148	0	0	0	1

gen_edn_if_asserts[2].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217121993	216942292	0	0
T1	2340	2263	0	0
T2	1278	1183	0	0
T3	1181	1017	0	0
T8	5491	5418	0	0
T11	2254	2157	0	0
T19	2149	2095	0	0
T20	1401	1312	0	0
T21	2236	2171	0	0
T22	1087	1034	0	0
T23	2736	2637	0	0

gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217121993	149817	0	0
T3	1181	636	0	0
T4	1243	560	0	0
T5	0	394	0	0
T6	0	364	0	0
T7	0	1072	0	0
T8	5491	0	0	0
T9	2117	0	0	0
T11	2254	0	0	0
T14	0	364	0	0
T19	2149	0	0	0
T20	1401	0	0	0
T21	2236	0	0	0
T22	1087	0	0	0
T23	2736	0	0	0
T24	0	1113	0	0
T70	0	332	0	0
T78	0	373	0	0
T98	0	7	0	0

gen_edn_if_asserts[3].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217121993	543620	0	316
T1	2340	42	0	0
T2	1278	12	0	0
T3	1181	595	0	0
T8	5491	245	0	0
T10	0	0	0	2
T11	2254	200	0	0
T19	2149	34	0	0
T20	1401	44	0	0
T21	2236	24	0	0
T22	1087	100	0	0
T23	2736	22	0	0
T28	0	0	0	2
T29	0	0	0	2
T99	0	0	0	2
T113	0	0	0	2
T114	0	0	0	2
T128	0	0	0	2
T129	0	0	0	2
T130	0	0	0	2
T142	0	0	0	2

gen_edn_if_asserts[3].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217121993	6279	0	112
T4	1243	0	0	0
T9	2117	0	0	0
T10	3586	0	0	0
T11	2254	0	0	0
T22	1087	3	0	1
T23	2736	0	0	0
T27	1838	0	0	0
T115	2863	3	0	1
T117	0	25	0	1
T118	0	26	0	1
T119	0	54	0	1
T121	0	41	0	1
T122	0	39	0	1
T123	0	3	0	1
T124	0	3	0	1
T128	1187	0	0	0
T143	1467	0	0	0
T149	0	14	0	1

gen_edn_if_asserts[3].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217121993	216942292	0	0
T1	2340	2263	0	0
T2	1278	1183	0	0
T3	1181	1017	0	0
T8	5491	5418	0	0
T11	2254	2157	0	0
T19	2149	2095	0	0
T20	1401	1312	0	0
T21	2236	2171	0	0
T22	1087	1034	0	0
T23	2736	2637	0	0

gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217121993	149817	0	0
T3	1181	636	0	0
T4	1243	560	0	0
T5	0	394	0	0
T6	0	364	0	0
T7	0	1072	0	0
T8	5491	0	0	0
T9	2117	0	0	0
T11	2254	0	0	0
T14	0	364	0	0
T19	2149	0	0	0
T20	1401	0	0	0
T21	2236	0	0	0
T22	1087	0	0	0
T23	2736	0	0	0
T24	0	1113	0	0
T70	0	332	0	0
T78	0	373	0	0
T98	0	7	0	0

gen_edn_if_asserts[4].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217121993	543620	0	316
T1	2340	42	0	0
T2	1278	12	0	0
T3	1181	595	0	0
T8	5491	245	0	0
T10	0	0	0	2
T11	2254	200	0	0
T19	2149	34	0	0
T20	1401	44	0	0
T21	2236	24	0	0
T22	1087	100	0	0
T23	2736	22	0	0
T28	0	0	0	2
T29	0	0	0	2
T99	0	0	0	2
T113	0	0	0	2
T114	0	0	0	2
T128	0	0	0	2
T129	0	0	0	2
T130	0	0	0	2
T142	0	0	0	2

gen_edn_if_asserts[4].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217121993	5309	0	101
T4	1243	0	0	0
T8	5491	845	0	1
T9	2117	0	0	0
T11	2254	15	0	1
T20	1401	0	0	0
T21	2236	0	0	0
T22	1087	0	0	0
T23	2736	0	0	0
T115	2863	3	0	1
T117	0	24	0	1
T121	0	3	0	1
T123	0	52	0	1
T124	0	49	0	1
T128	1187	0	0	0
T146	0	3	0	1
T148	0	3	0	1
T149	0	73	0	1

gen_edn_if_asserts[4].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217121993	216942292	0	0
T1	2340	2263	0	0
T2	1278	1183	0	0
T3	1181	1017	0	0
T8	5491	5418	0	0
T11	2254	2157	0	0
T19	2149	2095	0	0
T20	1401	1312	0	0
T21	2236	2171	0	0
T22	1087	1034	0	0
T23	2736	2637	0	0

gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217121993	149817	0	0
T3	1181	636	0	0
T4	1243	560	0	0
T5	0	394	0	0
T6	0	364	0	0
T7	0	1072	0	0
T8	5491	0	0	0
T9	2117	0	0	0
T11	2254	0	0	0
T14	0	364	0	0
T19	2149	0	0	0
T20	1401	0	0	0
T21	2236	0	0	0
T22	1087	0	0	0
T23	2736	0	0	0
T24	0	1113	0	0
T70	0	332	0	0
T78	0	373	0	0
T98	0	7	0	0

gen_edn_if_asserts[5].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217121993	543620	0	316
T1	2340	42	0	0
T2	1278	12	0	0
T3	1181	595	0	0
T8	5491	245	0	0
T10	0	0	0	2
T11	2254	200	0	0
T19	2149	34	0	0
T20	1401	44	0	0
T21	2236	24	0	0
T22	1087	100	0	0
T23	2736	22	0	0
T28	0	0	0	2
T29	0	0	0	2
T99	0	0	0	2
T113	0	0	0	2
T114	0	0	0	2
T128	0	0	0	2
T129	0	0	0	2
T130	0	0	0	2
T142	0	0	0	2

gen_edn_if_asserts[5].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217121993	2245	0	82
T4	1243	1	0	0
T9	2117	87	0	1
T10	3586	0	0	0
T12	0	47	0	1
T27	1838	0	0	0
T115	2863	0	0	0
T117	2744	0	0	0
T118	0	3	0	1
T119	0	3	0	1
T121	0	19	0	1
T123	0	25	0	1
T124	0	3	0	1
T128	1187	0	0	0
T143	1467	0	0	0
T144	3683	0	0	0
T145	2688	0	0	0
T146	0	3	0	1
T149	0	3	0	1
T150	0	0	0	1

gen_edn_if_asserts[5].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217121993	216942292	0	0
T1	2340	2263	0	0
T2	1278	1183	0	0
T3	1181	1017	0	0
T8	5491	5418	0	0
T11	2254	2157	0	0
T19	2149	2095	0	0
T20	1401	1312	0	0
T21	2236	2171	0	0
T22	1087	1034	0	0
T23	2736	2637	0	0

gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217121993	149817	0	0
T3	1181	636	0	0
T4	1243	560	0	0
T5	0	394	0	0
T6	0	364	0	0
T7	0	1072	0	0
T8	5491	0	0	0
T9	2117	0	0	0
T11	2254	0	0	0
T14	0	364	0	0
T19	2149	0	0	0
T20	1401	0	0	0
T21	2236	0	0	0
T22	1087	0	0	0
T23	2736	0	0	0
T24	0	1113	0	0
T70	0	332	0	0
T78	0	373	0	0
T98	0	7	0	0

gen_edn_if_asserts[6].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217121993	543620	0	316
T1	2340	42	0	0
T2	1278	12	0	0
T3	1181	595	0	0
T8	5491	245	0	0
T10	0	0	0	2
T11	2254	200	0	0
T19	2149	34	0	0
T20	1401	44	0	0
T21	2236	24	0	0
T22	1087	100	0	0
T23	2736	22	0	0
T28	0	0	0	2
T29	0	0	0	2
T99	0	0	0	2
T113	0	0	0	2
T114	0	0	0	2
T128	0	0	0	2
T129	0	0	0	2
T130	0	0	0	2
T142	0	0	0	2

gen_edn_if_asserts[6].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217121993	3528	0	75
T5	1363	0	0	0
T6	860	0	0	0
T10	3586	1	0	0
T28	0	4	0	0
T38	0	4	0	0
T98	1953	0	0	0
T116	3296	0	0	0
T117	2744	0	0	0
T118	0	3	0	1
T119	0	72	0	1
T121	0	3	0	1
T124	0	3	0	1
T125	0	0	0	1
T126	0	0	0	1
T129	1568	0	0	0
T133	1902	0	0	0
T144	3683	0	0	0
T145	2688	0	0	0
T146	0	3	0	1
T151	0	7	0	1
T152	0	3	0	1
T153	0	0	0	1

gen_edn_if_asserts[6].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217121993	216942292	0	0
T1	2340	2263	0	0
T2	1278	1183	0	0
T3	1181	1017	0	0
T8	5491	5418	0	0
T11	2254	2157	0	0
T19	2149	2095	0	0
T20	1401	1312	0	0
T21	2236	2171	0	0
T22	1087	1034	0	0
T23	2736	2637	0	0

gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217121993	149817	0	0
T3	1181	636	0	0
T4	1243	560	0	0
T5	0	394	0	0
T6	0	364	0	0
T7	0	1072	0	0
T8	5491	0	0	0
T9	2117	0	0	0
T11	2254	0	0	0
T14	0	364	0	0
T19	2149	0	0	0
T20	1401	0	0	0
T21	2236	0	0	0
T22	1087	0	0	0
T23	2736	0	0	0
T24	0	1113	0	0
T70	0	332	0	0
T78	0	373	0	0
T98	0	7	0	0