Module Definition
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Module : edn_csr_assert_fpv
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.edn_csr_assert 100.00 100.00



Module Instance : tb.dut.edn_csr_assert

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.44 83.33 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Assert Coverage for Module : edn_csr_assert_fpv
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 8 8 100.00 8 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 8 8 100.00 8 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
TlulOOBAddrErr_A 217646588 10022568 0 0
boot_gen_cmd_rd_A 217646588 63852 0 0
boot_ins_cmd_rd_A 217646588 74866 0 0
ctrl_rd_A 217646588 64749 0 0
err_code_test_rd_A 217646588 73938 0 0
intr_enable_rd_A 217646588 73157 0 0
max_num_reqs_between_reseeds_rd_A 217646588 66099 0 0
regwen_rd_A 217646588 76522 0 0


TlulOOBAddrErr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 217646588 10022568 0 0
T24 1951 0 0 0
T70 1744 0 0 0
T78 721 0 0 0
T99 549293 20161 0 0
T113 0 237179 0 0
T114 0 91348 0 0
T118 3289 0 0 0
T119 4377 0 0 0
T120 2493 0 0 0
T123 4570 0 0 0
T124 2240 0 0 0
T162 0 130742 0 0
T165 0 55274 0 0
T201 0 61072 0 0
T202 0 291211 0 0
T203 0 111940 0 0
T204 0 375668 0 0
T205 0 62870 0 0
T206 1909 0 0 0

boot_gen_cmd_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 217646588 63852 0 0
T24 1951 0 0 0
T70 1744 0 0 0
T78 721 0 0 0
T99 549293 660 0 0
T118 3289 0 0 0
T119 4377 0 0 0
T120 2493 0 0 0
T123 4570 0 0 0
T124 2240 0 0 0
T204 0 6059 0 0
T205 0 1738 0 0
T206 1909 0 0 0
T207 0 5102 0 0
T208 0 1364 0 0
T209 0 5667 0 0
T210 0 2809 0 0
T211 0 8616 0 0
T212 0 5161 0 0
T213 0 2495 0 0

boot_ins_cmd_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 217646588 74866 0 0
T24 1951 0 0 0
T70 1744 0 0 0
T78 721 0 0 0
T99 549293 748 0 0
T118 3289 0 0 0
T119 4377 0 0 0
T120 2493 0 0 0
T123 4570 0 0 0
T124 2240 0 0 0
T204 0 6603 0 0
T205 0 1939 0 0
T206 1909 0 0 0
T207 0 6177 0 0
T208 0 1354 0 0
T209 0 6994 0 0
T210 0 3570 0 0
T211 0 10226 0 0
T212 0 6450 0 0
T213 0 3105 0 0

ctrl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 217646588 64749 0 0
T3 1181 2 0 0
T4 1243 0 0 0
T8 5491 0 0 0
T9 2117 0 0 0
T11 2254 0 0 0
T19 2149 0 0 0
T20 1401 0 0 0
T21 2236 0 0 0
T22 1087 0 0 0
T23 2736 0 0 0
T99 0 671 0 0
T104 0 2 0 0
T204 0 5751 0 0
T205 0 1671 0 0
T207 0 5322 0 0
T208 0 1316 0 0
T209 0 6551 0 0
T214 0 4 0 0
T215 0 3 0 0

err_code_test_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 217646588 73938 0 0
T24 1951 0 0 0
T70 1744 0 0 0
T78 721 0 0 0
T99 549293 630 0 0
T118 3289 0 0 0
T119 4377 0 0 0
T120 2493 0 0 0
T123 4570 0 0 0
T124 2240 0 0 0
T204 0 6919 0 0
T205 0 1976 0 0
T206 1909 0 0 0
T207 0 5771 0 0
T208 0 1480 0 0
T209 0 6464 0 0
T210 0 3522 0 0
T211 0 9671 0 0
T212 0 6291 0 0
T213 0 3274 0 0

intr_enable_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 217646588 73157 0 0
T24 1951 0 0 0
T70 1744 0 0 0
T78 721 0 0 0
T99 549293 861 0 0
T118 3289 0 0 0
T119 4377 0 0 0
T120 2493 0 0 0
T123 4570 0 0 0
T124 2240 0 0 0
T204 0 6196 0 0
T205 0 1931 0 0
T206 1909 0 0 0
T207 0 5451 0 0
T208 0 1833 0 0
T214 0 100 0 0
T215 0 13 0 0
T216 0 72 0 0
T217 0 156 0 0
T218 0 49 0 0

max_num_reqs_between_reseeds_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 217646588 66099 0 0
T24 1951 0 0 0
T70 1744 0 0 0
T78 721 0 0 0
T99 549293 497 0 0
T118 3289 0 0 0
T119 4377 0 0 0
T120 2493 0 0 0
T123 4570 0 0 0
T124 2240 0 0 0
T204 0 6139 0 0
T205 0 1815 0 0
T206 1909 0 0 0
T207 0 4806 0 0
T208 0 1417 0 0
T209 0 5952 0 0
T210 0 3067 0 0
T211 0 8543 0 0
T212 0 5532 0 0
T213 0 2841 0 0

regwen_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 217646588 76522 0 0
T24 1951 0 0 0
T70 1744 0 0 0
T78 721 0 0 0
T99 549293 807 0 0
T118 3289 0 0 0
T119 4377 0 0 0
T120 2493 0 0 0
T123 4570 0 0 0
T124 2240 0 0 0
T204 0 6691 0 0
T205 0 1924 0 0
T206 1909 0 0 0
T207 0 6053 0 0
T208 0 1585 0 0
T209 0 6889 0 0
T210 0 3236 0 0
T211 0 10478 0 0
T212 0 6445 0 0
T213 0 2948 0 0

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