Unified Coverage Report :: Module :: edn

Module : edn

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	94.44		83.33	100.00			100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.25	98.24	93.80	97.02	86.05	96.62	99.77

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
edn_csr_assert	100.00						100.00
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_edn_core	93.19	99.92	92.46	82.54	86.05	99.28	98.88
u_edn_cov_if	25.00	50.00	0.00
u_reg	96.95	95.02	97.57	100.00		92.16	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Cond Coverage for Module : edn

	Total	Covered	Percent
Conditions	6	5	83.33
Logical	6	5	83.33
Non-Logical	0	0
Event	0	0

 LINE       98
 EXPRESSION (alert[0] || intg_err_alert[0])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T15,T27,T29

 LINE       98
 EXPRESSION (alert[1] || intg_err_alert[1])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T16,T17,T18
1	0	Covered	T1,T2,T36

---

Toggle Coverage for Module : edn

	Total	Covered	Percent
Totals	69	69	100.00
Total Bits	1172	1172	100.00
Total Bits 0->1	586	586	100.00
Total Bits 1->0	586	586	100.00

Ports	69	69	100.00
Port Bits	1172	1172	100.00
Port Bits 0->1	586	586	100.00
Port Bits 1->0	586	586	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T2,T3,T19	Yes	T2,T3,T19	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T2,T3,T15	Yes	T2,T3,T15	INPUT
tl_i.a_source[7:0]	Yes	Yes	T2,T3,T15	Yes	T2,T3,T15	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T40,T41,T42	Yes	T40,T41,T42	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T2,T3,T15	Yes	T2,T3,T15	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i[0].edn_req	Yes	Yes	T3,T15,T19	Yes	T3,T15,T19	INPUT
edn_i[1].edn_req	Yes	Yes	T2,T3,T43	Yes	T2,T3,T43	INPUT
edn_i[2].edn_req	Yes	Yes	T3,T36,T44	Yes	T3,T36,T44	INPUT
edn_i[3].edn_req	Yes	Yes	T3,T10,T45	Yes	T3,T10,T45	INPUT
edn_i[4].edn_req	Yes	Yes	T3,T44,T10	Yes	T3,T44,T10	INPUT
edn_i[5].edn_req	Yes	Yes	T1,T23,T44	Yes	T1,T23,T44	INPUT
edn_i[6].edn_req	Yes	Yes	T44,T10,T11	Yes	T44,T10,T11	INPUT
edn_o[0].edn_bus[31:0]	Yes	Yes	T3,T15,T19	Yes	T3,T15,T19	OUTPUT
edn_o[0].edn_fips	Yes	Yes	T3,T8,T20	Yes	T3,T8,T20	OUTPUT
edn_o[0].edn_ack	Yes	Yes	T3,T15,T19	Yes	T3,T15,T19	OUTPUT
edn_o[1].edn_bus[31:0]	Yes	Yes	T3,T43,T46	Yes	T3,T43,T46	OUTPUT
edn_o[1].edn_fips	Yes	Yes	T3,T43,T47	Yes	T3,T43,T47	OUTPUT
edn_o[1].edn_ack	Yes	Yes	T3,T43,T46	Yes	T3,T43,T46	OUTPUT
edn_o[2].edn_bus[31:0]	Yes	Yes	T3,T44,T48	Yes	T3,T44,T48	OUTPUT
edn_o[2].edn_fips	Yes	Yes	T3,T48,T10	Yes	T3,T44,T48	OUTPUT
edn_o[2].edn_ack	Yes	Yes	T3,T44,T48	Yes	T3,T44,T48	OUTPUT
edn_o[3].edn_bus[31:0]	Yes	Yes	T3,T10,T45	Yes	T3,T10,T45	OUTPUT
edn_o[3].edn_fips	Yes	Yes	T45,T11,T49	Yes	T3,T10,T45	OUTPUT
edn_o[3].edn_ack	Yes	Yes	T3,T10,T45	Yes	T3,T10,T45	OUTPUT
edn_o[4].edn_bus[31:0]	Yes	Yes	T3,T44,T10	Yes	T3,T44,T10	OUTPUT
edn_o[4].edn_fips	Yes	Yes	T44,T10,T11	Yes	T3,T44,T10	OUTPUT
edn_o[4].edn_ack	Yes	Yes	T3,T44,T10	Yes	T3,T44,T10	OUTPUT
edn_o[5].edn_bus[31:0]	Yes	Yes	T23,T44,T9	Yes	T23,T44,T9	OUTPUT
edn_o[5].edn_fips	Yes	Yes	T44,T50,T11	Yes	T44,T10,T27	OUTPUT
edn_o[5].edn_ack	Yes	Yes	T23,T44,T9	Yes	T23,T44,T9	OUTPUT
edn_o[6].edn_bus[31:0]	Yes	Yes	T44,T10,T11	Yes	T44,T10,T11	OUTPUT
edn_o[6].edn_fips	Yes	Yes	T44,T10,T12	Yes	T44,T10,T51	OUTPUT
edn_o[6].edn_ack	Yes	Yes	T44,T10,T11	Yes	T44,T10,T11	OUTPUT
csrng_cmd_o.genbits_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_bus[31:0]	Yes	Yes	T1,T3,T15	Yes	T1,T3,T15	OUTPUT
csrng_cmd_o.csrng_req_valid	Yes	Yes	T1,T3,T15	Yes	T1,T3,T15	OUTPUT
csrng_cmd_i.genbits_bus[127:0]	Yes	Yes	T3,T8,T20	Yes	T3,T8,T52	INPUT
csrng_cmd_i.genbits_fips	Yes	Yes	T3,T8,T20	Yes	T3,T8,T52	INPUT
csrng_cmd_i.genbits_valid	Yes	Yes	T3,T15,T19	Yes	T3,T15,T19	INPUT
csrng_cmd_i.csrng_rsp_sts[2:0]	Yes	Yes	T15,T29,T53	Yes	T15,T29,T53	INPUT
csrng_cmd_i.csrng_rsp_ack	Yes	Yes	T1,T3,T15	Yes	T1,T3,T15	INPUT
csrng_cmd_i.csrng_req_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T15,T54,T27	Yes	T15,T54,T27	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T1,T2,T36	Yes	T1,T2,T36	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T15,T54,T27	Yes	T15,T54,T27	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T1,T2,T36	Yes	T1,T2,T36	OUTPUT
intr_edn_cmd_req_done_o	Yes	Yes	T4,T55,T40	Yes	T4,T55,T40	OUTPUT
intr_edn_fatal_err_o	Yes	Yes	T4,T55,T40	Yes	T4,T55,T40	OUTPUT

*Tests covering at least one bit in the range

---

Assert Coverage for Module : edn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	47	47	100.00	47	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	47	47	100.00	47	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxKnownO_A	213976727	213797976	0	0
CsrngAppIfOut_A	213976727	213797976	0	0
FpvSecCmCntAlertCheck_A	213976727	132	0	0
FpvSecCmGenCmdFifoRptrCheck_A	213976727	80	0	0
FpvSecCmGenCmdFifoWptrCheck_A	213976727	80	0	0
FpvSecCmMainFsmCheck_A	213976727	80	0	0
FpvSecCmRegWeOnehotCheck_A	213976727	80	0	0
FpvSecCmResCmdFifoRptrCheck_A	213976727	80	0	0
FpvSecCmResCmdFifoWptrCheck_A	213976727	80	0	0
IntrEdnCmdReqDoneKnownO_A	213976727	213797976	0	0
TlAReadyKnownO_A	213976727	213797976	0	0
TlDValidKnownO_A	213976727	213797976	0	0
gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A	213976727	80	0	0
gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A	213976727	80	0	0
gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A	213976727	80	0	0
gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A	213976727	80	0	0
gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A	213976727	80	0	0
gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A	213976727	80	0	0
gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A	213976727	80	0	0
gen_edn_if_asserts[0].EdnDataStableDisable_A	213976727	568657	0	326
gen_edn_if_asserts[0].EdnDataStable_A	213976727	24974	0	342
gen_edn_if_asserts[0].EdnEndPointOut_A	213976727	213797976	0	0
gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A	213976727	148885	0	0
gen_edn_if_asserts[1].EdnDataStableDisable_A	213976727	568657	0	326
gen_edn_if_asserts[1].EdnDataStable_A	213976727	4967	0	112
gen_edn_if_asserts[1].EdnEndPointOut_A	213976727	213797976	0	0
gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A	213976727	148885	0	0
gen_edn_if_asserts[2].EdnDataStableDisable_A	213976727	568657	0	326
gen_edn_if_asserts[2].EdnDataStable_A	213976727	4915	0	115
gen_edn_if_asserts[2].EdnEndPointOut_A	213976727	213797976	0	0
gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A	213976727	148885	0	0
gen_edn_if_asserts[3].EdnDataStableDisable_A	213976727	568657	0	326
gen_edn_if_asserts[3].EdnDataStable_A	213976727	4574	0	98
gen_edn_if_asserts[3].EdnEndPointOut_A	213976727	213797976	0	0
gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A	213976727	148885	0	0
gen_edn_if_asserts[4].EdnDataStableDisable_A	213976727	568657	0	326
gen_edn_if_asserts[4].EdnDataStable_A	213976727	3216	0	94
gen_edn_if_asserts[4].EdnEndPointOut_A	213976727	213797976	0	0
gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A	213976727	148885	0	0
gen_edn_if_asserts[5].EdnDataStableDisable_A	213976727	568657	0	326
gen_edn_if_asserts[5].EdnDataStable_A	213976727	4487	0	90
gen_edn_if_asserts[5].EdnEndPointOut_A	213976727	213797976	0	0
gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A	213976727	148885	0	0
gen_edn_if_asserts[6].EdnDataStableDisable_A	213976727	568657	0	326
gen_edn_if_asserts[6].EdnDataStable_A	213976727	3518	0	83
gen_edn_if_asserts[6].EdnEndPointOut_A	213976727	213797976	0	0
gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A	213976727	148885	0	0

AlertTxKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	213976727	213797976	0	0
T1	1228	1097	0	0
T2	1958	1774	0	0
T3	3569	3495	0	0
T8	4440	4343	0	0
T15	2485	2406	0	0
T19	2484	2430	0	0
T20	1872	1820	0	0
T21	2006	1931	0	0
T22	1333	1277	0	0
T23	1095	1041	0	0

CsrngAppIfOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	213976727	213797976	0	0
T1	1228	1097	0	0
T2	1958	1774	0	0
T3	3569	3495	0	0
T8	4440	4343	0	0
T15	2485	2406	0	0
T19	2484	2430	0	0
T20	1872	1820	0	0
T21	2006	1931	0	0
T22	1333	1277	0	0
T23	1095	1041	0	0

FpvSecCmCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	213976727	132	0	0
T5	1940	0	0	0
T6	0	1	0	0
T7	0	1	0	0
T9	2713	0	0	0
T10	4277	0	0	0
T14	662	1	0	0
T40	913857	0	0	0
T47	5420	0	0	0
T48	1872	0	0	0
T49	0	1	0	0
T54	1630	0	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	1889	0	0	0
T63	2046	0	0	0

FpvSecCmGenCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	213976727	80	0	0
T16	24625	10	0	0
T17	0	10	0	0
T18	0	20	0	0
T64	0	20	0	0
T65	0	20	0	0
T66	1085	0	0	0
T67	1288	0	0	0
T68	783	0	0	0
T69	1676	0	0	0
T70	2644	0	0	0
T71	1434	0	0	0
T72	1613	0	0	0
T73	1641	0	0	0
T74	3664	0	0	0

FpvSecCmGenCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	213976727	80	0	0
T16	24625	10	0	0
T17	0	10	0	0
T18	0	20	0	0
T64	0	20	0	0
T65	0	20	0	0
T66	1085	0	0	0
T67	1288	0	0	0
T68	783	0	0	0
T69	1676	0	0	0
T70	2644	0	0	0
T71	1434	0	0	0
T72	1613	0	0	0
T73	1641	0	0	0
T74	3664	0	0	0

FpvSecCmMainFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	213976727	80	0	0
T16	24625	10	0	0
T17	0	10	0	0
T18	0	20	0	0
T64	0	20	0	0
T65	0	20	0	0
T66	1085	0	0	0
T67	1288	0	0	0
T68	783	0	0	0
T69	1676	0	0	0
T70	2644	0	0	0
T71	1434	0	0	0
T72	1613	0	0	0
T73	1641	0	0	0
T74	3664	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	213976727	80	0	0
T16	24625	10	0	0
T17	0	10	0	0
T18	0	20	0	0
T64	0	20	0	0
T65	0	20	0	0
T66	1085	0	0	0
T67	1288	0	0	0
T68	783	0	0	0
T69	1676	0	0	0
T70	2644	0	0	0
T71	1434	0	0	0
T72	1613	0	0	0
T73	1641	0	0	0
T74	3664	0	0	0

FpvSecCmResCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	213976727	80	0	0
T16	24625	10	0	0
T17	0	10	0	0
T18	0	20	0	0
T64	0	20	0	0
T65	0	20	0	0
T66	1085	0	0	0
T67	1288	0	0	0
T68	783	0	0	0
T69	1676	0	0	0
T70	2644	0	0	0
T71	1434	0	0	0
T72	1613	0	0	0
T73	1641	0	0	0
T74	3664	0	0	0

FpvSecCmResCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	213976727	80	0	0
T16	24625	10	0	0
T17	0	10	0	0
T18	0	20	0	0
T64	0	20	0	0
T65	0	20	0	0
T66	1085	0	0	0
T67	1288	0	0	0
T68	783	0	0	0
T69	1676	0	0	0
T70	2644	0	0	0
T71	1434	0	0	0
T72	1613	0	0	0
T73	1641	0	0	0
T74	3664	0	0	0

IntrEdnCmdReqDoneKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	213976727	213797976	0	0
T1	1228	1097	0	0
T2	1958	1774	0	0
T3	3569	3495	0	0
T8	4440	4343	0	0
T15	2485	2406	0	0
T19	2484	2430	0	0
T20	1872	1820	0	0
T21	2006	1931	0	0
T22	1333	1277	0	0
T23	1095	1041	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	213976727	213797976	0	0
T1	1228	1097	0	0
T2	1958	1774	0	0
T3	3569	3495	0	0
T8	4440	4343	0	0
T15	2485	2406	0	0
T19	2484	2430	0	0
T20	1872	1820	0	0
T21	2006	1931	0	0
T22	1333	1277	0	0
T23	1095	1041	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	213976727	213797976	0	0
T1	1228	1097	0	0
T2	1958	1774	0	0
T3	3569	3495	0	0
T8	4440	4343	0	0
T15	2485	2406	0	0
T19	2484	2430	0	0
T20	1872	1820	0	0
T21	2006	1931	0	0
T22	1333	1277	0	0
T23	1095	1041	0	0

gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	213976727	80	0	0
T16	24625	10	0	0
T17	0	10	0	0
T18	0	20	0	0
T64	0	20	0	0
T65	0	20	0	0
T66	1085	0	0	0
T67	1288	0	0	0
T68	783	0	0	0
T69	1676	0	0	0
T70	2644	0	0	0
T71	1434	0	0	0
T72	1613	0	0	0
T73	1641	0	0	0
T74	3664	0	0	0

gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	213976727	80	0	0
T16	24625	10	0	0
T17	0	10	0	0
T18	0	20	0	0
T64	0	20	0	0
T65	0	20	0	0
T66	1085	0	0	0
T67	1288	0	0	0
T68	783	0	0	0
T69	1676	0	0	0
T70	2644	0	0	0
T71	1434	0	0	0
T72	1613	0	0	0
T73	1641	0	0	0
T74	3664	0	0	0

gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	213976727	80	0	0
T16	24625	10	0	0
T17	0	10	0	0
T18	0	20	0	0
T64	0	20	0	0
T65	0	20	0	0
T66	1085	0	0	0
T67	1288	0	0	0
T68	783	0	0	0
T69	1676	0	0	0
T70	2644	0	0	0
T71	1434	0	0	0
T72	1613	0	0	0
T73	1641	0	0	0
T74	3664	0	0	0

gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	213976727	80	0	0
T16	24625	10	0	0
T17	0	10	0	0
T18	0	20	0	0
T64	0	20	0	0
T65	0	20	0	0
T66	1085	0	0	0
T67	1288	0	0	0
T68	783	0	0	0
T69	1676	0	0	0
T70	2644	0	0	0
T71	1434	0	0	0
T72	1613	0	0	0
T73	1641	0	0	0
T74	3664	0	0	0

gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	213976727	80	0	0
T16	24625	10	0	0
T17	0	10	0	0
T18	0	20	0	0
T64	0	20	0	0
T65	0	20	0	0
T66	1085	0	0	0
T67	1288	0	0	0
T68	783	0	0	0
T69	1676	0	0	0
T70	2644	0	0	0
T71	1434	0	0	0
T72	1613	0	0	0
T73	1641	0	0	0
T74	3664	0	0	0

gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	213976727	80	0	0
T16	24625	10	0	0
T17	0	10	0	0
T18	0	20	0	0
T64	0	20	0	0
T65	0	20	0	0
T66	1085	0	0	0
T67	1288	0	0	0
T68	783	0	0	0
T69	1676	0	0	0
T70	2644	0	0	0
T71	1434	0	0	0
T72	1613	0	0	0
T73	1641	0	0	0
T74	3664	0	0	0

gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	213976727	80	0	0
T16	24625	10	0	0
T17	0	10	0	0
T18	0	20	0	0
T64	0	20	0	0
T65	0	20	0	0
T66	1085	0	0	0
T67	1288	0	0	0
T68	783	0	0	0
T69	1676	0	0	0
T70	2644	0	0	0
T71	1434	0	0	0
T72	1613	0	0	0
T73	1641	0	0	0
T74	3664	0	0	0

gen_edn_if_asserts[0].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	213976727	568657	0	326
T1	1228	666	0	0
T2	1958	1060	0	0
T3	3569	39	0	0
T8	4440	343	0	0
T9	0	0	0	2
T15	2485	533	0	0
T19	2484	21	0	0
T20	1872	20	0	0
T21	2006	36	0	0
T22	1333	89	0	0
T23	1095	135	0	0
T40	0	0	0	2
T41	0	0	0	2
T51	0	0	0	2
T54	0	0	0	2
T75	0	0	0	2
T76	0	0	0	2
T77	0	0	0	2
T78	0	0	0	2
T79	0	0	0	2

gen_edn_if_asserts[0].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	213976727	24974	0	342
T3	3569	15	0	1
T4	0	13	0	0
T8	4440	169	0	1
T15	2485	4	0	1
T19	2484	3	0	1
T20	1872	11	0	1
T21	2006	11	0	1
T22	1333	3	0	1
T23	1095	0	0	0
T43	3205	0	0	0
T44	0	3	0	1
T52	2002	65	0	1
T55	0	0	0	1

gen_edn_if_asserts[0].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	213976727	213797976	0	0
T1	1228	1097	0	0
T2	1958	1774	0	0
T3	3569	3495	0	0
T8	4440	4343	0	0
T15	2485	2406	0	0
T19	2484	2430	0	0
T20	1872	1820	0	0
T21	2006	1931	0	0
T22	1333	1277	0	0
T23	1095	1041	0	0

gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	213976727	148885	0	0
T1	1228	658	0	0
T2	1958	1161	0	0
T3	3569	0	0	0
T5	0	1082	0	0
T6	0	616	0	0
T7	0	413	0	0
T8	4440	0	0	0
T14	0	354	0	0
T15	2485	0	0	0
T19	2484	0	0	0
T20	1872	0	0	0
T21	2006	0	0	0
T22	1333	0	0	0
T23	1095	0	0	0
T29	0	1096	0	0
T36	0	629	0	0
T80	0	322	0	0
T81	0	1112	0	0

gen_edn_if_asserts[1].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	213976727	568657	0	326
T1	1228	666	0	0
T2	1958	1060	0	0
T3	3569	39	0	0
T8	4440	343	0	0
T9	0	0	0	2
T15	2485	533	0	0
T19	2484	21	0	0
T20	1872	20	0	0
T21	2006	36	0	0
T22	1333	89	0	0
T23	1095	135	0	0
T40	0	0	0	2
T41	0	0	0	2
T51	0	0	0	2
T54	0	0	0	2
T75	0	0	0	2
T76	0	0	0	2
T77	0	0	0	2
T78	0	0	0	2
T79	0	0	0	2

gen_edn_if_asserts[1].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	213976727	4967	0	112
T3	3569	41	0	1
T8	4440	0	0	0
T11	0	3	0	1
T12	0	0	0	1
T15	2485	0	0	0
T19	2484	0	0	0
T20	1872	0	0	0
T21	2006	0	0	0
T22	1333	0	0	0
T23	1095	0	0	0
T43	3205	53	0	1
T46	0	4	0	0
T47	0	49	0	1
T48	0	49	0	1
T50	0	3	0	1
T52	2002	0	0	0
T63	0	15	0	1
T78	0	4	0	0
T82	0	3	0	1
T83	0	0	0	1

gen_edn_if_asserts[1].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	213976727	213797976	0	0
T1	1228	1097	0	0
T2	1958	1774	0	0
T3	3569	3495	0	0
T8	4440	4343	0	0
T15	2485	2406	0	0
T19	2484	2430	0	0
T20	1872	1820	0	0
T21	2006	1931	0	0
T22	1333	1277	0	0
T23	1095	1041	0	0

gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	213976727	148885	0	0
T1	1228	658	0	0
T2	1958	1161	0	0
T3	3569	0	0	0
T5	0	1082	0	0
T6	0	616	0	0
T7	0	413	0	0
T8	4440	0	0	0
T14	0	354	0	0
T15	2485	0	0	0
T19	2484	0	0	0
T20	1872	0	0	0
T21	2006	0	0	0
T22	1333	0	0	0
T23	1095	0	0	0
T29	0	1096	0	0
T36	0	629	0	0
T80	0	322	0	0
T81	0	1112	0	0

gen_edn_if_asserts[2].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	213976727	568657	0	326
T1	1228	666	0	0
T2	1958	1060	0	0
T3	3569	39	0	0
T8	4440	343	0	0
T9	0	0	0	2
T15	2485	533	0	0
T19	2484	21	0	0
T20	1872	20	0	0
T21	2006	36	0	0
T22	1333	89	0	0
T23	1095	135	0	0
T40	0	0	0	2
T41	0	0	0	2
T51	0	0	0	2
T54	0	0	0	2
T75	0	0	0	2
T76	0	0	0	2
T77	0	0	0	2
T78	0	0	0	2
T79	0	0	0	2

gen_edn_if_asserts[2].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	213976727	4915	0	115
T3	3569	67	0	1
T8	4440	0	0	0
T10	0	411	0	1
T11	0	59	0	1
T12	0	53	0	1
T15	2485	0	0	0
T19	2484	0	0	0
T20	1872	0	0	0
T21	2006	0	0	0
T22	1333	0	0	0
T23	1095	0	0	0
T43	3205	0	0	0
T44	0	3	0	1
T45	0	3	0	1
T48	0	56	0	1
T52	2002	0	0	0
T82	0	24	0	1
T84	0	3	0	1
T85	0	50	0	1

gen_edn_if_asserts[2].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	213976727	213797976	0	0
T1	1228	1097	0	0
T2	1958	1774	0	0
T3	3569	3495	0	0
T8	4440	4343	0	0
T15	2485	2406	0	0
T19	2484	2430	0	0
T20	1872	1820	0	0
T21	2006	1931	0	0
T22	1333	1277	0	0
T23	1095	1041	0	0

gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	213976727	148885	0	0
T1	1228	658	0	0
T2	1958	1161	0	0
T3	3569	0	0	0
T5	0	1082	0	0
T6	0	616	0	0
T7	0	413	0	0
T8	4440	0	0	0
T14	0	354	0	0
T15	2485	0	0	0
T19	2484	0	0	0
T20	1872	0	0	0
T21	2006	0	0	0
T22	1333	0	0	0
T23	1095	0	0	0
T29	0	1096	0	0
T36	0	629	0	0
T80	0	322	0	0
T81	0	1112	0	0

gen_edn_if_asserts[3].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	213976727	568657	0	326
T1	1228	666	0	0
T2	1958	1060	0	0
T3	3569	39	0	0
T8	4440	343	0	0
T9	0	0	0	2
T15	2485	533	0	0
T19	2484	21	0	0
T20	1872	20	0	0
T21	2006	36	0	0
T22	1333	89	0	0
T23	1095	135	0	0
T40	0	0	0	2
T41	0	0	0	2
T51	0	0	0	2
T54	0	0	0	2
T75	0	0	0	2
T76	0	0	0	2
T77	0	0	0	2
T78	0	0	0	2
T79	0	0	0	2

gen_edn_if_asserts[3].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	213976727	4574	0	98
T3	3569	3	0	1
T8	4440	0	0	0
T10	0	3	0	1
T11	0	27	0	1
T13	0	3	0	1
T15	2485	0	0	0
T19	2484	0	0	0
T20	1872	0	0	0
T21	2006	0	0	0
T22	1333	0	0	0
T23	1095	0	0	0
T43	3205	0	0	0
T45	0	31	0	1
T52	2002	0	0	0
T75	0	4	0	0
T82	0	3	0	1
T86	0	3	0	1
T87	0	3	0	1
T88	0	4	0	0
T89	0	0	0	1
T90	0	0	0	1

gen_edn_if_asserts[3].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	213976727	213797976	0	0
T1	1228	1097	0	0
T2	1958	1774	0	0
T3	3569	3495	0	0
T8	4440	4343	0	0
T15	2485	2406	0	0
T19	2484	2430	0	0
T20	1872	1820	0	0
T21	2006	1931	0	0
T22	1333	1277	0	0
T23	1095	1041	0	0

gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	213976727	148885	0	0
T1	1228	658	0	0
T2	1958	1161	0	0
T3	3569	0	0	0
T5	0	1082	0	0
T6	0	616	0	0
T7	0	413	0	0
T8	4440	0	0	0
T14	0	354	0	0
T15	2485	0	0	0
T19	2484	0	0	0
T20	1872	0	0	0
T21	2006	0	0	0
T22	1333	0	0	0
T23	1095	0	0	0
T29	0	1096	0	0
T36	0	629	0	0
T80	0	322	0	0
T81	0	1112	0	0

gen_edn_if_asserts[4].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	213976727	568657	0	326
T1	1228	666	0	0
T2	1958	1060	0	0
T3	3569	39	0	0
T8	4440	343	0	0
T9	0	0	0	2
T15	2485	533	0	0
T19	2484	21	0	0
T20	1872	20	0	0
T21	2006	36	0	0
T22	1333	89	0	0
T23	1095	135	0	0
T40	0	0	0	2
T41	0	0	0	2
T51	0	0	0	2
T54	0	0	0	2
T75	0	0	0	2
T76	0	0	0	2
T77	0	0	0	2
T78	0	0	0	2
T79	0	0	0	2

gen_edn_if_asserts[4].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	213976727	3216	0	94
T3	3569	3	0	1
T8	4440	0	0	0
T10	0	45	0	1
T11	0	46	0	1
T12	0	50	0	1
T13	0	34	0	1
T15	2485	0	0	0
T19	2484	0	0	0
T20	1872	0	0	0
T21	2006	0	0	0
T22	1333	0	0	0
T23	1095	0	0	0
T27	0	4	0	0
T43	3205	0	0	0
T44	0	50	0	1
T52	2002	0	0	0
T82	0	23	0	1
T86	0	3	0	1
T89	0	0	0	1
T91	0	11	0	1

gen_edn_if_asserts[4].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	213976727	213797976	0	0
T1	1228	1097	0	0
T2	1958	1774	0	0
T3	3569	3495	0	0
T8	4440	4343	0	0
T15	2485	2406	0	0
T19	2484	2430	0	0
T20	1872	1820	0	0
T21	2006	1931	0	0
T22	1333	1277	0	0
T23	1095	1041	0	0

gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	213976727	148885	0	0
T1	1228	658	0	0
T2	1958	1161	0	0
T3	3569	0	0	0
T5	0	1082	0	0
T6	0	616	0	0
T7	0	413	0	0
T8	4440	0	0	0
T14	0	354	0	0
T15	2485	0	0	0
T19	2484	0	0	0
T20	1872	0	0	0
T21	2006	0	0	0
T22	1333	0	0	0
T23	1095	0	0	0
T29	0	1096	0	0
T36	0	629	0	0
T80	0	322	0	0
T81	0	1112	0	0

gen_edn_if_asserts[5].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	213976727	568657	0	326
T1	1228	666	0	0
T2	1958	1060	0	0
T3	3569	39	0	0
T8	4440	343	0	0
T9	0	0	0	2
T15	2485	533	0	0
T19	2484	21	0	0
T20	1872	20	0	0
T21	2006	36	0	0
T22	1333	89	0	0
T23	1095	135	0	0
T40	0	0	0	2
T41	0	0	0	2
T51	0	0	0	2
T54	0	0	0	2
T75	0	0	0	2
T76	0	0	0	2
T77	0	0	0	2
T78	0	0	0	2
T79	0	0	0	2

gen_edn_if_asserts[5].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	213976727	4487	0	90
T4	12232	0	0	0
T9	0	4	0	0
T10	0	3	0	1
T11	0	15	0	1
T12	0	39	0	1
T13	0	59	0	1
T14	662	0	0	0
T23	1095	4	0	0
T27	0	4	0	1
T36	1173	0	0	0
T43	3205	0	0	0
T44	3301	39	0	1
T46	769	0	0	0
T50	0	59	0	1
T52	2002	0	0	0
T55	23169	0	0	0
T62	1889	0	0	0
T87	0	0	0	1
T89	0	0	0	1
T92	0	19	0	1

gen_edn_if_asserts[5].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	213976727	213797976	0	0
T1	1228	1097	0	0
T2	1958	1774	0	0
T3	3569	3495	0	0
T8	4440	4343	0	0
T15	2485	2406	0	0
T19	2484	2430	0	0
T20	1872	1820	0	0
T21	2006	1931	0	0
T22	1333	1277	0	0
T23	1095	1041	0	0

gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	213976727	148885	0	0
T1	1228	658	0	0
T2	1958	1161	0	0
T3	3569	0	0	0
T5	0	1082	0	0
T6	0	616	0	0
T7	0	413	0	0
T8	4440	0	0	0
T14	0	354	0	0
T15	2485	0	0	0
T19	2484	0	0	0
T20	1872	0	0	0
T21	2006	0	0	0
T22	1333	0	0	0
T23	1095	0	0	0
T29	0	1096	0	0
T36	0	629	0	0
T80	0	322	0	0
T81	0	1112	0	0

gen_edn_if_asserts[6].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	213976727	568657	0	326
T1	1228	666	0	0
T2	1958	1060	0	0
T3	3569	39	0	0
T8	4440	343	0	0
T9	0	0	0	2
T15	2485	533	0	0
T19	2484	21	0	0
T20	1872	20	0	0
T21	2006	36	0	0
T22	1333	89	0	0
T23	1095	135	0	0
T40	0	0	0	2
T41	0	0	0	2
T51	0	0	0	2
T54	0	0	0	2
T75	0	0	0	2
T76	0	0	0	2
T77	0	0	0	2
T78	0	0	0	2
T79	0	0	0	2

gen_edn_if_asserts[6].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	213976727	3518	0	83
T9	2713	0	0	0
T10	0	37	0	1
T11	0	3	0	1
T12	0	25	0	1
T13	0	61	0	1
T14	662	0	0	0
T40	913857	0	0	0
T44	3301	43	0	1
T46	769	0	0	0
T47	5420	0	0	0
T48	1872	0	0	0
T51	0	4	0	0
T54	1630	0	0	0
T55	23169	0	0	0
T62	1889	0	0	0
T83	0	11	0	1
T87	0	0	0	1
T91	0	3	0	1
T93	0	3	0	1
T94	0	3	0	1

gen_edn_if_asserts[6].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	213976727	213797976	0	0
T1	1228	1097	0	0
T2	1958	1774	0	0
T3	3569	3495	0	0
T8	4440	4343	0	0
T15	2485	2406	0	0
T19	2484	2430	0	0
T20	1872	1820	0	0
T21	2006	1931	0	0
T22	1333	1277	0	0
T23	1095	1041	0	0

gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	213976727	148885	0	0
T1	1228	658	0	0
T2	1958	1161	0	0
T3	3569	0	0	0
T5	0	1082	0	0
T6	0	616	0	0
T7	0	413	0	0
T8	4440	0	0	0
T14	0	354	0	0
T15	2485	0	0	0
T19	2484	0	0	0
T20	1872	0	0	0
T21	2006	0	0	0
T22	1333	0	0	0
T23	1095	0	0	0
T29	0	1096	0	0
T36	0	629	0	0
T80	0	322	0	0
T81	0	1112	0	0