Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44		83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	214514609	9447902	0	0
boot_gen_cmd_rd_A	214514609	79003	0	0
boot_ins_cmd_rd_A	214514609	91809	0	0
ctrl_rd_A	214514609	79773	0	0
err_code_test_rd_A	214514609	91996	0	0
intr_enable_rd_A	214514609	89037	0	0
max_num_reqs_between_reseeds_rd_A	214514609	81762	0	0
regwen_rd_A	214514609	94137	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	214514609	9447902	0	0
T5	1940	0	0	0
T9	2713	0	0	0
T10	4277	0	0	0
T27	2604	0	0	0
T40	913857	510490	0	0
T41	0	238981	0	0
T42	0	97335	0	0
T45	3339	0	0	0
T50	2290	0	0	0
T63	2046	0	0	0
T75	4178	0	0	0
T162	4377	0	0	0
T197	0	161638	0	0
T198	0	69452	0	0
T199	0	212866	0	0
T200	0	350951	0	0
T201	0	89997	0	0
T202	0	122272	0	0
T203	0	212358	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	214514609	79003	0	0
T24	1552	0	0	0
T124	3528	0	0	0
T137	1036	0	0	0
T152	2311	0	0	0
T155	1161	0	0	0
T164	2670	0	0	0
T181	0	7336	0	0
T197	476988	4339	0	0
T199	0	6529	0	0
T201	0	2587	0	0
T204	0	8415	0	0
T205	0	5658	0	0
T206	0	4847	0	0
T207	0	1534	0	0
T208	0	4272	0	0
T209	0	2960	0	0
T210	7171	0	0	0
T211	5685	0	0	0
T212	9136	0	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	214514609	91809	0	0
T24	1552	0	0	0
T124	3528	0	0	0
T137	1036	0	0	0
T152	2311	0	0	0
T155	1161	0	0	0
T164	2670	0	0	0
T181	0	8155	0	0
T197	476988	5355	0	0
T199	0	7244	0	0
T201	0	3131	0	0
T204	0	9497	0	0
T205	0	6873	0	0
T206	0	5711	0	0
T207	0	1907	0	0
T208	0	4961	0	0
T209	0	3458	0	0
T210	7171	0	0	0
T211	5685	0	0	0
T212	9136	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	214514609	79773	0	0
T2	1958	2	0	0
T3	3569	0	0	0
T8	4440	0	0	0
T15	2485	0	0	0
T19	2484	0	0	0
T20	1872	0	0	0
T21	2006	0	0	0
T22	1333	0	0	0
T23	1095	0	0	0
T24	0	3	0	0
T52	2002	0	0	0
T55	0	1	0	0
T75	0	4	0	0
T197	0	4919	0	0
T199	0	6589	0	0
T201	0	2628	0	0
T213	0	4	0	0
T214	0	2	0	0
T215	0	5	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	214514609	91996	0	0
T24	1552	0	0	0
T124	3528	0	0	0
T137	1036	0	0	0
T152	2311	0	0	0
T155	1161	0	0	0
T164	2670	0	0	0
T181	0	8634	0	0
T197	476988	5172	0	0
T199	0	7104	0	0
T201	0	3083	0	0
T204	0	9665	0	0
T205	0	6571	0	0
T206	0	5665	0	0
T207	0	1808	0	0
T208	0	5141	0	0
T209	0	3449	0	0
T210	7171	0	0	0
T211	5685	0	0	0
T212	9136	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	214514609	89037	0	0
T9	2713	0	0	0
T10	4277	0	0	0
T14	662	0	0	0
T40	913857	0	0	0
T47	5420	0	0	0
T48	1872	0	0	0
T54	1630	0	0	0
T55	23169	89	0	0
T62	1889	0	0	0
T63	2046	0	0	0
T197	0	5042	0	0
T199	0	6548	0	0
T201	0	3156	0	0
T204	0	8623	0	0
T205	0	5788	0	0
T216	0	93	0	0
T217	0	28	0	0
T218	0	49	0	0
T219	0	39	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	214514609	81762	0	0
T24	1552	0	0	0
T124	3528	0	0	0
T137	1036	0	0	0
T152	2311	0	0	0
T155	1161	0	0	0
T164	2670	0	0	0
T181	0	7918	0	0
T197	476988	4687	0	0
T199	0	6234	0	0
T201	0	2753	0	0
T204	0	7917	0	0
T205	0	5924	0	0
T206	0	5170	0	0
T207	0	1356	0	0
T208	0	4461	0	0
T209	0	2757	0	0
T210	7171	0	0	0
T211	5685	0	0	0
T212	9136	0	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	214514609	94137	0	0
T24	1552	0	0	0
T124	3528	0	0	0
T137	1036	0	0	0
T152	2311	0	0	0
T155	1161	0	0	0
T164	2670	0	0	0
T181	0	8589	0	0
T197	476988	5414	0	0
T199	0	7024	0	0
T201	0	3186	0	0
T204	0	10490	0	0
T205	0	6732	0	0
T206	0	5767	0	0
T207	0	1986	0	0
T208	0	4949	0	0
T209	0	3412	0	0
T210	7171	0	0	0
T211	5685	0	0	0
T212	9136	0	0	0