Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44		83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	230793091	10194988	0	0
boot_gen_cmd_rd_A	230793091	70550	0	0
boot_ins_cmd_rd_A	230793091	81939	0	0
ctrl_rd_A	230793091	71071	0	0
err_code_test_rd_A	230793091	80498	0	0
intr_enable_rd_A	230793091	76987	0	0
max_num_reqs_between_reseeds_rd_A	230793091	70084	0	0
regwen_rd_A	230793091	81367	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230793091	10194988	0	0
T6	1086	0	0	0
T13	3529	0	0	0
T14	2287	0	0	0
T38	654435	378349	0	0
T39	479063	265166	0	0
T40	0	76164	0	0
T41	1830	0	0	0
T51	1862	0	0	0
T52	842	0	0	0
T71	0	65834	0	0
T76	0	176823	0	0
T78	0	129821	0	0
T79	1756	0	0	0
T80	822	0	0	0
T205	0	439154	0	0
T206	0	173386	0	0
T207	0	250668	0	0
T208	0	179612	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230793091	70550	0	0
T19	2642	0	0	0
T54	2287	0	0	0
T78	383872	3396	0	0
T83	2912	0	0	0
T105	1486	0	0	0
T119	735	0	0	0
T154	1849	0	0	0
T168	1452	0	0	0
T178	2074	0	0	0
T205	777937	0	0	0
T206	0	4891	0	0
T208	0	5039	0	0
T209	0	3653	0	0
T210	0	5912	0	0
T211	0	16993	0	0
T212	0	1353	0	0
T213	0	1436	0	0
T214	0	3118	0	0
T215	0	306	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230793091	81939	0	0
T19	2642	0	0	0
T54	2287	0	0	0
T78	383872	4016	0	0
T83	2912	0	0	0
T105	1486	0	0	0
T119	735	0	0	0
T154	1849	0	0	0
T168	1452	0	0	0
T178	2074	0	0	0
T205	777937	0	0	0
T206	0	5458	0	0
T208	0	5755	0	0
T209	0	4189	0	0
T210	0	7172	0	0
T211	0	19755	0	0
T212	0	1385	0	0
T213	0	1750	0	0
T214	0	3871	0	0
T215	0	297	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230793091	71071	0	0
T19	2642	0	0	0
T54	2287	0	0	0
T56	0	4	0	0
T78	383872	3527	0	0
T83	2912	0	0	0
T105	1486	2	0	0
T119	735	0	0	0
T154	1849	0	0	0
T168	1452	0	0	0
T178	2074	0	0	0
T205	777937	0	0	0
T206	0	5010	0	0
T208	0	5134	0	0
T209	0	3761	0	0
T210	0	5938	0	0
T211	0	16813	0	0
T216	0	4	0	0
T217	0	4	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230793091	80498	0	0
T19	2642	0	0	0
T54	2287	0	0	0
T78	383872	3889	0	0
T83	2912	0	0	0
T105	1486	0	0	0
T119	735	0	0	0
T154	1849	0	0	0
T168	1452	0	0	0
T178	2074	0	0	0
T205	777937	0	0	0
T206	0	5909	0	0
T208	0	5998	0	0
T209	0	4289	0	0
T210	0	6607	0	0
T211	0	19245	0	0
T212	0	1375	0	0
T213	0	1583	0	0
T214	0	3711	0	0
T215	0	271	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230793091	76987	0	0
T19	2642	0	0	0
T54	2287	0	0	0
T78	383872	3951	0	0
T83	2912	0	0	0
T105	1486	0	0	0
T119	735	0	0	0
T154	1849	0	0	0
T168	1452	0	0	0
T178	2074	0	0	0
T205	777937	0	0	0
T206	0	5637	0	0
T208	0	5385	0	0
T209	0	3947	0	0
T210	0	6208	0	0
T211	0	17110	0	0
T212	0	1473	0	0
T213	0	1416	0	0
T216	0	51	0	0
T218	0	5	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230793091	70084	0	0
T19	2642	0	0	0
T54	2287	0	0	0
T78	383872	3602	0	0
T83	2912	0	0	0
T105	1486	0	0	0
T119	735	0	0	0
T154	1849	0	0	0
T168	1452	0	0	0
T178	2074	0	0	0
T205	777937	0	0	0
T206	0	4950	0	0
T208	0	5037	0	0
T209	0	3505	0	0
T210	0	6127	0	0
T211	0	16361	0	0
T212	0	1239	0	0
T213	0	1185	0	0
T214	0	3297	0	0
T215	0	314	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230793091	81367	0	0
T19	2642	0	0	0
T54	2287	0	0	0
T78	383872	4048	0	0
T83	2912	0	0	0
T105	1486	0	0	0
T119	735	0	0	0
T154	1849	0	0	0
T168	1452	0	0	0
T178	2074	0	0	0
T205	777937	0	0	0
T206	0	5643	0	0
T208	0	5920	0	0
T209	0	4322	0	0
T210	0	7049	0	0
T211	0	19000	0	0
T212	0	1573	0	0
T213	0	1424	0	0
T214	0	3646	0	0
T215	0	366	0	0