Unified Coverage Report :: Module :: edn

Module : edn

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	94.44		83.33	100.00			100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.15	98.24	93.80	97.02	85.47	96.62	99.77

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
edn_csr_assert	100.00						100.00
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_edn_core	93.09	99.92	92.46	82.54	85.47	99.28	98.88
u_edn_cov_if	25.00	50.00	0.00
u_reg	96.95	95.02	97.57	100.00		92.16	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Cond Coverage for Module : edn

	Total	Covered	Percent
Conditions	6	5	83.33
Logical	6	5	83.33
Non-Logical	0	0
Event	0	0

 LINE       98
 EXPRESSION (alert[0] || intg_err_alert[0])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T28,T29,T30

 LINE       98
 EXPRESSION (alert[1] || intg_err_alert[1])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T16,T17,T18
1	0	Covered	T2,T4,T5

---

Toggle Coverage for Module : edn

	Total	Covered	Percent
Totals	69	69	100.00
Total Bits	1172	1172	100.00
Total Bits 0->1	586	586	100.00
Total Bits 1->0	586	586	100.00

Ports	69	69	100.00
Port Bits	1172	1172	100.00
Port Bits 0->1	586	586	100.00
Port Bits 1->0	586	586	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T4,T5	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T2,T9,T4	Yes	T2,T9,T4	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T38,T39,T40	Yes	T38,T39,T40	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T3,T22	Yes	T1,T3,T22	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i[0].edn_req	Yes	Yes	T3,T22,T23	Yes	T3,T22,T23	INPUT
edn_i[1].edn_req	Yes	Yes	T23,T4,T5	Yes	T23,T4,T5	INPUT
edn_i[2].edn_req	Yes	Yes	T1,T2,T41	Yes	T1,T2,T41	INPUT
edn_i[3].edn_req	Yes	Yes	T1,T13,T41	Yes	T1,T13,T41	INPUT
edn_i[4].edn_req	Yes	Yes	T1,T9,T14	Yes	T1,T9,T14	INPUT
edn_i[5].edn_req	Yes	Yes	T9,T13,T41	Yes	T9,T13,T41	INPUT
edn_i[6].edn_req	Yes	Yes	T9,T42,T43	Yes	T9,T42,T43	INPUT
edn_o[0].edn_bus[31:0]	Yes	Yes	T3,T22,T23	Yes	T3,T22,T23	OUTPUT
edn_o[0].edn_fips	Yes	Yes	T3,T22,T23	Yes	T3,T22,T23	OUTPUT
edn_o[0].edn_ack	Yes	Yes	T3,T22,T23	Yes	T3,T22,T23	OUTPUT
edn_o[1].edn_bus[31:0]	Yes	Yes	T23,T13,T41	Yes	T23,T13,T41	OUTPUT
edn_o[1].edn_fips	Yes	Yes	T23,T44,T45	Yes	T23,T13,T41	OUTPUT
edn_o[1].edn_ack	Yes	Yes	T23,T5,T13	Yes	T23,T5,T13	OUTPUT
edn_o[2].edn_bus[31:0]	Yes	Yes	T1,T41,T28	Yes	T1,T41,T28	OUTPUT
edn_o[2].edn_fips	Yes	Yes	T41,T46,T47	Yes	T1,T41,T28	OUTPUT
edn_o[2].edn_ack	Yes	Yes	T1,T41,T28	Yes	T1,T41,T28	OUTPUT
edn_o[3].edn_bus[31:0]	Yes	Yes	T1,T13,T41	Yes	T1,T13,T41	OUTPUT
edn_o[3].edn_fips	Yes	Yes	T1,T41,T43	Yes	T1,T13,T41	OUTPUT
edn_o[3].edn_ack	Yes	Yes	T1,T13,T41	Yes	T1,T13,T41	OUTPUT
edn_o[4].edn_bus[31:0]	Yes	Yes	T1,T9,T14	Yes	T1,T9,T14	OUTPUT
edn_o[4].edn_fips	Yes	Yes	T1,T14,T42	Yes	T1,T14,T46	OUTPUT
edn_o[4].edn_ack	Yes	Yes	T1,T9,T14	Yes	T1,T9,T14	OUTPUT
edn_o[5].edn_bus[31:0]	Yes	Yes	T9,T13,T41	Yes	T9,T13,T41	OUTPUT
edn_o[5].edn_fips	Yes	Yes	T9,T13,T41	Yes	T9,T13,T41	OUTPUT
edn_o[5].edn_ack	Yes	Yes	T9,T13,T41	Yes	T9,T13,T41	OUTPUT
edn_o[6].edn_bus[31:0]	Yes	Yes	T9,T42,T43	Yes	T9,T42,T43	OUTPUT
edn_o[6].edn_fips	Yes	Yes	T9,T48,T11	Yes	T9,T43,T48	OUTPUT
edn_o[6].edn_ack	Yes	Yes	T9,T42,T43	Yes	T9,T42,T43	OUTPUT
csrng_cmd_o.genbits_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_bus[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_i.genbits_bus[127:0]	Yes	Yes	T1,T3,T22	Yes	T1,T22,T9	INPUT
csrng_cmd_i.genbits_fips	Yes	Yes	T1,T3,T22	Yes	T1,T3,T22	INPUT
csrng_cmd_i.genbits_valid	Yes	Yes	T1,T3,T22	Yes	T1,T3,T22	INPUT
csrng_cmd_i.csrng_rsp_sts[2:0]	Yes	Yes	T28,T49,T50	Yes	T28,T49,T50	INPUT
csrng_cmd_i.csrng_rsp_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_req_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T24,T51,T52	Yes	T24,T51,T52	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T2,T24,T4	Yes	T2,T24,T4	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T24,T51,T52	Yes	T24,T51,T52	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T2,T24,T4	Yes	T2,T24,T4	OUTPUT
intr_edn_cmd_req_done_o	Yes	Yes	T38,T39,T53	Yes	T38,T39,T53	OUTPUT
intr_edn_fatal_err_o	Yes	Yes	T5,T38,T39	Yes	T5,T38,T39	OUTPUT

*Tests covering at least one bit in the range

---

Assert Coverage for Module : edn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	47	47	100.00	47	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	47	47	100.00	47	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxKnownO_A	230342208	230173598	0	0
CsrngAppIfOut_A	230342208	230173598	0	0
FpvSecCmCntAlertCheck_A	230342208	111	0	0
FpvSecCmGenCmdFifoRptrCheck_A	230342208	70	0	0
FpvSecCmGenCmdFifoWptrCheck_A	230342208	70	0	0
FpvSecCmMainFsmCheck_A	230342208	70	0	0
FpvSecCmRegWeOnehotCheck_A	230342208	70	0	0
FpvSecCmResCmdFifoRptrCheck_A	230342208	70	0	0
FpvSecCmResCmdFifoWptrCheck_A	230342208	70	0	0
IntrEdnCmdReqDoneKnownO_A	230342208	230173598	0	0
TlAReadyKnownO_A	230342208	230173598	0	0
TlDValidKnownO_A	230342208	230173598	0	0
gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A	230342208	70	0	0
gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A	230342208	70	0	0
gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A	230342208	70	0	0
gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A	230342208	70	0	0
gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A	230342208	70	0	0
gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A	230342208	70	0	0
gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A	230342208	70	0	0
gen_edn_if_asserts[0].EdnDataStableDisable_A	230342208	553559	0	324
gen_edn_if_asserts[0].EdnDataStable_A	230342208	25869	0	330
gen_edn_if_asserts[0].EdnEndPointOut_A	230342208	230173598	0	0
gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A	230342208	149462	0	0
gen_edn_if_asserts[1].EdnDataStableDisable_A	230342208	553559	0	324
gen_edn_if_asserts[1].EdnDataStable_A	230342208	4057	0	120
gen_edn_if_asserts[1].EdnEndPointOut_A	230342208	230173598	0	0
gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A	230342208	149462	0	0
gen_edn_if_asserts[2].EdnDataStableDisable_A	230342208	553559	0	324
gen_edn_if_asserts[2].EdnDataStable_A	230342208	2966	0	112
gen_edn_if_asserts[2].EdnEndPointOut_A	230342208	230173598	0	0
gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A	230342208	149462	0	0
gen_edn_if_asserts[3].EdnDataStableDisable_A	230342208	553559	0	324
gen_edn_if_asserts[3].EdnDataStable_A	230342208	3670	0	94
gen_edn_if_asserts[3].EdnEndPointOut_A	230342208	230173598	0	0
gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A	230342208	149462	0	0
gen_edn_if_asserts[4].EdnDataStableDisable_A	230342208	553559	0	324
gen_edn_if_asserts[4].EdnDataStable_A	230342208	2790	0	104
gen_edn_if_asserts[4].EdnEndPointOut_A	230342208	230173598	0	0
gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A	230342208	149462	0	0
gen_edn_if_asserts[5].EdnDataStableDisable_A	230342208	553559	0	324
gen_edn_if_asserts[5].EdnDataStable_A	230342208	4479	0	93
gen_edn_if_asserts[5].EdnEndPointOut_A	230342208	230173598	0	0
gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A	230342208	149462	0	0
gen_edn_if_asserts[6].EdnDataStableDisable_A	230342208	553559	0	324
gen_edn_if_asserts[6].EdnDataStable_A	230342208	52320	0	71
gen_edn_if_asserts[6].EdnEndPointOut_A	230342208	230173598	0	0
gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A	230342208	149462	0	0

AlertTxKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230342208	230173598	0	0
T1	2524	2443	0	0
T2	783	612	0	0
T3	5582	5493	0	0
T4	1233	1118	0	0
T5	711	555	0	0
T9	4617	4517	0	0
T10	3671	3579	0	0
T22	3362	3298	0	0
T23	1325	1274	0	0
T24	1743	1664	0	0

CsrngAppIfOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230342208	230173598	0	0
T1	2524	2443	0	0
T2	783	612	0	0
T3	5582	5493	0	0
T4	1233	1118	0	0
T5	711	555	0	0
T9	4617	4517	0	0
T10	3671	3579	0	0
T22	3362	3298	0	0
T23	1325	1274	0	0
T24	1743	1664	0	0

FpvSecCmCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230342208	111	0	0
T6	1086	1	0	0
T7	1890	0	0	0
T14	2287	1	0	0
T15	0	1	0	0
T16	0	10	0	0
T21	2197	0	0	0
T28	1866	0	0	0
T41	1830	0	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	3761	0	0	0
T61	2802	0	0	0
T62	931	0	0	0
T63	2712	0	0	0

FpvSecCmGenCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230342208	70	0	0
T16	23916	10	0	0
T17	0	10	0	0
T18	0	20	0	0
T64	0	20	0	0
T65	0	10	0	0
T66	3176	0	0	0
T67	6598	0	0	0
T68	1012	0	0	0
T69	1001	0	0	0
T70	1488	0	0	0
T71	157234	0	0	0
T72	4445	0	0	0
T73	2569	0	0	0
T74	1347	0	0	0

FpvSecCmGenCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230342208	70	0	0
T16	23916	10	0	0
T17	0	10	0	0
T18	0	20	0	0
T64	0	20	0	0
T65	0	10	0	0
T66	3176	0	0	0
T67	6598	0	0	0
T68	1012	0	0	0
T69	1001	0	0	0
T70	1488	0	0	0
T71	157234	0	0	0
T72	4445	0	0	0
T73	2569	0	0	0
T74	1347	0	0	0

FpvSecCmMainFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230342208	70	0	0
T16	23916	10	0	0
T17	0	10	0	0
T18	0	20	0	0
T64	0	20	0	0
T65	0	10	0	0
T66	3176	0	0	0
T67	6598	0	0	0
T68	1012	0	0	0
T69	1001	0	0	0
T70	1488	0	0	0
T71	157234	0	0	0
T72	4445	0	0	0
T73	2569	0	0	0
T74	1347	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230342208	70	0	0
T16	23916	10	0	0
T17	0	10	0	0
T18	0	20	0	0
T64	0	20	0	0
T65	0	10	0	0
T66	3176	0	0	0
T67	6598	0	0	0
T68	1012	0	0	0
T69	1001	0	0	0
T70	1488	0	0	0
T71	157234	0	0	0
T72	4445	0	0	0
T73	2569	0	0	0
T74	1347	0	0	0

FpvSecCmResCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230342208	70	0	0
T16	23916	10	0	0
T17	0	10	0	0
T18	0	20	0	0
T64	0	20	0	0
T65	0	10	0	0
T66	3176	0	0	0
T67	6598	0	0	0
T68	1012	0	0	0
T69	1001	0	0	0
T70	1488	0	0	0
T71	157234	0	0	0
T72	4445	0	0	0
T73	2569	0	0	0
T74	1347	0	0	0

FpvSecCmResCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230342208	70	0	0
T16	23916	10	0	0
T17	0	10	0	0
T18	0	20	0	0
T64	0	20	0	0
T65	0	10	0	0
T66	3176	0	0	0
T67	6598	0	0	0
T68	1012	0	0	0
T69	1001	0	0	0
T70	1488	0	0	0
T71	157234	0	0	0
T72	4445	0	0	0
T73	2569	0	0	0
T74	1347	0	0	0

IntrEdnCmdReqDoneKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230342208	230173598	0	0
T1	2524	2443	0	0
T2	783	612	0	0
T3	5582	5493	0	0
T4	1233	1118	0	0
T5	711	555	0	0
T9	4617	4517	0	0
T10	3671	3579	0	0
T22	3362	3298	0	0
T23	1325	1274	0	0
T24	1743	1664	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230342208	230173598	0	0
T1	2524	2443	0	0
T2	783	612	0	0
T3	5582	5493	0	0
T4	1233	1118	0	0
T5	711	555	0	0
T9	4617	4517	0	0
T10	3671	3579	0	0
T22	3362	3298	0	0
T23	1325	1274	0	0
T24	1743	1664	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230342208	230173598	0	0
T1	2524	2443	0	0
T2	783	612	0	0
T3	5582	5493	0	0
T4	1233	1118	0	0
T5	711	555	0	0
T9	4617	4517	0	0
T10	3671	3579	0	0
T22	3362	3298	0	0
T23	1325	1274	0	0
T24	1743	1664	0	0

gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230342208	70	0	0
T16	23916	10	0	0
T17	0	10	0	0
T18	0	20	0	0
T64	0	20	0	0
T65	0	10	0	0
T66	3176	0	0	0
T67	6598	0	0	0
T68	1012	0	0	0
T69	1001	0	0	0
T70	1488	0	0	0
T71	157234	0	0	0
T72	4445	0	0	0
T73	2569	0	0	0
T74	1347	0	0	0

gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230342208	70	0	0
T16	23916	10	0	0
T17	0	10	0	0
T18	0	20	0	0
T64	0	20	0	0
T65	0	10	0	0
T66	3176	0	0	0
T67	6598	0	0	0
T68	1012	0	0	0
T69	1001	0	0	0
T70	1488	0	0	0
T71	157234	0	0	0
T72	4445	0	0	0
T73	2569	0	0	0
T74	1347	0	0	0

gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230342208	70	0	0
T16	23916	10	0	0
T17	0	10	0	0
T18	0	20	0	0
T64	0	20	0	0
T65	0	10	0	0
T66	3176	0	0	0
T67	6598	0	0	0
T68	1012	0	0	0
T69	1001	0	0	0
T70	1488	0	0	0
T71	157234	0	0	0
T72	4445	0	0	0
T73	2569	0	0	0
T74	1347	0	0	0

gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230342208	70	0	0
T16	23916	10	0	0
T17	0	10	0	0
T18	0	20	0	0
T64	0	20	0	0
T65	0	10	0	0
T66	3176	0	0	0
T67	6598	0	0	0
T68	1012	0	0	0
T69	1001	0	0	0
T70	1488	0	0	0
T71	157234	0	0	0
T72	4445	0	0	0
T73	2569	0	0	0
T74	1347	0	0	0

gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230342208	70	0	0
T16	23916	10	0	0
T17	0	10	0	0
T18	0	20	0	0
T64	0	20	0	0
T65	0	10	0	0
T66	3176	0	0	0
T67	6598	0	0	0
T68	1012	0	0	0
T69	1001	0	0	0
T70	1488	0	0	0
T71	157234	0	0	0
T72	4445	0	0	0
T73	2569	0	0	0
T74	1347	0	0	0

gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230342208	70	0	0
T16	23916	10	0	0
T17	0	10	0	0
T18	0	20	0	0
T64	0	20	0	0
T65	0	10	0	0
T66	3176	0	0	0
T67	6598	0	0	0
T68	1012	0	0	0
T69	1001	0	0	0
T70	1488	0	0	0
T71	157234	0	0	0
T72	4445	0	0	0
T73	2569	0	0	0
T74	1347	0	0	0

gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230342208	70	0	0
T16	23916	10	0	0
T17	0	10	0	0
T18	0	20	0	0
T64	0	20	0	0
T65	0	10	0	0
T66	3176	0	0	0
T67	6598	0	0	0
T68	1012	0	0	0
T69	1001	0	0	0
T70	1488	0	0	0
T71	157234	0	0	0
T72	4445	0	0	0
T73	2569	0	0	0
T74	1347	0	0	0

gen_edn_if_asserts[0].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230342208	553559	0	324
T1	2524	32	0	0
T2	783	333	0	0
T3	5582	40	0	0
T4	1233	628	0	0
T5	711	153	0	0
T9	4617	81	0	0
T10	3671	205	0	0
T22	3362	23	0	0
T23	1325	124	0	0
T24	1743	1662	0	2
T38	0	0	0	2
T39	0	0	0	2
T40	0	0	0	2
T51	0	0	0	2
T52	0	0	0	2
T75	0	0	0	2
T76	0	0	0	2
T77	0	0	0	2
T78	0	0	0	2

gen_edn_if_asserts[0].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230342208	25869	0	330
T3	5582	31	0	1
T4	1233	0	0	0
T5	711	0	0	0
T6	0	1	0	0
T9	4617	0	0	0
T10	3671	24	0	1
T21	0	0	0	1
T22	3362	48	0	1
T23	1325	41	0	1
T24	1743	0	0	0
T38	654435	87	0	0
T39	0	84	0	0
T41	0	30	0	1
T60	0	0	0	1
T63	0	0	0	1
T79	1756	13	0	1
T80	0	3	0	1

gen_edn_if_asserts[0].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230342208	230173598	0	0
T1	2524	2443	0	0
T2	783	612	0	0
T3	5582	5493	0	0
T4	1233	1118	0	0
T5	711	555	0	0
T9	4617	4517	0	0
T10	3671	3579	0	0
T22	3362	3298	0	0
T23	1325	1274	0	0
T24	1743	1664	0	0

gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230342208	149462	0	0
T2	783	362	0	0
T3	5582	0	0	0
T4	1233	656	0	0
T5	711	226	0	0
T6	0	381	0	0
T7	0	1092	0	0
T8	0	352	0	0
T9	4617	0	0	0
T10	3671	0	0	0
T14	0	1124	0	0
T22	3362	0	0	0
T23	1325	0	0	0
T24	1743	0	0	0
T38	654435	0	0	0
T61	0	1072	0	0
T81	0	1113	0	0
T82	0	212	0	0

gen_edn_if_asserts[1].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230342208	553559	0	324
T1	2524	32	0	0
T2	783	333	0	0
T3	5582	40	0	0
T4	1233	628	0	0
T5	711	153	0	0
T9	4617	81	0	0
T10	3671	205	0	0
T22	3362	23	0	0
T23	1325	124	0	0
T24	1743	1662	0	2
T38	0	0	0	2
T39	0	0	0	2
T40	0	0	0	2
T51	0	0	0	2
T52	0	0	0	2
T75	0	0	0	2
T76	0	0	0	2
T77	0	0	0	2
T78	0	0	0	2

gen_edn_if_asserts[1].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230342208	4057	0	120
T4	1233	0	0	0
T5	711	1	0	0
T10	3671	0	0	0
T13	3529	3	0	1
T23	1325	20	0	1
T24	1743	0	0	0
T38	654435	0	0	0
T39	479063	0	0	0
T41	0	3	0	1
T43	0	3	0	1
T44	0	35	0	1
T45	0	0	0	1
T46	0	3	0	1
T47	0	3	0	1
T51	1862	0	0	0
T62	0	3	0	1
T75	0	4	0	0
T79	1756	0	0	0
T83	0	0	0	1

gen_edn_if_asserts[1].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230342208	230173598	0	0
T1	2524	2443	0	0
T2	783	612	0	0
T3	5582	5493	0	0
T4	1233	1118	0	0
T5	711	555	0	0
T9	4617	4517	0	0
T10	3671	3579	0	0
T22	3362	3298	0	0
T23	1325	1274	0	0
T24	1743	1664	0	0

gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230342208	149462	0	0
T2	783	362	0	0
T3	5582	0	0	0
T4	1233	656	0	0
T5	711	226	0	0
T6	0	381	0	0
T7	0	1092	0	0
T8	0	352	0	0
T9	4617	0	0	0
T10	3671	0	0	0
T14	0	1124	0	0
T22	3362	0	0	0
T23	1325	0	0	0
T24	1743	0	0	0
T38	654435	0	0	0
T61	0	1072	0	0
T81	0	1113	0	0
T82	0	212	0	0

gen_edn_if_asserts[2].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230342208	553559	0	324
T1	2524	32	0	0
T2	783	333	0	0
T3	5582	40	0	0
T4	1233	628	0	0
T5	711	153	0	0
T9	4617	81	0	0
T10	3671	205	0	0
T22	3362	23	0	0
T23	1325	124	0	0
T24	1743	1662	0	2
T38	0	0	0	2
T39	0	0	0	2
T40	0	0	0	2
T51	0	0	0	2
T52	0	0	0	2
T75	0	0	0	2
T76	0	0	0	2
T77	0	0	0	2
T78	0	0	0	2

gen_edn_if_asserts[2].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230342208	2966	0	112
T1	2524	3	0	1
T2	783	0	0	0
T3	5582	0	0	0
T4	1233	0	0	0
T5	711	0	0	0
T9	4617	0	0	0
T10	3671	0	0	0
T22	3362	0	0	0
T23	1325	0	0	0
T24	1743	0	0	0
T28	0	4	0	1
T41	0	25	0	1
T42	0	11	0	1
T43	0	3	0	1
T44	0	3	0	1
T46	0	27	0	1
T47	0	17	0	1
T48	0	13	0	1
T84	0	3	0	1

gen_edn_if_asserts[2].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230342208	230173598	0	0
T1	2524	2443	0	0
T2	783	612	0	0
T3	5582	5493	0	0
T4	1233	1118	0	0
T5	711	555	0	0
T9	4617	4517	0	0
T10	3671	3579	0	0
T22	3362	3298	0	0
T23	1325	1274	0	0
T24	1743	1664	0	0

gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230342208	149462	0	0
T2	783	362	0	0
T3	5582	0	0	0
T4	1233	656	0	0
T5	711	226	0	0
T6	0	381	0	0
T7	0	1092	0	0
T8	0	352	0	0
T9	4617	0	0	0
T10	3671	0	0	0
T14	0	1124	0	0
T22	3362	0	0	0
T23	1325	0	0	0
T24	1743	0	0	0
T38	654435	0	0	0
T61	0	1072	0	0
T81	0	1113	0	0
T82	0	212	0	0

gen_edn_if_asserts[3].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230342208	553559	0	324
T1	2524	32	0	0
T2	783	333	0	0
T3	5582	40	0	0
T4	1233	628	0	0
T5	711	153	0	0
T9	4617	81	0	0
T10	3671	205	0	0
T22	3362	23	0	0
T23	1325	124	0	0
T24	1743	1662	0	2
T38	0	0	0	2
T39	0	0	0	2
T40	0	0	0	2
T51	0	0	0	2
T52	0	0	0	2
T75	0	0	0	2
T76	0	0	0	2
T77	0	0	0	2
T78	0	0	0	2

gen_edn_if_asserts[3].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230342208	3670	0	94
T1	2524	9	0	1
T2	783	0	0	0
T3	5582	0	0	0
T4	1233	0	0	0
T5	711	0	0	0
T9	4617	0	0	0
T10	3671	0	0	0
T13	0	3	0	1
T22	3362	0	0	0
T23	1325	0	0	0
T24	1743	0	0	0
T41	0	31	0	1
T43	0	17	0	1
T44	0	3	0	1
T45	0	3	0	1
T46	0	6	0	1
T48	0	24	0	1
T83	0	3	0	1
T84	0	22	0	1

gen_edn_if_asserts[3].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230342208	230173598	0	0
T1	2524	2443	0	0
T2	783	612	0	0
T3	5582	5493	0	0
T4	1233	1118	0	0
T5	711	555	0	0
T9	4617	4517	0	0
T10	3671	3579	0	0
T22	3362	3298	0	0
T23	1325	1274	0	0
T24	1743	1664	0	0

gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230342208	149462	0	0
T2	783	362	0	0
T3	5582	0	0	0
T4	1233	656	0	0
T5	711	226	0	0
T6	0	381	0	0
T7	0	1092	0	0
T8	0	352	0	0
T9	4617	0	0	0
T10	3671	0	0	0
T14	0	1124	0	0
T22	3362	0	0	0
T23	1325	0	0	0
T24	1743	0	0	0
T38	654435	0	0	0
T61	0	1072	0	0
T81	0	1113	0	0
T82	0	212	0	0

gen_edn_if_asserts[4].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230342208	553559	0	324
T1	2524	32	0	0
T2	783	333	0	0
T3	5582	40	0	0
T4	1233	628	0	0
T5	711	153	0	0
T9	4617	81	0	0
T10	3671	205	0	0
T22	3362	23	0	0
T23	1325	124	0	0
T24	1743	1662	0	2
T38	0	0	0	2
T39	0	0	0	2
T40	0	0	0	2
T51	0	0	0	2
T52	0	0	0	2
T75	0	0	0	2
T76	0	0	0	2
T77	0	0	0	2
T78	0	0	0	2

gen_edn_if_asserts[4].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230342208	2790	0	104
T1	2524	57	0	1
T2	783	0	0	0
T3	5582	0	0	0
T4	1233	0	0	0
T5	711	0	0	0
T9	4617	3	0	1
T10	3671	0	0	0
T14	0	1	0	0
T22	3362	0	0	0
T23	1325	0	0	0
T24	1743	0	0	0
T29	0	4	0	1
T30	0	4	0	1
T42	0	48	0	1
T43	0	3	0	1
T45	0	34	0	1
T46	0	3	0	1
T83	0	3	0	1
T84	0	0	0	1

gen_edn_if_asserts[4].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230342208	230173598	0	0
T1	2524	2443	0	0
T2	783	612	0	0
T3	5582	5493	0	0
T4	1233	1118	0	0
T5	711	555	0	0
T9	4617	4517	0	0
T10	3671	3579	0	0
T22	3362	3298	0	0
T23	1325	1274	0	0
T24	1743	1664	0	0

gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230342208	149462	0	0
T2	783	362	0	0
T3	5582	0	0	0
T4	1233	656	0	0
T5	711	226	0	0
T6	0	381	0	0
T7	0	1092	0	0
T8	0	352	0	0
T9	4617	0	0	0
T10	3671	0	0	0
T14	0	1124	0	0
T22	3362	0	0	0
T23	1325	0	0	0
T24	1743	0	0	0
T38	654435	0	0	0
T61	0	1072	0	0
T81	0	1113	0	0
T82	0	212	0	0

gen_edn_if_asserts[5].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230342208	553559	0	324
T1	2524	32	0	0
T2	783	333	0	0
T3	5582	40	0	0
T4	1233	628	0	0
T5	711	153	0	0
T9	4617	81	0	0
T10	3671	205	0	0
T22	3362	23	0	0
T23	1325	124	0	0
T24	1743	1662	0	2
T38	0	0	0	2
T39	0	0	0	2
T40	0	0	0	2
T51	0	0	0	2
T52	0	0	0	2
T75	0	0	0	2
T76	0	0	0	2
T77	0	0	0	2
T78	0	0	0	2

gen_edn_if_asserts[5].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230342208	4479	0	93
T4	1233	0	0	0
T5	711	0	0	0
T9	4617	592	0	1
T10	3671	0	0	0
T11	0	3	0	1
T13	0	38	0	1
T23	1325	0	0	0
T24	1743	0	0	0
T38	654435	0	0	0
T39	479063	0	0	0
T41	0	23	0	1
T43	0	52	0	1
T51	1862	0	0	0
T79	1756	0	0	0
T83	0	42	0	1
T84	0	53	0	1
T85	0	3	0	1
T86	0	15	0	1
T87	0	49	0	1

gen_edn_if_asserts[5].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230342208	230173598	0	0
T1	2524	2443	0	0
T2	783	612	0	0
T3	5582	5493	0	0
T4	1233	1118	0	0
T5	711	555	0	0
T9	4617	4517	0	0
T10	3671	3579	0	0
T22	3362	3298	0	0
T23	1325	1274	0	0
T24	1743	1664	0	0

gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230342208	149462	0	0
T2	783	362	0	0
T3	5582	0	0	0
T4	1233	656	0	0
T5	711	226	0	0
T6	0	381	0	0
T7	0	1092	0	0
T8	0	352	0	0
T9	4617	0	0	0
T10	3671	0	0	0
T14	0	1124	0	0
T22	3362	0	0	0
T23	1325	0	0	0
T24	1743	0	0	0
T38	654435	0	0	0
T61	0	1072	0	0
T81	0	1113	0	0
T82	0	212	0	0

gen_edn_if_asserts[6].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230342208	553559	0	324
T1	2524	32	0	0
T2	783	333	0	0
T3	5582	40	0	0
T4	1233	628	0	0
T5	711	153	0	0
T9	4617	81	0	0
T10	3671	205	0	0
T22	3362	23	0	0
T23	1325	124	0	0
T24	1743	1662	0	2
T38	0	0	0	2
T39	0	0	0	2
T40	0	0	0	2
T51	0	0	0	2
T52	0	0	0	2
T75	0	0	0	2
T76	0	0	0	2
T77	0	0	0	2
T78	0	0	0	2

gen_edn_if_asserts[6].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230342208	52320	0	71
T4	1233	0	0	0
T5	711	0	0	0
T9	4617	44	0	1
T10	3671	0	0	0
T11	0	33	0	1
T19	0	4	0	0
T23	1325	0	0	0
T24	1743	0	0	0
T38	654435	0	0	0
T39	479063	0	0	0
T42	0	3	0	1
T43	0	3	0	1
T48	0	32	0	1
T51	1862	0	0	0
T79	1756	0	0	0
T84	0	3	0	1
T85	0	3	0	1
T88	0	3	0	1
T89	0	3	0	1
T90	0	0	0	1

gen_edn_if_asserts[6].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230342208	230173598	0	0
T1	2524	2443	0	0
T2	783	612	0	0
T3	5582	5493	0	0
T4	1233	1118	0	0
T5	711	555	0	0
T9	4617	4517	0	0
T10	3671	3579	0	0
T22	3362	3298	0	0
T23	1325	1274	0	0
T24	1743	1664	0	0

gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230342208	149462	0	0
T2	783	362	0	0
T3	5582	0	0	0
T4	1233	656	0	0
T5	711	226	0	0
T6	0	381	0	0
T7	0	1092	0	0
T8	0	352	0	0
T9	4617	0	0	0
T10	3671	0	0	0
T14	0	1124	0	0
T22	3362	0	0	0
T23	1325	0	0	0
T24	1743	0	0	0
T38	654435	0	0	0
T61	0	1072	0	0
T81	0	1113	0	0
T82	0	212	0	0