Unified Coverage Report :: Module :: edn_main_sm

Module : edn_main_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.63	100.00	94.44		81.08	97.62	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_edn_main_sm	94.63	100.00	94.44		81.08	97.62	100.00

---

Module Instance : tb.dut.u_edn_core.u_edn_main_sm

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.63	100.00	94.44		81.08	97.62	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.65	100.00	94.44		81.08	97.73	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.60	100.00	90.39			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
TOTAL		106	106	100.00
ALWAYS	41	3	3	100.00
CONT_ASSIGN	43	1	1	100.00
ALWAYS	46	102	102	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
41	3	3
43	1	1
46	1	1
47	1	1
48	1	1
49	1	1
50	1	1
51	1	1
52	1	1
53	1	1
54	1	1
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
65	1	1
66	1	1
67	1	1
68	1	1
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
76	1	1
77	1	1
80	1	1
81	1	1
			MISSING_ELSE
85	1	1
86	1	1
89	1	1
90	1	1
			MISSING_ELSE
94	1	1
97	1	1
98	1	1
			MISSING_ELSE
102	1	1
103	1	1
106	1	1
107	1	1
108	1	1
			MISSING_ELSE
113	1	1
114	1	1
115	1	1
			MISSING_ELSE
119	1	1
120	1	1
121	1	1
			MISSING_ELSE
125	1	1
126	1	1
127	1	1
			MISSING_ELSE
131	1	1
132	1	1
133	1	1
134	1	1
136	1	1
137	1	1
139	1	1
144	1	1
145	1	1
146	1	1
149	1	1
150	1	1
151	1	1
152	1	1
			MISSING_ELSE
156	1	1
157	1	1
158	1	1
161	1	1
162	1	1
163	1	1
164	1	1
			MISSING_ELSE
168	1	1
171	1	1
174	1	1
182	1	1
184	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
221	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_main_sm

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       62
 EXPRESSION (boot_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T22
1	0	Covered	T2,T4,T61
1	1	Covered	T2,T3,T4

 LINE       64
 EXPRESSION (auto_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T22
1	0	Covered	T6,T7,T28
1	1	Covered	T9,T10,T13

 LINE       182
 EXPRESSION (local_escalate_i || csrng_ack_err_i)
             --------1-------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T28,T29,T30
1	0	Covered	T2,T4,T5

 LINE       184
 EXPRESSION (local_escalate_i ? Error : ((state_q == Error) ? Error : RejectCsrngEntropy))
             --------1-------

-1-	Status	Tests
0	Covered	T28,T29,T30
1	Covered	T2,T4,T5

 LINE       184
 SUB-EXPRESSION ((state_q == Error) ? Error : RejectCsrngEntropy)
                 ---------1--------

-1-	Status	Tests
0	Covered	T28,T29,T30
1	Not Covered

 LINE       184
 SUB-EXPRESSION (state_q == Error)
                ---------1--------

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T2,T4,T5

 LINE       198
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_i)) && 
      2  (state_q inside {BootLoadIns, BootInsAckWait, BootLoadGen, BootGenAckWait, BootLoadUni, BootUniAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode, RejectCsrngEntropy}))

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T6

---

FSM Coverage for Module : edn_main_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	20	20	100.00	(Not included in score)
Transitions	74	60	81.08
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AutoAckWait	152	Covered	T9,T10,T13
AutoCaptGenCnt	139	Covered	T9,T10,T13
AutoCaptReseedCnt	137	Covered	T9,T10,T13
AutoDispatch	121	Covered	T9,T10,T13
AutoFirstAckWait	115	Covered	T9,T10,T13
AutoLoadIns	67	Covered	T9,T10,T13
AutoSendGenCmd	146	Covered	T9,T10,T13
AutoSendReseedCmd	158	Covered	T9,T10,T13
BootDone	94	Covered	T2,T3,T4
BootGenAckWait	86	Covered	T2,T3,T4
BootInsAckWait	77	Covered	T2,T3,T4
BootLoadGen	81	Covered	T2,T3,T4
BootLoadIns	63	Covered	T2,T3,T4
BootLoadUni	98	Covered	T3,T4,T79
BootPulse	90	Covered	T2,T3,T4
BootUniAckWait	103	Covered	T3,T4,T79
Error	184	Covered	T2,T4,T5
Idle	108	Covered	T1,T2,T3
RejectCsrngEntropy	184	Covered	T28,T29,T30
SWPortMode	72	Covered	T1,T3,T22

transitions	Line No.	Covered	Tests
AutoAckWait->AutoDispatch	127	Covered	T9,T10,T13
AutoAckWait->Error	184	Covered	T91,T92,T93
AutoAckWait->Idle	208	Covered	T75,T77,T19
AutoAckWait->RejectCsrngEntropy	184	Covered	T30,T94,T50
AutoCaptGenCnt->AutoSendGenCmd	146	Covered	T9,T10,T13
AutoCaptGenCnt->Error	184	Covered	T95,T96
AutoCaptGenCnt->Idle	208	Covered	T97,T98,T99
AutoCaptGenCnt->RejectCsrngEntropy	184	Not Covered
AutoCaptReseedCnt->AutoSendReseedCmd	158	Covered	T9,T10,T13
AutoCaptReseedCnt->Error	184	Covered	T6,T8,T100
AutoCaptReseedCnt->Idle	208	Covered	T19,T101,T102
AutoCaptReseedCnt->RejectCsrngEntropy	184	Not Covered
AutoDispatch->AutoCaptGenCnt	139	Covered	T9,T10,T13
AutoDispatch->AutoCaptReseedCnt	137	Covered	T9,T10,T13
AutoDispatch->Error	184	Covered	T103,T104
AutoDispatch->Idle	134	Covered	T9,T10,T13
AutoDispatch->RejectCsrngEntropy	184	Not Covered
AutoFirstAckWait->AutoDispatch	121	Covered	T9,T10,T13
AutoFirstAckWait->Error	184	Covered	T105,T106
AutoFirstAckWait->Idle	208	Covered	T75,T107,T108
AutoFirstAckWait->RejectCsrngEntropy	184	Not Covered
AutoLoadIns->AutoFirstAckWait	115	Covered	T9,T10,T13
AutoLoadIns->Error	184	Covered	T56,T109,T110
AutoLoadIns->Idle	208	Covered	T6,T7,T8
AutoLoadIns->RejectCsrngEntropy	184	Not Covered
AutoSendGenCmd->AutoAckWait	152	Covered	T9,T10,T13
AutoSendGenCmd->Error	184	Covered	T111
AutoSendGenCmd->Idle	208	Covered	T20,T112,T113
AutoSendGenCmd->RejectCsrngEntropy	184	Not Covered
AutoSendReseedCmd->AutoAckWait	164	Covered	T9,T10,T13
AutoSendReseedCmd->Error	184	Covered	T114
AutoSendReseedCmd->Idle	208	Covered	T115,T116,T117
AutoSendReseedCmd->RejectCsrngEntropy	184	Not Covered
BootDone->BootLoadUni	98	Covered	T3,T4,T79
BootDone->Error	184	Covered	T15,T55,T118
BootDone->Idle	208	Covered	T119,T120,T121
BootDone->RejectCsrngEntropy	184	Not Covered
BootGenAckWait->BootPulse	90	Covered	T2,T3,T4
BootGenAckWait->Error	184	Covered	T54
BootGenAckWait->Idle	208	Covered	T54,T122,T123
BootGenAckWait->RejectCsrngEntropy	184	Covered	T73,T124,T125
BootInsAckWait->BootLoadGen	81	Covered	T2,T3,T4
BootInsAckWait->Error	184	Covered	T126,T127,T128
BootInsAckWait->Idle	208	Covered	T2,T4,T61
BootInsAckWait->RejectCsrngEntropy	184	Covered	T28,T29,T129
BootLoadGen->BootGenAckWait	86	Covered	T2,T3,T4
BootLoadGen->Error	184	Covered	T130,T131
BootLoadGen->Idle	208	Covered	T132,T133,T134
BootLoadGen->RejectCsrngEntropy	184	Not Covered
BootLoadIns->BootInsAckWait	77	Covered	T2,T3,T4
BootLoadIns->Error	184	Covered	T82,T135,T136
BootLoadIns->Idle	208	Covered	T137,T138
BootLoadIns->RejectCsrngEntropy	184	Not Covered
BootLoadUni->BootUniAckWait	103	Covered	T3,T4,T79
BootLoadUni->Error	184	Covered	T139,T140
BootLoadUni->Idle	208	Not Covered
BootLoadUni->RejectCsrngEntropy	184	Not Covered
BootPulse->BootDone	94	Covered	T2,T3,T4
BootPulse->Error	184	Covered	T81,T141
BootPulse->Idle	208	Covered	T68,T142,T143
BootPulse->RejectCsrngEntropy	184	Not Covered
BootUniAckWait->Error	184	Covered	T4,T144,T123
BootUniAckWait->Idle	108	Covered	T3,T79,T47
BootUniAckWait->RejectCsrngEntropy	184	Covered	T145,T146,T147
Idle->AutoLoadIns	67	Covered	T9,T10,T13
Idle->BootLoadIns	63	Covered	T2,T3,T4
Idle->Error	184	Covered	T16,T17,T18
Idle->RejectCsrngEntropy	184	Not Covered
Idle->SWPortMode	72	Covered	T1,T3,T22
RejectCsrngEntropy->Error	184	Covered	T148,T149,T150
RejectCsrngEntropy->Idle	208	Covered	T28,T29,T30
SWPortMode->Error	184	Covered	T14,T151,T152
SWPortMode->Idle	208	Covered	T38,T39,T28
SWPortMode->RejectCsrngEntropy	184	Covered	T49,T153,T148

---

Branch Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
Branches		42	41	97.62
IF	41	2	2	100.00
CASE	60	35	35	100.00
IF	182	5	4	80.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	41	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if ((boot_req_mode_i && edn_enable_i))
-3-:	64	if ((auto_req_mode_i && edn_enable_i))
-4-:	68	if (edn_enable_i)
-5-:	80	if (csrng_cmd_ack_i)
-6-:	89	if (csrng_cmd_ack_i)
-7-:	97	if ((!boot_req_mode_i))
-8-:	106	if (csrng_cmd_ack_i)
-9-:	114	if (sw_cmd_req_load_i)
-10-:	120	if (csrng_cmd_ack_i)
-11-:	126	if (csrng_cmd_ack_i)
-12-:	132	if ((!auto_req_mode_i))
-13-:	136	if (max_reqs_cnt_zero_i)
-14-:	151	if (cmd_sent_i)
-15-:	163	if (cmd_sent_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	Status	Tests
Idle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T4
Idle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T13
Idle	0	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T22
Idle	0	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
BootLoadIns	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T4
BootInsAckWait	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T4
BootInsAckWait	-	-	-	0	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T4
BootLoadGen	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T4
BootGenAckWait	-	-	-	-	1	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T4
BootGenAckWait	-	-	-	-	0	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T4
BootPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T4
BootDone	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T3,T4,T79
BootDone	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T2,T4,T61
BootLoadUni	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T79
BootUniAckWait	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T3,T79,T47
BootUniAckWait	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T3,T4,T79
AutoLoadIns	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T9,T10,T13
AutoLoadIns	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T9,T10,T13
AutoFirstAckWait	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T9,T10,T13
AutoFirstAckWait	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T9,T10,T13
AutoAckWait	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T9,T10,T13
AutoAckWait	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T9,T10,T13
AutoDispatch	-	-	-	-	-	-	-	-	-	-	1	-	-	-	Covered	T9,T10,T13
AutoDispatch	-	-	-	-	-	-	-	-	-	-	0	1	-	-	Covered	T9,T10,T13
AutoDispatch	-	-	-	-	-	-	-	-	-	-	0	0	-	-	Covered	T9,T10,T13
AutoCaptGenCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T13
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T9,T10,T13
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T9,T10,T13
AutoCaptReseedCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T13
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T9,T10,T13
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T9,T10,T13
SWPortMode	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T22
RejectCsrngEntropy	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T28,T29,T30
Error	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T5
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T5,T7

	LineNo.	Expression
-1-:	182	if ((local_escalate_i || csrng_ack_err_i))
-2-:	184	(local_escalate_i) ? 
-3-:	184	((state_q == Error)) ? 
-4-:	198	if (((!edn_enable_i) && (state_q inside {BootLoadIns, BootInsAckWait, BootLoadGen, BootGenAckWait, BootLoadUni, BootUniAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode, RejectCsrngEntropy})))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	1	-	-	Covered	T2,T4,T5
1	0	1	-	Not Covered
1	0	0	-	Covered	T28,T29,T30
0	-	-	1	Covered	T2,T4,T6
0	-	-	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_main_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ErrorStStable_A	230342208	145055	0	0
FpvSecCmErrorStEscalate_A	230342208	146096	0	0
u_state_regs_A	230303142	230134532	0	0

ErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230342208	145055	0	0
T2	783	310	0	0
T3	5582	0	0	0
T4	1233	654	0	0
T5	711	174	0	0
T6	0	379	0	0
T7	0	1040	0	0
T8	0	350	0	0
T9	4617	0	0	0
T10	3671	0	0	0
T14	0	1122	0	0
T22	3362	0	0	0
T23	1325	0	0	0
T24	1743	0	0	0
T38	654435	0	0	0
T61	0	1020	0	0
T81	0	1111	0	0
T82	0	210	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230342208	146096	0	0
T2	783	311	0	0
T3	5582	0	0	0
T4	1233	655	0	0
T5	711	175	0	0
T6	0	380	0	0
T7	0	1041	0	0
T8	0	351	0	0
T9	4617	0	0	0
T10	3671	0	0	0
T14	0	1123	0	0
T22	3362	0	0	0
T23	1325	0	0	0
T24	1743	0	0	0
T38	654435	0	0	0
T61	0	1021	0	0
T81	0	1112	0	0
T82	0	211	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230303142	230134532	0	0
T1	2524	2443	0	0
T2	627	456	0	0
T3	5582	5493	0	0
T4	977	862	0	0
T5	573	417	0	0
T9	4617	4517	0	0
T10	3671	3579	0	0
T22	3362	3298	0	0
T23	1325	1274	0	0
T24	1743	1664	0	0