Module Definition
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Module : edn_core
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.60 100.00 90.39 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_core.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_edn_core 97.60 100.00 90.39 100.00 100.00



Module Instance : tb.dut.u_edn_core

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.60 100.00 90.39 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.09 99.92 92.46 82.54 85.47 99.28 98.88


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.44 83.33 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_ep_blk[0].u_edn_ack_sm_ep 97.14 100.00 100.00 85.71 100.00 100.00
gen_ep_blk[0].u_prim_packer_fifo_ep 98.81 100.00 95.24 100.00 100.00
gen_ep_blk[1].u_edn_ack_sm_ep 98.57 100.00 100.00 92.86 100.00 100.00
gen_ep_blk[1].u_prim_packer_fifo_ep 98.81 100.00 95.24 100.00 100.00
gen_ep_blk[2].u_edn_ack_sm_ep 97.14 100.00 100.00 85.71 100.00 100.00
gen_ep_blk[2].u_prim_packer_fifo_ep 98.81 100.00 95.24 100.00 100.00
gen_ep_blk[3].u_edn_ack_sm_ep 97.14 100.00 100.00 85.71 100.00 100.00
gen_ep_blk[3].u_prim_packer_fifo_ep 98.81 100.00 95.24 100.00 100.00
gen_ep_blk[4].u_edn_ack_sm_ep 97.14 100.00 100.00 85.71 100.00 100.00
gen_ep_blk[4].u_prim_packer_fifo_ep 98.81 100.00 95.24 100.00 100.00
gen_ep_blk[5].u_edn_ack_sm_ep 98.57 100.00 100.00 92.86 100.00 100.00
gen_ep_blk[5].u_prim_packer_fifo_ep 98.81 100.00 95.24 100.00 100.00
gen_ep_blk[6].u_edn_ack_sm_ep 98.57 100.00 100.00 92.86 100.00 100.00
gen_ep_blk[6].u_prim_packer_fifo_ep 98.81 100.00 95.24 100.00 100.00
u_edn_main_sm 94.65 100.00 94.44 81.08 97.73 100.00
u_intr_hw_edn_cmd_req_done 100.00 100.00 100.00 100.00 100.00
u_intr_hw_edn_fatal_err 100.00 100.00 100.00 100.00 100.00
u_prim_arbiter_ppc_packer_arb 95.16 95.00 92.31 100.00 93.33
u_prim_count_max_reqs_cntr 70.79 70.79
u_prim_edge_detector_recov_alert 100.00 100.00 100.00 100.00
u_prim_fifo_sync_gencmd 98.38 100.00 91.89 100.00 100.00 100.00
u_prim_fifo_sync_rescmd 98.38 100.00 91.89 100.00 100.00 100.00
u_prim_mubi4_sync_auto_req_mode 100.00 100.00 100.00
u_prim_mubi4_sync_boot_req_mode 100.00 100.00 100.00
u_prim_mubi4_sync_cmd_fifo_rst 100.00 100.00 100.00
u_prim_mubi4_sync_edn_enable 100.00 100.00 100.00
u_prim_packer_fifo_cs 95.24 100.00 95.24 85.71 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : edn_core
Line No.TotalCoveredPercent
TOTAL253253100.00
ALWAYS2173636100.00
CONT_ASSIGN29211100.00
CONT_ASSIGN29711100.00
CONT_ASSIGN30411100.00
CONT_ASSIGN31011100.00
CONT_ASSIGN31211100.00
CONT_ASSIGN31411100.00
CONT_ASSIGN31611100.00
CONT_ASSIGN31811100.00
CONT_ASSIGN32111100.00
CONT_ASSIGN32511100.00
CONT_ASSIGN32911100.00
CONT_ASSIGN33711100.00
CONT_ASSIGN34011100.00
CONT_ASSIGN34311100.00
CONT_ASSIGN34611100.00
CONT_ASSIGN34911100.00
CONT_ASSIGN35111100.00
CONT_ASSIGN35211100.00
CONT_ASSIGN35711100.00
CONT_ASSIGN36011100.00
CONT_ASSIGN36311100.00
CONT_ASSIGN36811100.00
CONT_ASSIGN36811100.00
CONT_ASSIGN36811100.00
CONT_ASSIGN36811100.00
CONT_ASSIGN36811100.00
CONT_ASSIGN36811100.00
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CONT_ASSIGN36811100.00
CONT_ASSIGN36811100.00
CONT_ASSIGN36811100.00
CONT_ASSIGN36811100.00
CONT_ASSIGN36811100.00
CONT_ASSIGN36811100.00
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CONT_ASSIGN36811100.00
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CONT_ASSIGN36811100.00
CONT_ASSIGN36811100.00
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CONT_ASSIGN36811100.00
CONT_ASSIGN36811100.00
CONT_ASSIGN36811100.00
CONT_ASSIGN36811100.00
CONT_ASSIGN36811100.00
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CONT_ASSIGN36811100.00
CONT_ASSIGN37211100.00
CONT_ASSIGN37411100.00
CONT_ASSIGN37511100.00
CONT_ASSIGN37811100.00
CONT_ASSIGN39711100.00
CONT_ASSIGN40011100.00
CONT_ASSIGN40411100.00
CONT_ASSIGN41311100.00
CONT_ASSIGN41411100.00
CONT_ASSIGN41511100.00
CONT_ASSIGN41611100.00
CONT_ASSIGN41911100.00
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CONT_ASSIGN41911100.00
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CONT_ASSIGN41911100.00
CONT_ASSIGN41911100.00
CONT_ASSIGN41911100.00
CONT_ASSIGN41911100.00
CONT_ASSIGN41911100.00
CONT_ASSIGN41911100.00
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CONT_ASSIGN41911100.00
CONT_ASSIGN41911100.00
CONT_ASSIGN41911100.00
CONT_ASSIGN41911100.00
CONT_ASSIGN41911100.00
CONT_ASSIGN41911100.00
CONT_ASSIGN41911100.00
CONT_ASSIGN41911100.00
CONT_ASSIGN43411100.00
CONT_ASSIGN43511100.00
CONT_ASSIGN43611100.00
CONT_ASSIGN43711100.00
CONT_ASSIGN44011100.00
CONT_ASSIGN44011100.00
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CONT_ASSIGN45411100.00
CONT_ASSIGN46111100.00
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CONT_ASSIGN46411100.00
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CONT_ASSIGN55211100.00
CONT_ASSIGN56211100.00
CONT_ASSIGN56311100.00
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CONT_ASSIGN57411100.00
CONT_ASSIGN58111100.00
CONT_ASSIGN58211100.00
CONT_ASSIGN59311100.00
CONT_ASSIGN59411100.00
CONT_ASSIGN59911100.00
CONT_ASSIGN60011100.00
CONT_ASSIGN60611100.00
CONT_ASSIGN60711100.00
CONT_ASSIGN61711100.00
CONT_ASSIGN61811100.00
CONT_ASSIGN62711100.00
CONT_ASSIGN62811100.00
CONT_ASSIGN65511100.00
CONT_ASSIGN65711100.00
CONT_ASSIGN66111100.00
CONT_ASSIGN66511100.00
CONT_ASSIGN66711100.00
CONT_ASSIGN66911100.00
CONT_ASSIGN69811100.00
CONT_ASSIGN70011100.00
CONT_ASSIGN70411100.00
CONT_ASSIGN70811100.00
CONT_ASSIGN71011100.00
CONT_ASSIGN71211100.00
CONT_ASSIGN77111100.00
CONT_ASSIGN77511100.00
CONT_ASSIGN77811100.00
CONT_ASSIGN78811100.00
CONT_ASSIGN79311100.00
CONT_ASSIGN79411100.00
CONT_ASSIGN79511100.00
CONT_ASSIGN79611100.00
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CONT_ASSIGN83511100.00
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CONT_ASSIGN85911100.00
CONT_ASSIGN86011100.00
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CONT_ASSIGN86411100.00
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CONT_ASSIGN88311100.00
CONT_ASSIGN88511100.00
CONT_ASSIGN88711100.00
CONT_ASSIGN89311100.00
CONT_ASSIGN89611100.00
CONT_ASSIGN89711100.00
CONT_ASSIGN92111100.00
CONT_ASSIGN92111100.00
CONT_ASSIGN92111100.00
CONT_ASSIGN92111100.00
CONT_ASSIGN92111100.00
CONT_ASSIGN92111100.00
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CONT_ASSIGN92211100.00
CONT_ASSIGN92211100.00
CONT_ASSIGN92211100.00
CONT_ASSIGN92211100.00
CONT_ASSIGN92211100.00
CONT_ASSIGN92211100.00
CONT_ASSIGN92211100.00
CONT_ASSIGN92511100.00
CONT_ASSIGN92511100.00
CONT_ASSIGN92511100.00
CONT_ASSIGN92511100.00
CONT_ASSIGN92511100.00
CONT_ASSIGN92511100.00
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CONT_ASSIGN93111100.00
CONT_ASSIGN93111100.00
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CONT_ASSIGN93211100.00
CONT_ASSIGN93211100.00
CONT_ASSIGN93211100.00
CONT_ASSIGN93211100.00
CONT_ASSIGN93211100.00
CONT_ASSIGN93211100.00
CONT_ASSIGN93211100.00
CONT_ASSIGN95211100.00
CONT_ASSIGN96811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_core.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_core.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
217 1 1
218 1 1
219 1 1
220 1 1
221 1 1
222 1 1
223 1 1
224 1 1
225 1 1
226 1 1
227 1 1
228 1 1
229 1 1
230 1 1
231 1 1
232 1 1
233 1 1
234 1 1
236 1 1
237 1 1
238 1 1
239 1 1
240 1 1
241 1 1
242 1 1
243 1 1
244 1 1
245 1 1
246 1 1
247 1 1
248 1 1
249 1 1
250 1 1
251 1 1
252 1 1
253 1 1
292 1 1
297 1 1
304 1 1
310 1 1
312 1 1
314 1 1
316 1 1
318 1 1
321 1 1
325 1 1
329 1 1
337 1 1
340 1 1
343 1 1
346 1 1
349 1 1
351 1 1
352 1 1
357 1 1
360 1 1
363 1 1
368 31 31
372 1 1
374 1 1
375 1 1
378 1 1
397 1 1
400 1 1
404 1 1
413 1 1
414 1 1
415 1 1
416 1 1
419 19 19
434 1 1
435 1 1
436 1 1
437 1 1
440 3 3
454 1 1
461 1 1
462 1 1
463 1 1
464 1 1
465 1 1
480 1 1
481 1 1
483 1 1
484 1 1
486 1 1
487 1 1
489 1 1
490 1 1
492 1 1
493 1 1
494 1 1
497 1 1
506 1 1
513 1 1
517 1 1
533 1 1
541 1 1
542 1 1
547 1 1
548 1 1
552 1 1
562 1 1
563 1 1
573 1 1
574 1 1
581 1 1
582 1 1
593 1 1
594 1 1
599 1 1
600 1 1
606 1 1
607 1 1
617 1 1
618 1 1
627 1 1
628 1 1
655 1 1
657 1 1
661 1 1
665 1 1
667 1 1
669 1 1
698 1 1
700 1 1
704 1 1
708 1 1
710 1 1
712 1 1
771 1 1
775 1 1
778 1 1
788 1 1
793 1 1
794 1 1
795 1 1
796 1 1
799 1 1
835 7 7
859 1 1
860 1 1
863 1 1
864 1 1
865 1 1
866 1 1
868 1 1
883 1 1
885 1 1
887 1 1
893 1 1
896 1 1
897 1 1
921 7 7
922 7 7
925 7 7
928 7 7
931 7 7
932 7 7
952 1 1
968 1 1


Cond Coverage for Module : edn_core
TotalCoveredPercent
Conditions63557490.39
Logical63557490.39
Non-Logical00
Event00

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.
Line numbersPercent
292-71091.78
712-96887.03

Branch Coverage for Module : edn_core
Line No.TotalCoveredPercent
Branches 104 104 100.00
TERNARY 497 6 6 100.00
TERNARY 506 4 4 100.00
TERNARY 517 7 7 100.00
TERNARY 533 5 5 100.00
TERNARY 552 6 6 100.00
TERNARY 563 6 6 100.00
TERNARY 574 3 3 100.00
TERNARY 582 4 4 100.00
TERNARY 594 3 3 100.00
TERNARY 600 3 3 100.00
TERNARY 607 5 5 100.00
TERNARY 618 5 5 100.00
TERNARY 628 2 2 100.00
TERNARY 657 2 2 100.00
TERNARY 661 2 2 100.00
TERNARY 700 2 2 100.00
TERNARY 704 2 2 100.00
TERNARY 778 6 6 100.00
TERNARY 868 3 3 100.00
TERNARY 885 2 2 100.00
TERNARY 887 3 3 100.00
TERNARY 925 3 3 100.00
TERNARY 925 3 3 100.00
TERNARY 925 3 3 100.00
TERNARY 925 3 3 100.00
TERNARY 925 3 3 100.00
TERNARY 925 3 3 100.00
TERNARY 925 3 3 100.00
IF 217 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_core.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_core.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 497 ((!edn_enable_fo[CsrngCmdReq])) ? -2-: 497 (boot_wr_ins_cmd) ? -3-: 497 (boot_wr_gen_cmd) ? -4-: 497 (boot_wr_uni_cmd) ? -5-: 497 (sw_cmd_req_load) ?

Branches:
-1--2--3--4--5-StatusTests
1 - - - - Covered T1,T2,T3
0 1 - - - Covered T2,T3,T4
0 0 1 - - Covered T2,T3,T4
0 0 0 1 - Covered T3,T4,T79
0 0 0 0 1 Covered T1,T3,T22
0 0 0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 506 ((!edn_enable_fo[CsrngCmdReqValid])) ? -2-: 506 (cs_cmd_handshake) ? -3-: 506 ((((sw_cmd_req_load || boot_wr_ins_cmd) || boot_wr_gen_cmd) || boot_wr_uni_cmd)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 517 ((!edn_enable_fo[CsrngCmdReqOut])) ? -2-: 517 ((send_rescmd || capt_rescmd_fifo_cnt)) ? -3-: 517 (sfifo_rescmd_pop) ? -4-: 517 ((send_gencmd || capt_gencmd_fifo_cnt)) ? -5-: 517 (sfifo_gencmd_pop) ? -6-: 517 ((cs_cmd_req_vld_q && (!cs_cmd_handshake))) ?

Branches:
-1--2--3--4--5--6-StatusTests
1 - - - - - Covered T1,T2,T3
0 1 1 - - - Covered T9,T10,T13
0 1 0 - - - Covered T9,T10,T13
0 0 - 1 1 - Covered T9,T10,T13
0 0 - 1 0 - Covered T9,T10,T13
0 0 - 0 - 1 Covered T1,T2,T3
0 0 - 0 - 0 Covered T1,T2,T3


LineNo. Expression -1-: 533 ((!edn_enable_fo[CsrngCmdReqValidOut])) ? -2-: 533 (cmd_sent) ? -3-: 533 ((send_rescmd || capt_rescmd_fifo_cnt)) ? -4-: 533 ((send_gencmd || capt_gencmd_fifo_cnt)) ?

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Covered T9,T10,T13
0 0 1 - Covered T9,T10,T13
0 0 0 1 Covered T9,T10,T13
0 0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 552 ((!edn_enable_fo[SwCmdSts])) ? -2-: 552 ((!sw_cmd_valid)) ? -3-: 552 (sw_cmd_req_load) ? -4-: 552 (accept_sw_cmds_pulse) ? -5-: 552 (csrng_cmd_i.csrng_rsp_ack) ?

Branches:
-1--2--3--4--5-StatusTests
1 - - - - Covered T1,T2,T3
0 1 - - - Covered T2,T3,T9
0 0 1 - - Covered T1,T3,T22
0 0 0 1 - Covered T1,T3,T22
0 0 0 0 1 Covered T1,T3,T22
0 0 0 0 0 Covered T1,T3,T22


LineNo. Expression -1-: 563 ((!edn_enable_fo[SwCmdSts])) ? -2-: 563 ((!sw_cmd_valid)) ? -3-: 563 (sw_cmd_req_load) ? -4-: 563 (accept_sw_cmds_pulse) ? -5-: 563 (cs_cmd_handshake) ?

Branches:
-1--2--3--4--5-StatusTests
1 - - - - Covered T1,T2,T3
0 1 - - - Covered T2,T3,T9
0 0 1 - - Covered T1,T3,T22
0 0 0 1 - Covered T1,T3,T22
0 0 0 0 1 Covered T1,T3,T22
0 0 0 0 0 Covered T1,T3,T22


LineNo. Expression -1-: 574 ((!edn_enable_fo[SwCmdSts])) ? -2-: 574 ((csrng_cmd_i.csrng_rsp_ack && sw_cmd_valid)) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T3,T22
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 582 ((!edn_enable_fo[SwCmdSts])) ? -2-: 582 (sw_cmd_req_load) ? -3-: 582 ((csrng_cmd_i.csrng_rsp_ack && sw_cmd_valid)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T3,T22
0 0 1 Covered T1,T3,T22
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 594 ((main_sm_done_pulse || (!edn_enable_fo[HwCmdSts]))) ? -2-: 594 (boot_wr_ins_cmd) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T2,T3,T4
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 600 ((main_sm_done_pulse || (!edn_enable_fo[HwCmdSts]))) ? -2-: 600 (auto_req_mode_busy) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T9,T10,T13
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 607 ((!edn_enable_fo[HwCmdSts])) ? -2-: 607 (sw_cmd_valid) ? -3-: 607 ((cs_cmd_req_vld_out_q && csrng_cmd_i.csrng_req_ready)) ? -4-: 607 ((csrng_cmd_i.csrng_rsp_ack && (csrng_cmd_i.csrng_rsp_sts != CMD_STS_SUCCESS))) ?

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Covered T1,T3,T22
0 0 1 - Covered T2,T3,T9
0 0 0 1 Covered T28,T29,T30
0 0 0 0 Covered T2,T3,T9


LineNo. Expression -1-: 618 ((!edn_enable_fo[HwCmdSts])) ? -2-: 618 (sw_cmd_valid) ? -3-: 618 ((cs_cmd_req_vld_out_q && csrng_cmd_i.csrng_req_ready)) ? -4-: 618 (csrng_cmd_i.csrng_rsp_ack) ?

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Covered T1,T3,T22
0 0 1 - Covered T2,T3,T9
0 0 0 1 Covered T2,T3,T9
0 0 0 0 Covered T2,T3,T9


LineNo. Expression -1-: 628 ((((edn_enable_fo[HwCmdSts] && (!sw_cmd_valid)) && cs_cmd_req_vld_out_q) && csrng_cmd_i.csrng_req_ready)) ?

Branches:
-1-StatusTests
1 Covered T2,T3,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 657 (rescmd_handshake) ?

Branches:
-1-StatusTests
1 Covered T9,T10,T13
0 Covered T1,T2,T3


LineNo. Expression -1-: 661 (auto_req_mode_busy) ?

Branches:
-1-StatusTests
1 Covered T9,T10,T13
0 Covered T1,T2,T3


LineNo. Expression -1-: 700 (gencmd_handshake) ?

Branches:
-1-StatusTests
1 Covered T9,T10,T13
0 Covered T1,T2,T3


LineNo. Expression -1-: 704 (auto_req_mode_busy) ?

Branches:
-1-StatusTests
1 Covered T9,T10,T13
0 Covered T1,T2,T3


LineNo. Expression -1-: 778 ((!edn_enable_fo[CmdFifoCnt])) ? -2-: 778 ((cmd_fifo_rst_fo[3] || main_sm_done_pulse)) ? -3-: 778 (capt_gencmd_fifo_cnt) ? -4-: 778 (capt_rescmd_fifo_cnt) ? -5-: 778 ((sfifo_gencmd_pop || sfifo_rescmd_pop)) ?

Branches:
-1--2--3--4--5-StatusTests
1 - - - - Covered T1,T2,T3
0 1 - - - Covered T1,T3,T22
0 0 1 - - Covered T9,T10,T13
0 0 0 1 - Covered T9,T10,T13
0 0 0 0 1 Covered T9,T10,T13
0 0 0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 868 ((!edn_enable_fo[CsrngFipsEn])) ? -2-: 868 ((packer_cs_push && packer_cs_wready)) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T3,T22
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 885 (cs_rdata_capt_vld) ?

Branches:
-1-StatusTests
1 Covered T1,T3,T22
0 Covered T1,T2,T3


LineNo. Expression -1-: 887 ((!edn_enable_fo[CsrngDataVld])) ? -2-: 887 (cs_rdata_capt_vld) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T3,T22
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 925 (packer_ep_clr[0]) ? -2-: 925 ((packer_ep_push[0] && packer_ep_wready[0])) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T3,T22,T23
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 925 (packer_ep_clr[1]) ? -2-: 925 ((packer_ep_push[1] && packer_ep_wready[1])) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T23,T5,T13
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 925 (packer_ep_clr[2]) ? -2-: 925 ((packer_ep_push[2] && packer_ep_wready[2])) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T41,T28
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 925 (packer_ep_clr[3]) ? -2-: 925 ((packer_ep_push[3] && packer_ep_wready[3])) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T13,T41
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 925 (packer_ep_clr[4]) ? -2-: 925 ((packer_ep_push[4] && packer_ep_wready[4])) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T9,T14
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 925 (packer_ep_clr[5]) ? -2-: 925 ((packer_ep_push[5] && packer_ep_wready[5])) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T9,T13,T41
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 925 (packer_ep_clr[6]) ? -2-: 925 ((packer_ep_push[6] && packer_ep_wready[6])) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T9,T42,T43
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 217 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Module : edn_core
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CsErrAcceptNoEntropy_A 230342208 7015 0 0
CsErrIssueNoCommands_A 230342208 7015 0 0


CsErrAcceptNoEntropy_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 230342208 7015 0 0
T21 2197 0 0 0
T28 1866 117 0 0
T29 0 148 0 0
T30 0 136 0 0
T40 186533 0 0 0
T46 1593 0 0 0
T50 0 117 0 0
T53 20871 0 0 0
T60 3761 0 0 0
T61 2802 0 0 0
T62 931 0 0 0
T63 2712 0 0 0
T73 0 156 0 0
T75 3191 0 0 0
T94 0 151 0 0
T145 0 162 0 0
T146 0 129 0 0
T166 0 147 0 0
T171 0 117 0 0

CsErrIssueNoCommands_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 230342208 7015 0 0
T21 2197 0 0 0
T28 1866 117 0 0
T29 0 148 0 0
T30 0 136 0 0
T40 186533 0 0 0
T46 1593 0 0 0
T50 0 117 0 0
T53 20871 0 0 0
T60 3761 0 0 0
T61 2802 0 0 0
T62 931 0 0 0
T63 2712 0 0 0
T73 0 156 0 0
T75 3191 0 0 0
T94 0 151 0 0
T145 0 162 0 0
T146 0 129 0 0
T166 0 147 0 0
T171 0 117 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%