Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_prim_fifo_sync_rescmd	94.64	100.00	78.57			100.00	100.00
tb.dut.u_edn_core.u_prim_fifo_sync_gencmd	94.64	100.00	78.57			100.00	100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.38	100.00	91.89	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.60	100.00	90.39			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.38	100.00	91.89	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.60	100.00	90.39			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Module : prim_fifo_sync

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T9,T10,T13
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T9,T4

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T32,T35,T36
1	1	0	Not Covered
1	1	1	Covered	T2,T9,T4

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T33,T34,T37
1	0	1	Covered	T2,T9,T4
1	1	0	Not Covered
1	1	1	Covered	T9,T10,T13

---

Branch Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T9,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	459979082	1001177	0	0
DepthKnown_A	460684416	460347196	0	0
RvalidKnown_A	460684416	460347196	0	0
WreadyKnown_A	460684416	460347196	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	460341764	1093565	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459979082	1001177	0	0
T4	220	0	0	0
T5	600	0	0	0
T6	0	146	0	0
T7	0	83	0	0
T8	0	61	0	0
T9	9234	5699	0	0
T10	7342	2837	0	0
T13	0	3352	0	0
T21	0	1179	0	0
T23	2650	0	0	0
T24	3486	0	0	0
T28	0	43	0	0
T38	1308870	0	0	0
T39	958126	0	0	0
T51	3724	0	0	0
T75	0	2864	0	0
T77	0	2134	0	0
T79	3512	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460684416	460347196	0	0
T1	5048	4886	0	0
T2	1566	1224	0	0
T3	11164	10986	0	0
T4	2466	2236	0	0
T5	1422	1110	0	0
T9	9234	9034	0	0
T10	7342	7158	0	0
T22	6724	6596	0	0
T23	2650	2548	0	0
T24	3486	3328	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460684416	460347196	0	0
T1	5048	4886	0	0
T2	1566	1224	0	0
T3	11164	10986	0	0
T4	2466	2236	0	0
T5	1422	1110	0	0
T9	9234	9034	0	0
T10	7342	7158	0	0
T22	6724	6596	0	0
T23	2650	2548	0	0
T24	3486	3328	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460684416	460347196	0	0
T1	5048	4886	0	0
T2	1566	1224	0	0
T3	11164	10986	0	0
T4	2466	2236	0	0
T5	1422	1110	0	0
T9	9234	9034	0	0
T10	7342	7158	0	0
T22	6724	6596	0	0
T23	2650	2548	0	0
T24	3486	3328	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	460341764	1093565	0	0
T2	1566	292	0	0
T3	11164	0	0	0
T4	2466	435	0	0
T5	1422	0	0	0
T6	0	995	0	0
T7	0	1346	0	0
T9	9234	5699	0	0
T10	7342	2837	0	0
T13	0	3352	0	0
T21	0	1179	0	0
T22	6724	0	0	0
T23	2650	0	0	0
T24	3486	0	0	0
T28	0	43	0	0
T38	1308870	0	0	0
T61	0	2218	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T154,T155
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T9,T4

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T32,T35,T156
1	1	0	Not Covered
1	1	1	Covered	T2,T9,T4

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T37,T157
1	0	1	Covered	T2,T9,T4
1	1	0	Not Covered
1	1	1	Covered	T9,T10,T13

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T9,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	229989541	495264	0	0
DepthKnown_A	230342208	230173598	0	0
RvalidKnown_A	230342208	230173598	0	0
WreadyKnown_A	230342208	230173598	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	230170882	541187	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	229989541	495264	0	0
T4	110	0	0	0
T5	300	0	0	0
T6	0	27	0	0
T7	0	41	0	0
T8	0	29	0	0
T9	4617	2844	0	0
T10	3671	1368	0	0
T13	0	1642	0	0
T21	0	534	0	0
T23	1325	0	0	0
T24	1743	0	0	0
T28	0	9	0	0
T38	654435	0	0	0
T39	479063	0	0	0
T51	1862	0	0	0
T75	0	1346	0	0
T77	0	1046	0	0
T79	1756	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230342208	230173598	0	0
T1	2524	2443	0	0
T2	783	612	0	0
T3	5582	5493	0	0
T4	1233	1118	0	0
T5	711	555	0	0
T9	4617	4517	0	0
T10	3671	3579	0	0
T22	3362	3298	0	0
T23	1325	1274	0	0
T24	1743	1664	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230342208	230173598	0	0
T1	2524	2443	0	0
T2	783	612	0	0
T3	5582	5493	0	0
T4	1233	1118	0	0
T5	711	555	0	0
T9	4617	4517	0	0
T10	3671	3579	0	0
T22	3362	3298	0	0
T23	1325	1274	0	0
T24	1743	1664	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230342208	230173598	0	0
T1	2524	2443	0	0
T2	783	612	0	0
T3	5582	5493	0	0
T4	1233	1118	0	0
T5	711	555	0	0
T9	4617	4517	0	0
T10	3671	3579	0	0
T22	3362	3298	0	0
T23	1325	1274	0	0
T24	1743	1664	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	230170882	541187	0	0
T2	783	147	0	0
T3	5582	0	0	0
T4	1233	219	0	0
T5	711	0	0	0
T6	0	421	0	0
T7	0	665	0	0
T9	4617	2844	0	0
T10	3671	1368	0	0
T13	0	1642	0	0
T21	0	534	0	0
T22	3362	0	0	0
T23	1325	0	0	0
T24	1743	0	0	0
T28	0	9	0	0
T38	654435	0	0	0
T61	0	1110	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T9,T10,T13
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T9,T4

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T36
1	1	0	Not Covered
1	1	1	Covered	T2,T9,T4

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T33,T34,T158
1	0	1	Covered	T2,T9,T4
1	1	0	Not Covered
1	1	1	Covered	T9,T10,T13

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T9,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	229989541	505913	0	0
DepthKnown_A	230342208	230173598	0	0
RvalidKnown_A	230342208	230173598	0	0
WreadyKnown_A	230342208	230173598	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	230170882	552378	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	229989541	505913	0	0
T4	110	0	0	0
T5	300	0	0	0
T6	0	119	0	0
T7	0	42	0	0
T8	0	32	0	0
T9	4617	2855	0	0
T10	3671	1469	0	0
T13	0	1710	0	0
T21	0	645	0	0
T23	1325	0	0	0
T24	1743	0	0	0
T28	0	34	0	0
T38	654435	0	0	0
T39	479063	0	0	0
T51	1862	0	0	0
T75	0	1518	0	0
T77	0	1088	0	0
T79	1756	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230342208	230173598	0	0
T1	2524	2443	0	0
T2	783	612	0	0
T3	5582	5493	0	0
T4	1233	1118	0	0
T5	711	555	0	0
T9	4617	4517	0	0
T10	3671	3579	0	0
T22	3362	3298	0	0
T23	1325	1274	0	0
T24	1743	1664	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230342208	230173598	0	0
T1	2524	2443	0	0
T2	783	612	0	0
T3	5582	5493	0	0
T4	1233	1118	0	0
T5	711	555	0	0
T9	4617	4517	0	0
T10	3671	3579	0	0
T22	3362	3298	0	0
T23	1325	1274	0	0
T24	1743	1664	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230342208	230173598	0	0
T1	2524	2443	0	0
T2	783	612	0	0
T3	5582	5493	0	0
T4	1233	1118	0	0
T5	711	555	0	0
T9	4617	4517	0	0
T10	3671	3579	0	0
T22	3362	3298	0	0
T23	1325	1274	0	0
T24	1743	1664	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	230170882	552378	0	0
T2	783	145	0	0
T3	5582	0	0	0
T4	1233	216	0	0
T5	711	0	0	0
T6	0	574	0	0
T7	0	681	0	0
T9	4617	2855	0	0
T10	3671	1469	0	0
T13	0	1710	0	0
T21	0	645	0	0
T22	3362	0	0	0
T23	1325	0	0	0
T24	1743	0	0	0
T28	0	34	0	0
T38	654435	0	0	0
T61	0	1108	0	0