Unified Coverage Report :: Module :: edn

Module : edn

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	94.44		83.33	100.00			100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.96	98.24	93.80	97.02	84.30	96.62	99.77

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
edn_csr_assert	100.00						100.00
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_edn_core	92.90	99.92	92.46	82.54	84.30	99.28	98.88
u_edn_cov_if	25.00	50.00	0.00
u_reg	96.95	95.02	97.57	100.00		92.16	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Cond Coverage for Module : edn

	Total	Covered	Percent
Conditions	6	5	83.33
Logical	6	5	83.33
Non-Logical	0	0
Event	0	0

 LINE       98
 EXPRESSION (alert[0] || intg_err_alert[0])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T20,T26,T27

 LINE       98
 EXPRESSION (alert[1] || intg_err_alert[1])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T15,T16
1	0	Covered	T5,T6,T14

---

Toggle Coverage for Module : edn

	Total	Covered	Percent
Totals	69	69	100.00
Total Bits	1172	1172	100.00
Total Bits 0->1	586	586	100.00
Total Bits 1->0	586	586	100.00

Ports	69	69	100.00
Port Bits	1172	1172	100.00
Port Bits 0->1	586	586	100.00
Port Bits 1->0	586	586	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T4,T5,T6	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T4,T117,T118	Yes	T4,T117,T118	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T3,*T4	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i[0].edn_req	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
edn_i[1].edn_req	Yes	Yes	T19,T28,T119	Yes	T19,T28,T119	INPUT
edn_i[2].edn_req	Yes	Yes	T3,T5,T19	Yes	T3,T5,T19	INPUT
edn_i[3].edn_req	Yes	Yes	T3,T19,T55	Yes	T3,T19,T55	INPUT
edn_i[4].edn_req	Yes	Yes	T3,T19,T120	Yes	T3,T19,T120	INPUT
edn_i[5].edn_req	Yes	Yes	T19,T121,T122	Yes	T19,T121,T122	INPUT
edn_i[6].edn_req	Yes	Yes	T19,T10,T22	Yes	T19,T10,T22	INPUT
edn_o[0].edn_bus[31:0]	Yes	Yes	T1,T4,T19	Yes	T1,T3,T4	OUTPUT
edn_o[0].edn_fips	Yes	Yes	T4,T19,T11	Yes	T3,T4,T19	OUTPUT
edn_o[0].edn_ack	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
edn_o[1].edn_bus[31:0]	Yes	Yes	T19,T28,T119	Yes	T19,T28,T119	OUTPUT
edn_o[1].edn_fips	Yes	Yes	T19,T28,T119	Yes	T19,T28,T119	OUTPUT
edn_o[1].edn_ack	Yes	Yes	T19,T28,T119	Yes	T19,T28,T119	OUTPUT
edn_o[2].edn_bus[31:0]	Yes	Yes	T3,T5,T19	Yes	T3,T5,T19	OUTPUT
edn_o[2].edn_fips	Yes	Yes	T5,T121,T29	Yes	T5,T121,T29	OUTPUT
edn_o[2].edn_ack	Yes	Yes	T3,T5,T19	Yes	T3,T5,T19	OUTPUT
edn_o[3].edn_bus[31:0]	Yes	Yes	T55,T122,T123	Yes	T19,T55,T122	OUTPUT
edn_o[3].edn_fips	Yes	Yes	T122,T123,T124	Yes	T55,T122,T123	OUTPUT
edn_o[3].edn_ack	Yes	Yes	T3,T19,T55	Yes	T3,T19,T55	OUTPUT
edn_o[4].edn_bus[31:0]	Yes	Yes	T3,T19,T120	Yes	T3,T19,T120	OUTPUT
edn_o[4].edn_fips	Yes	Yes	T3,T19,T120	Yes	T3,T19,T120	OUTPUT
edn_o[4].edn_ack	Yes	Yes	T3,T19,T120	Yes	T3,T19,T120	OUTPUT
edn_o[5].edn_bus[31:0]	Yes	Yes	T19,T121,T122	Yes	T19,T121,T122	OUTPUT
edn_o[5].edn_fips	Yes	Yes	T19,T121,T122	Yes	T19,T121,T122	OUTPUT
edn_o[5].edn_ack	Yes	Yes	T19,T121,T122	Yes	T19,T121,T122	OUTPUT
edn_o[6].edn_bus[31:0]	Yes	Yes	T19,T10,T23	Yes	T19,T10,T22	OUTPUT
edn_o[6].edn_fips	Yes	Yes	T125,T13,T126	Yes	T10,T22,T28	OUTPUT
edn_o[6].edn_ack	Yes	Yes	T19,T10,T22	Yes	T19,T10,T22	OUTPUT
csrng_cmd_o.genbits_ready	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
csrng_cmd_o.csrng_req_bus[31:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
csrng_cmd_o.csrng_req_valid	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
csrng_cmd_i.genbits_bus[127:0]	Yes	Yes	T3,T4,T19	Yes	T3,T4,T19	INPUT
csrng_cmd_i.genbits_fips	Yes	Yes	T3,T4,T19	Yes	T3,T4,T19	INPUT
csrng_cmd_i.genbits_valid	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
csrng_cmd_i.csrng_rsp_sts[2:0]	Yes	Yes	T69,T99,T70	Yes	T69,T99,T70	INPUT
csrng_cmd_i.csrng_rsp_ack	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
csrng_cmd_i.csrng_req_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T2,T20,T26	Yes	T2,T20,T26	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T2,T5,T6	Yes	T2,T5,T6	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T2,T20,T26	Yes	T2,T20,T26	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T2,T5,T6	Yes	T2,T5,T6	OUTPUT
intr_edn_cmd_req_done_o	Yes	Yes	T4,T103,T117	Yes	T4,T103,T117	OUTPUT
intr_edn_fatal_err_o	Yes	Yes	T4,T5,T105	Yes	T4,T5,T105	OUTPUT

*Tests covering at least one bit in the range

---

Assert Coverage for Module : edn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	47	47	100.00	47	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	47	47	100.00	47	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxKnownO_A	222469498	222304030	0	0
CsrngAppIfOut_A	222469498	222304030	0	0
FpvSecCmCntAlertCheck_A	222469498	110	0	0
FpvSecCmGenCmdFifoRptrCheck_A	222469498	70	0	0
FpvSecCmGenCmdFifoWptrCheck_A	222469498	70	0	0
FpvSecCmMainFsmCheck_A	222469498	70	0	0
FpvSecCmRegWeOnehotCheck_A	222469498	70	0	0
FpvSecCmResCmdFifoRptrCheck_A	222469498	70	0	0
FpvSecCmResCmdFifoWptrCheck_A	222469498	70	0	0
IntrEdnCmdReqDoneKnownO_A	222469498	222304030	0	0
TlAReadyKnownO_A	222469498	222304030	0	0
TlDValidKnownO_A	222469498	222304030	0	0
gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A	222469498	70	0	0
gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A	222469498	70	0	0
gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A	222469498	70	0	0
gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A	222469498	70	0	0
gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A	222469498	70	0	0
gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A	222469498	70	0	0
gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A	222469498	70	0	0
gen_edn_if_asserts[0].EdnDataStableDisable_A	222469498	517852	0	326
gen_edn_if_asserts[0].EdnDataStable_A	222469498	25626	0	350
gen_edn_if_asserts[0].EdnEndPointOut_A	222469498	222304030	0	0
gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A	222469498	142542	0	0
gen_edn_if_asserts[1].EdnDataStableDisable_A	222469498	517852	0	326
gen_edn_if_asserts[1].EdnDataStable_A	222469498	3486	0	122
gen_edn_if_asserts[1].EdnEndPointOut_A	222469498	222304030	0	0
gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A	222469498	142542	0	0
gen_edn_if_asserts[2].EdnDataStableDisable_A	222469498	517852	0	326
gen_edn_if_asserts[2].EdnDataStable_A	222469498	4331	0	102
gen_edn_if_asserts[2].EdnEndPointOut_A	222469498	222304030	0	0
gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A	222469498	142542	0	0
gen_edn_if_asserts[3].EdnDataStableDisable_A	222469498	517852	0	326
gen_edn_if_asserts[3].EdnDataStable_A	222469498	5117	0	92
gen_edn_if_asserts[3].EdnEndPointOut_A	222469498	222304030	0	0
gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A	222469498	142542	0	0
gen_edn_if_asserts[4].EdnDataStableDisable_A	222469498	517852	0	326
gen_edn_if_asserts[4].EdnDataStable_A	222469498	5345	0	103
gen_edn_if_asserts[4].EdnEndPointOut_A	222469498	222304030	0	0
gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A	222469498	142542	0	0
gen_edn_if_asserts[5].EdnDataStableDisable_A	222469498	517852	0	326
gen_edn_if_asserts[5].EdnDataStable_A	222469498	1610	0	70
gen_edn_if_asserts[5].EdnEndPointOut_A	222469498	222304030	0	0
gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A	222469498	142542	0	0
gen_edn_if_asserts[6].EdnDataStableDisable_A	222469498	517852	0	326
gen_edn_if_asserts[6].EdnDataStable_A	222469498	1387	0	85
gen_edn_if_asserts[6].EdnEndPointOut_A	222469498	222304030	0	0
gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A	222469498	142542	0	0

AlertTxKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222469498	222304030	0	0
T1	3154	3087	0	0
T2	929	874	0	0
T3	4338	4280	0	0
T4	457515	457502	0	0
T5	499	356	0	0
T6	45422	23834	0	0
T10	3564	3465	0	0
T19	2317	2239	0	0
T20	1984	1912	0	0
T21	1425	1363	0	0

CsrngAppIfOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222469498	222304030	0	0
T1	3154	3087	0	0
T2	929	874	0	0
T3	4338	4280	0	0
T4	457515	457502	0	0
T5	499	356	0	0
T6	45422	23834	0	0
T10	3564	3465	0	0
T19	2317	2239	0	0
T20	1984	1912	0	0
T21	1425	1363	0	0

FpvSecCmCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222469498	110	0	0
T6	45422	20	0	0
T7	0	1	0	0
T10	3564	0	0	0
T11	2653	0	0	0
T14	1037	1	0	0
T15	0	10	0	0
T19	2317	0	0	0
T20	1984	0	0	0
T21	1425	0	0	0
T22	1010	0	0	0
T24	827	0	0	0
T72	0	1	0	0
T75	0	1	0	0
T92	0	1	0	0
T102	0	1	0	0
T106	1614	0	0	0
T127	0	1	0	0
T128	0	1	0	0

FpvSecCmGenCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222469498	70	0	0
T6	45422	20	0	0
T10	3564	0	0	0
T11	2653	0	0	0
T14	1037	0	0	0
T15	0	10	0	0
T16	0	10	0	0
T19	2317	0	0	0
T20	1984	0	0	0
T21	1425	0	0	0
T22	1010	0	0	0
T24	827	0	0	0
T106	1614	0	0	0
T129	0	10	0	0
T130	0	20	0	0

FpvSecCmGenCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222469498	70	0	0
T6	45422	20	0	0
T10	3564	0	0	0
T11	2653	0	0	0
T14	1037	0	0	0
T15	0	10	0	0
T16	0	10	0	0
T19	2317	0	0	0
T20	1984	0	0	0
T21	1425	0	0	0
T22	1010	0	0	0
T24	827	0	0	0
T106	1614	0	0	0
T129	0	10	0	0
T130	0	20	0	0

FpvSecCmMainFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222469498	70	0	0
T6	45422	20	0	0
T10	3564	0	0	0
T11	2653	0	0	0
T14	1037	0	0	0
T15	0	10	0	0
T16	0	10	0	0
T19	2317	0	0	0
T20	1984	0	0	0
T21	1425	0	0	0
T22	1010	0	0	0
T24	827	0	0	0
T106	1614	0	0	0
T129	0	10	0	0
T130	0	20	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222469498	70	0	0
T6	45422	20	0	0
T10	3564	0	0	0
T11	2653	0	0	0
T14	1037	0	0	0
T15	0	10	0	0
T16	0	10	0	0
T19	2317	0	0	0
T20	1984	0	0	0
T21	1425	0	0	0
T22	1010	0	0	0
T24	827	0	0	0
T106	1614	0	0	0
T129	0	10	0	0
T130	0	20	0	0

FpvSecCmResCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222469498	70	0	0
T6	45422	20	0	0
T10	3564	0	0	0
T11	2653	0	0	0
T14	1037	0	0	0
T15	0	10	0	0
T16	0	10	0	0
T19	2317	0	0	0
T20	1984	0	0	0
T21	1425	0	0	0
T22	1010	0	0	0
T24	827	0	0	0
T106	1614	0	0	0
T129	0	10	0	0
T130	0	20	0	0

FpvSecCmResCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222469498	70	0	0
T6	45422	20	0	0
T10	3564	0	0	0
T11	2653	0	0	0
T14	1037	0	0	0
T15	0	10	0	0
T16	0	10	0	0
T19	2317	0	0	0
T20	1984	0	0	0
T21	1425	0	0	0
T22	1010	0	0	0
T24	827	0	0	0
T106	1614	0	0	0
T129	0	10	0	0
T130	0	20	0	0

IntrEdnCmdReqDoneKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222469498	222304030	0	0
T1	3154	3087	0	0
T2	929	874	0	0
T3	4338	4280	0	0
T4	457515	457502	0	0
T5	499	356	0	0
T6	45422	23834	0	0
T10	3564	3465	0	0
T19	2317	2239	0	0
T20	1984	1912	0	0
T21	1425	1363	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222469498	222304030	0	0
T1	3154	3087	0	0
T2	929	874	0	0
T3	4338	4280	0	0
T4	457515	457502	0	0
T5	499	356	0	0
T6	45422	23834	0	0
T10	3564	3465	0	0
T19	2317	2239	0	0
T20	1984	1912	0	0
T21	1425	1363	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222469498	222304030	0	0
T1	3154	3087	0	0
T2	929	874	0	0
T3	4338	4280	0	0
T4	457515	457502	0	0
T5	499	356	0	0
T6	45422	23834	0	0
T10	3564	3465	0	0
T19	2317	2239	0	0
T20	1984	1912	0	0
T21	1425	1363	0	0

gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222469498	70	0	0
T6	45422	20	0	0
T10	3564	0	0	0
T11	2653	0	0	0
T14	1037	0	0	0
T15	0	10	0	0
T16	0	10	0	0
T19	2317	0	0	0
T20	1984	0	0	0
T21	1425	0	0	0
T22	1010	0	0	0
T24	827	0	0	0
T106	1614	0	0	0
T129	0	10	0	0
T130	0	20	0	0

gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222469498	70	0	0
T6	45422	20	0	0
T10	3564	0	0	0
T11	2653	0	0	0
T14	1037	0	0	0
T15	0	10	0	0
T16	0	10	0	0
T19	2317	0	0	0
T20	1984	0	0	0
T21	1425	0	0	0
T22	1010	0	0	0
T24	827	0	0	0
T106	1614	0	0	0
T129	0	10	0	0
T130	0	20	0	0

gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222469498	70	0	0
T6	45422	20	0	0
T10	3564	0	0	0
T11	2653	0	0	0
T14	1037	0	0	0
T15	0	10	0	0
T16	0	10	0	0
T19	2317	0	0	0
T20	1984	0	0	0
T21	1425	0	0	0
T22	1010	0	0	0
T24	827	0	0	0
T106	1614	0	0	0
T129	0	10	0	0
T130	0	20	0	0

gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222469498	70	0	0
T6	45422	20	0	0
T10	3564	0	0	0
T11	2653	0	0	0
T14	1037	0	0	0
T15	0	10	0	0
T16	0	10	0	0
T19	2317	0	0	0
T20	1984	0	0	0
T21	1425	0	0	0
T22	1010	0	0	0
T24	827	0	0	0
T106	1614	0	0	0
T129	0	10	0	0
T130	0	20	0	0

gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222469498	70	0	0
T6	45422	20	0	0
T10	3564	0	0	0
T11	2653	0	0	0
T14	1037	0	0	0
T15	0	10	0	0
T16	0	10	0	0
T19	2317	0	0	0
T20	1984	0	0	0
T21	1425	0	0	0
T22	1010	0	0	0
T24	827	0	0	0
T106	1614	0	0	0
T129	0	10	0	0
T130	0	20	0	0

gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222469498	70	0	0
T6	45422	20	0	0
T10	3564	0	0	0
T11	2653	0	0	0
T14	1037	0	0	0
T15	0	10	0	0
T16	0	10	0	0
T19	2317	0	0	0
T20	1984	0	0	0
T21	1425	0	0	0
T22	1010	0	0	0
T24	827	0	0	0
T106	1614	0	0	0
T129	0	10	0	0
T130	0	20	0	0

gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222469498	70	0	0
T6	45422	20	0	0
T10	3564	0	0	0
T11	2653	0	0	0
T14	1037	0	0	0
T15	0	10	0	0
T16	0	10	0	0
T19	2317	0	0	0
T20	1984	0	0	0
T21	1425	0	0	0
T22	1010	0	0	0
T24	827	0	0	0
T106	1614	0	0	0
T129	0	10	0	0
T130	0	20	0	0

gen_edn_if_asserts[0].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222469498	517852	0	326
T1	3154	14	0	0
T2	929	872	0	2
T3	4338	332	0	0
T4	457515	1598	0	2
T5	499	123	0	0
T6	45422	19191	0	2
T10	3564	1203	0	2
T17	0	0	0	2
T19	2317	20	0	0
T20	1984	152	0	0
T21	1425	17	0	0
T25	0	0	0	2
T55	0	0	0	2
T56	0	0	0	2
T117	0	0	0	2
T118	0	0	0	2

gen_edn_if_asserts[0].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222469498	25626	0	350
T1	3154	3	0	1
T2	929	0	0	0
T3	4338	3	0	1
T4	457515	83	0	0
T5	499	0	0	0
T6	45422	0	0	0
T10	3564	0	0	0
T11	0	59	0	1
T19	2317	31	0	1
T20	1984	8	0	1
T21	1425	3	0	1
T24	0	3	0	1
T105	0	1	0	0
T106	0	3	0	1
T121	0	0	0	1
T131	0	0	0	1

gen_edn_if_asserts[0].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222469498	222304030	0	0
T1	3154	3087	0	0
T2	929	874	0	0
T3	4338	4280	0	0
T4	457515	457502	0	0
T5	499	356	0	0
T6	45422	23834	0	0
T10	3564	3465	0	0
T19	2317	2239	0	0
T20	1984	1912	0	0
T21	1425	1363	0	0

gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222469498	142542	0	0
T5	499	200	0	0
T6	45422	17710	0	0
T7	0	1094	0	0
T8	0	404	0	0
T9	0	602	0	0
T10	3564	0	0	0
T11	2653	0	0	0
T14	1037	604	0	0
T19	2317	0	0	0
T20	1984	0	0	0
T21	1425	0	0	0
T24	827	0	0	0
T75	0	604	0	0
T76	0	352	0	0
T102	0	604	0	0
T105	0	1115	0	0
T106	1614	0	0	0

gen_edn_if_asserts[1].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222469498	517852	0	326
T1	3154	14	0	0
T2	929	872	0	2
T3	4338	332	0	0
T4	457515	1598	0	2
T5	499	123	0	0
T6	45422	19191	0	2
T10	3564	1203	0	2
T17	0	0	0	2
T19	2317	20	0	0
T20	1984	152	0	0
T21	1425	17	0	0
T25	0	0	0	2
T55	0	0	0	2
T56	0	0	0	2
T117	0	0	0	2
T118	0	0	0	2

gen_edn_if_asserts[1].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222469498	3486	0	122
T10	3564	0	0	0
T11	2653	0	0	0
T14	1037	0	0	0
T17	0	4	0	0
T19	2317	24	0	1
T20	1984	0	0	0
T21	1425	0	0	0
T22	1010	0	0	0
T24	827	0	0	0
T28	0	31	0	1
T61	0	4	0	0
T69	0	4	0	0
T82	0	3	0	1
T105	2220	0	0	0
T106	1614	0	0	0
T119	0	43	0	1
T122	0	3	0	1
T124	0	0	0	1
T132	0	21	0	1
T133	0	19	0	1
T134	0	0	0	1
T135	0	0	0	1

gen_edn_if_asserts[1].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222469498	222304030	0	0
T1	3154	3087	0	0
T2	929	874	0	0
T3	4338	4280	0	0
T4	457515	457502	0	0
T5	499	356	0	0
T6	45422	23834	0	0
T10	3564	3465	0	0
T19	2317	2239	0	0
T20	1984	1912	0	0
T21	1425	1363	0	0

gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222469498	142542	0	0
T5	499	200	0	0
T6	45422	17710	0	0
T7	0	1094	0	0
T8	0	404	0	0
T9	0	602	0	0
T10	3564	0	0	0
T11	2653	0	0	0
T14	1037	604	0	0
T19	2317	0	0	0
T20	1984	0	0	0
T21	1425	0	0	0
T24	827	0	0	0
T75	0	604	0	0
T76	0	352	0	0
T102	0	604	0	0
T105	0	1115	0	0
T106	1614	0	0	0

gen_edn_if_asserts[2].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222469498	517852	0	326
T1	3154	14	0	0
T2	929	872	0	2
T3	4338	332	0	0
T4	457515	1598	0	2
T5	499	123	0	0
T6	45422	19191	0	2
T10	3564	1203	0	2
T17	0	0	0	2
T19	2317	20	0	0
T20	1984	152	0	0
T21	1425	17	0	0
T25	0	0	0	2
T55	0	0	0	2
T56	0	0	0	2
T117	0	0	0	2
T118	0	0	0	2

gen_edn_if_asserts[2].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222469498	4331	0	102
T3	4338	3	0	1
T4	457515	0	0	0
T5	499	1	0	0
T6	45422	0	0	0
T10	3564	0	0	0
T14	1037	0	0	0
T19	2317	3	0	1
T20	1984	0	0	0
T21	1425	0	0	0
T24	827	0	0	0
T27	0	8	0	1
T29	0	29	0	1
T121	0	53	0	1
T124	0	54	0	1
T125	0	0	0	1
T133	0	34	0	1
T134	0	0	0	1
T136	0	4	0	0
T137	0	3	0	1

gen_edn_if_asserts[2].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222469498	222304030	0	0
T1	3154	3087	0	0
T2	929	874	0	0
T3	4338	4280	0	0
T4	457515	457502	0	0
T5	499	356	0	0
T6	45422	23834	0	0
T10	3564	3465	0	0
T19	2317	2239	0	0
T20	1984	1912	0	0
T21	1425	1363	0	0

gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222469498	142542	0	0
T5	499	200	0	0
T6	45422	17710	0	0
T7	0	1094	0	0
T8	0	404	0	0
T9	0	602	0	0
T10	3564	0	0	0
T11	2653	0	0	0
T14	1037	604	0	0
T19	2317	0	0	0
T20	1984	0	0	0
T21	1425	0	0	0
T24	827	0	0	0
T75	0	604	0	0
T76	0	352	0	0
T102	0	604	0	0
T105	0	1115	0	0
T106	1614	0	0	0

gen_edn_if_asserts[3].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222469498	517852	0	326
T1	3154	14	0	0
T2	929	872	0	2
T3	4338	332	0	0
T4	457515	1598	0	2
T5	499	123	0	0
T6	45422	19191	0	2
T10	3564	1203	0	2
T17	0	0	0	2
T19	2317	20	0	0
T20	1984	152	0	0
T21	1425	17	0	0
T25	0	0	0	2
T55	0	0	0	2
T56	0	0	0	2
T117	0	0	0	2
T118	0	0	0	2

gen_edn_if_asserts[3].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222469498	5117	0	92
T3	4338	3	0	1
T4	457515	0	0	0
T5	499	0	0	0
T6	45422	0	0	0
T10	3564	0	0	0
T13	0	3	0	1
T14	1037	0	0	0
T18	0	3	0	1
T19	2317	3	0	1
T20	1984	0	0	0
T21	1425	0	0	0
T24	827	0	0	0
T35	0	4	0	0
T55	0	4	0	0
T122	0	23	0	1
T123	0	33	0	1
T124	0	62	0	1
T133	0	3	0	1
T138	0	0	0	1
T139	0	0	0	1

gen_edn_if_asserts[3].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222469498	222304030	0	0
T1	3154	3087	0	0
T2	929	874	0	0
T3	4338	4280	0	0
T4	457515	457502	0	0
T5	499	356	0	0
T6	45422	23834	0	0
T10	3564	3465	0	0
T19	2317	2239	0	0
T20	1984	1912	0	0
T21	1425	1363	0	0

gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222469498	142542	0	0
T5	499	200	0	0
T6	45422	17710	0	0
T7	0	1094	0	0
T8	0	404	0	0
T9	0	602	0	0
T10	3564	0	0	0
T11	2653	0	0	0
T14	1037	604	0	0
T19	2317	0	0	0
T20	1984	0	0	0
T21	1425	0	0	0
T24	827	0	0	0
T75	0	604	0	0
T76	0	352	0	0
T102	0	604	0	0
T105	0	1115	0	0
T106	1614	0	0	0

gen_edn_if_asserts[4].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222469498	517852	0	326
T1	3154	14	0	0
T2	929	872	0	2
T3	4338	332	0	0
T4	457515	1598	0	2
T5	499	123	0	0
T6	45422	19191	0	2
T10	3564	1203	0	2
T17	0	0	0	2
T19	2317	20	0	0
T20	1984	152	0	0
T21	1425	17	0	0
T25	0	0	0	2
T55	0	0	0	2
T56	0	0	0	2
T117	0	0	0	2
T118	0	0	0	2

gen_edn_if_asserts[4].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222469498	5345	0	103
T3	4338	207	0	1
T4	457515	0	0	0
T5	499	0	0	0
T6	45422	0	0	0
T10	3564	0	0	0
T13	0	0	0	1
T14	1037	0	0	0
T18	0	543	0	1
T19	2317	49	0	1
T20	1984	0	0	0
T21	1425	0	0	0
T24	827	0	0	0
T56	0	4	0	0
T120	0	36	0	1
T123	0	53	0	1
T124	0	16	0	1
T125	0	3	0	1
T133	0	14	0	1
T134	0	3	0	1

gen_edn_if_asserts[4].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222469498	222304030	0	0
T1	3154	3087	0	0
T2	929	874	0	0
T3	4338	4280	0	0
T4	457515	457502	0	0
T5	499	356	0	0
T6	45422	23834	0	0
T10	3564	3465	0	0
T19	2317	2239	0	0
T20	1984	1912	0	0
T21	1425	1363	0	0

gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222469498	142542	0	0
T5	499	200	0	0
T6	45422	17710	0	0
T7	0	1094	0	0
T8	0	404	0	0
T9	0	602	0	0
T10	3564	0	0	0
T11	2653	0	0	0
T14	1037	604	0	0
T19	2317	0	0	0
T20	1984	0	0	0
T21	1425	0	0	0
T24	827	0	0	0
T75	0	604	0	0
T76	0	352	0	0
T102	0	604	0	0
T105	0	1115	0	0
T106	1614	0	0	0

gen_edn_if_asserts[5].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222469498	517852	0	326
T1	3154	14	0	0
T2	929	872	0	2
T3	4338	332	0	0
T4	457515	1598	0	2
T5	499	123	0	0
T6	45422	19191	0	2
T10	3564	1203	0	2
T17	0	0	0	2
T19	2317	20	0	0
T20	1984	152	0	0
T21	1425	17	0	0
T25	0	0	0	2
T55	0	0	0	2
T56	0	0	0	2
T117	0	0	0	2
T118	0	0	0	2

gen_edn_if_asserts[5].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222469498	1610	0	70
T10	3564	0	0	0
T11	2653	0	0	0
T14	1037	0	0	0
T19	2317	35	0	1
T20	1984	0	0	0
T21	1425	0	0	0
T22	1010	0	0	0
T24	827	0	0	0
T69	0	4	0	1
T105	2220	0	0	0
T106	1614	0	0	0
T121	0	28	0	1
T122	0	31	0	1
T123	0	11	0	1
T124	0	46	0	1
T125	0	52	0	1
T133	0	25	0	1
T134	0	28	0	1
T137	0	24	0	1

gen_edn_if_asserts[5].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222469498	222304030	0	0
T1	3154	3087	0	0
T2	929	874	0	0
T3	4338	4280	0	0
T4	457515	457502	0	0
T5	499	356	0	0
T6	45422	23834	0	0
T10	3564	3465	0	0
T19	2317	2239	0	0
T20	1984	1912	0	0
T21	1425	1363	0	0

gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222469498	142542	0	0
T5	499	200	0	0
T6	45422	17710	0	0
T7	0	1094	0	0
T8	0	404	0	0
T9	0	602	0	0
T10	3564	0	0	0
T11	2653	0	0	0
T14	1037	604	0	0
T19	2317	0	0	0
T20	1984	0	0	0
T21	1425	0	0	0
T24	827	0	0	0
T75	0	604	0	0
T76	0	352	0	0
T102	0	604	0	0
T105	0	1115	0	0
T106	1614	0	0	0

gen_edn_if_asserts[6].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222469498	517852	0	326
T1	3154	14	0	0
T2	929	872	0	2
T3	4338	332	0	0
T4	457515	1598	0	2
T5	499	123	0	0
T6	45422	19191	0	2
T10	3564	1203	0	2
T17	0	0	0	2
T19	2317	20	0	0
T20	1984	152	0	0
T21	1425	17	0	0
T25	0	0	0	2
T55	0	0	0	2
T56	0	0	0	2
T117	0	0	0	2
T118	0	0	0	2

gen_edn_if_asserts[6].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222469498	1387	0	85
T10	3564	4	0	0
T11	2653	0	0	0
T14	1037	0	0	0
T19	2317	3	0	1
T20	1984	0	0	0
T21	1425	0	0	0
T22	1010	3	0	1
T23	0	4	0	0
T24	827	0	0	0
T25	0	4	0	0
T28	0	19	0	1
T86	0	3	0	1
T105	2220	0	0	0
T106	1614	0	0	0
T119	0	13	0	1
T120	0	3	0	1
T121	0	4	0	1
T123	0	0	0	1
T124	0	0	0	1
T133	0	0	0	1

gen_edn_if_asserts[6].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222469498	222304030	0	0
T1	3154	3087	0	0
T2	929	874	0	0
T3	4338	4280	0	0
T4	457515	457502	0	0
T5	499	356	0	0
T6	45422	23834	0	0
T10	3564	3465	0	0
T19	2317	2239	0	0
T20	1984	1912	0	0
T21	1425	1363	0	0

gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222469498	142542	0	0
T5	499	200	0	0
T6	45422	17710	0	0
T7	0	1094	0	0
T8	0	404	0	0
T9	0	602	0	0
T10	3564	0	0	0
T11	2653	0	0	0
T14	1037	604	0	0
T19	2317	0	0	0
T20	1984	0	0	0
T21	1425	0	0	0
T24	827	0	0	0
T75	0	604	0	0
T76	0	352	0	0
T102	0	604	0	0
T105	0	1115	0	0
T106	1614	0	0	0