Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44		83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	223001072	9298698	0	0
boot_gen_cmd_rd_A	223001072	74690	0	0
boot_ins_cmd_rd_A	223001072	85088	0	0
ctrl_rd_A	223001072	74977	0	0
err_code_test_rd_A	223001072	85250	0	0
intr_enable_rd_A	223001072	82747	0	0
max_num_reqs_between_reseeds_rd_A	223001072	77207	0	0
regwen_rd_A	223001072	86592	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223001072	9298698	0	0
T4	457515	158438	0	0
T5	499	0	0	0
T6	45422	0	0	0
T10	3564	0	0	0
T14	1037	0	0	0
T19	2317	0	0	0
T20	1984	0	0	0
T21	1425	0	0	0
T24	827	0	0	0
T106	1614	0	0	0
T117	0	74255	0	0
T118	0	109690	0	0
T145	0	224328	0	0
T146	0	78462	0	0
T147	0	132439	0	0
T150	0	238817	0	0
T151	0	71078	0	0
T184	0	55337	0	0
T185	0	144713	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223001072	74690	0	0
T4	457515	4144	0	0
T5	499	0	0	0
T6	45422	0	0	0
T10	3564	0	0	0
T14	1037	0	0	0
T19	2317	0	0	0
T20	1984	0	0	0
T21	1425	0	0	0
T24	827	0	0	0
T106	1614	0	0	0
T147	0	2026	0	0
T184	0	1469	0	0
T186	0	6936	0	0
T187	0	2163	0	0
T188	0	5978	0	0
T189	0	5903	0	0
T190	0	10411	0	0
T191	0	1619	0	0
T192	0	2398	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223001072	85088	0	0
T4	457515	4945	0	0
T5	499	0	0	0
T6	45422	0	0	0
T10	3564	0	0	0
T14	1037	0	0	0
T19	2317	0	0	0
T20	1984	0	0	0
T21	1425	0	0	0
T24	827	0	0	0
T106	1614	0	0	0
T147	0	2298	0	0
T184	0	1753	0	0
T186	0	7787	0	0
T187	0	2266	0	0
T188	0	6538	0	0
T189	0	6758	0	0
T190	0	11895	0	0
T191	0	1869	0	0
T192	0	2794	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223001072	74977	0	0
T4	457515	4422	0	0
T5	499	0	0	0
T6	45422	0	0	0
T10	3564	0	0	0
T14	1037	0	0	0
T19	2317	0	0	0
T20	1984	0	0	0
T21	1425	0	0	0
T24	827	0	0	0
T62	0	2	0	0
T106	1614	0	0	0
T107	0	2	0	0
T131	0	7	0	0
T133	0	1	0	0
T147	0	1940	0	0
T184	0	1655	0	0
T193	0	9	0	0
T194	0	3	0	0
T195	0	3	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223001072	85250	0	0
T4	457515	4860	0	0
T5	499	0	0	0
T6	45422	0	0	0
T10	3564	0	0	0
T14	1037	0	0	0
T19	2317	0	0	0
T20	1984	0	0	0
T21	1425	0	0	0
T24	827	0	0	0
T106	1614	0	0	0
T147	0	2031	0	0
T184	0	1793	0	0
T186	0	8250	0	0
T187	0	2466	0	0
T188	0	6944	0	0
T189	0	6508	0	0
T190	0	12010	0	0
T191	0	1953	0	0
T192	0	2434	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223001072	82747	0	0
T4	457515	4509	0	0
T5	499	0	0	0
T6	45422	0	0	0
T10	3564	0	0	0
T14	1037	0	0	0
T19	2317	0	0	0
T20	1984	0	0	0
T21	1425	0	0	0
T24	827	0	0	0
T106	1614	0	0	0
T147	0	2220	0	0
T184	0	1986	0	0
T186	0	7216	0	0
T187	0	2253	0	0
T188	0	6139	0	0
T194	0	60	0	0
T196	0	47	0	0
T197	0	26	0	0
T198	0	32	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223001072	77207	0	0
T4	457515	4739	0	0
T5	499	0	0	0
T6	45422	0	0	0
T10	3564	0	0	0
T14	1037	0	0	0
T19	2317	0	0	0
T20	1984	0	0	0
T21	1425	0	0	0
T24	827	0	0	0
T106	1614	0	0	0
T147	0	2019	0	0
T184	0	1701	0	0
T186	0	6917	0	0
T187	0	2197	0	0
T188	0	5791	0	0
T189	0	5907	0	0
T190	0	10745	0	0
T191	0	1675	0	0
T192	0	2292	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223001072	86592	0	0
T4	457515	4852	0	0
T5	499	0	0	0
T6	45422	0	0	0
T10	3564	0	0	0
T14	1037	0	0	0
T19	2317	0	0	0
T20	1984	0	0	0
T21	1425	0	0	0
T24	827	0	0	0
T106	1614	0	0	0
T147	0	2363	0	0
T184	0	1763	0	0
T186	0	7866	0	0
T187	0	2367	0	0
T188	0	6553	0	0
T189	0	6858	0	0
T190	0	12018	0	0
T191	0	1872	0	0
T192	0	2752	0	0