Unified Coverage Report :: Module :: edn

Module : edn

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	94.44		83.33	100.00			100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.14	98.24	93.74	97.02	85.47	96.62	99.77

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
edn_csr_assert	100.00						100.00
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_edn_core	93.08	99.92	92.37	82.54	85.47	99.28	98.88
u_edn_cov_if	25.00	50.00	0.00
u_reg	96.95	95.02	97.57	100.00		92.16	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Cond Coverage for Module : edn

	Total	Covered	Percent
Conditions	6	5	83.33
Logical	6	5	83.33
Non-Logical	0	0
Event	0	0

 LINE       98
 EXPRESSION (alert[0] || intg_err_alert[0])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T8,T16,T29

 LINE       98
 EXPRESSION (alert[1] || intg_err_alert[1])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T15
1	0	Covered	T3,T4,T22

---

Toggle Coverage for Module : edn

	Total	Covered	Percent
Totals	69	69	100.00
Total Bits	1172	1172	100.00
Total Bits 0->1	586	586	100.00
Total Bits 1->0	586	586	100.00

Ports	69	69	100.00
Port Bits	1172	1172	100.00
Port Bits 0->1	586	586	100.00
Port Bits 1->0	586	586	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T7	Yes	T1,T2,T7	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T21	Yes	T1,T2,T21	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T1,T37,T38	Yes	T1,T37,T38	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i[0].edn_req	Yes	Yes	T1,T21,T7	Yes	T1,T21,T7	INPUT
edn_i[1].edn_req	Yes	Yes	T3,T21,T39	Yes	T3,T21,T39	INPUT
edn_i[2].edn_req	Yes	Yes	T2,T4,T21	Yes	T2,T4,T21	INPUT
edn_i[3].edn_req	Yes	Yes	T2,T21,T8	Yes	T2,T21,T8	INPUT
edn_i[4].edn_req	Yes	Yes	T2,T18,T40	Yes	T2,T18,T40	INPUT
edn_i[5].edn_req	Yes	Yes	T12,T41,T40	Yes	T12,T41,T40	INPUT
edn_i[6].edn_req	Yes	Yes	T21,T42,T43	Yes	T21,T42,T43	INPUT
edn_o[0].edn_bus[31:0]	Yes	Yes	T1,T21,T7	Yes	T1,T21,T7	OUTPUT
edn_o[0].edn_fips	Yes	Yes	T1,T21,T7	Yes	T1,T21,T7	OUTPUT
edn_o[0].edn_ack	Yes	Yes	T1,T21,T7	Yes	T1,T21,T7	OUTPUT
edn_o[1].edn_bus[31:0]	Yes	Yes	T21,T39,T44	Yes	T21,T39,T40	OUTPUT
edn_o[1].edn_fips	Yes	Yes	T21,T39,T44	Yes	T21,T39,T40	OUTPUT
edn_o[1].edn_ack	Yes	Yes	T21,T39,T40	Yes	T21,T39,T40	OUTPUT
edn_o[2].edn_bus[31:0]	Yes	Yes	T2,T21,T40	Yes	T2,T21,T17	OUTPUT
edn_o[2].edn_fips	Yes	Yes	T21,T44,T45	Yes	T21,T17,T44	OUTPUT
edn_o[2].edn_ack	Yes	Yes	T2,T21,T22	Yes	T2,T21,T22	OUTPUT
edn_o[3].edn_bus[31:0]	Yes	Yes	T21,T8,T42	Yes	T21,T8,T42	OUTPUT
edn_o[3].edn_fips	Yes	Yes	T21,T40,T46	Yes	T2,T21,T40	OUTPUT
edn_o[3].edn_ack	Yes	Yes	T2,T21,T8	Yes	T2,T21,T8	OUTPUT
edn_o[4].edn_bus[31:0]	Yes	Yes	T2,T40,T45	Yes	T2,T18,T40	OUTPUT
edn_o[4].edn_fips	Yes	Yes	T2,T40,T47	Yes	T2,T40,T45	OUTPUT
edn_o[4].edn_ack	Yes	Yes	T2,T18,T40	Yes	T2,T18,T40	OUTPUT
edn_o[5].edn_bus[31:0]	Yes	Yes	T12,T41,T44	Yes	T12,T41,T40	OUTPUT
edn_o[5].edn_fips	Yes	Yes	T45,T48,T49	Yes	T41,T40,T44	OUTPUT
edn_o[5].edn_ack	Yes	Yes	T12,T41,T40	Yes	T12,T41,T40	OUTPUT
edn_o[6].edn_bus[31:0]	Yes	Yes	T21,T50,T51	Yes	T21,T43,T50	OUTPUT
edn_o[6].edn_fips	Yes	Yes	T43,T52,T48	Yes	T21,T42,T43	OUTPUT
edn_o[6].edn_ack	Yes	Yes	T21,T42,T43	Yes	T21,T42,T43	OUTPUT
csrng_cmd_o.genbits_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_bus[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_i.genbits_bus[127:0]	Yes	Yes	T1,T2,T21	Yes	T1,T2,T21	INPUT
csrng_cmd_i.genbits_fips	Yes	Yes	T1,T2,T21	Yes	T1,T2,T21	INPUT
csrng_cmd_i.genbits_valid	Yes	Yes	T1,T2,T21	Yes	T1,T2,T21	INPUT
csrng_cmd_i.csrng_rsp_sts[2:0]	Yes	Yes	T8,T16,T29	Yes	T8,T16,T29	INPUT
csrng_cmd_i.csrng_rsp_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_req_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T20,T23,T8	Yes	T20,T23,T8	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T3,T20,T4	Yes	T3,T20,T4	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T20,T23,T8	Yes	T20,T23,T8	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T3,T20,T4	Yes	T3,T20,T4	OUTPUT
intr_edn_cmd_req_done_o	Yes	Yes	T1,T37,T38	Yes	T1,T37,T38	OUTPUT
intr_edn_fatal_err_o	Yes	Yes	T1,T22,T12	Yes	T1,T22,T12	OUTPUT

*Tests covering at least one bit in the range

---

Assert Coverage for Module : edn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	47	47	100.00	47	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	47	47	100.00	47	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxKnownO_A	190590014	190422050	0	0
CsrngAppIfOut_A	190590014	190422050	0	0
FpvSecCmCntAlertCheck_A	190590014	115	0	0
FpvSecCmGenCmdFifoRptrCheck_A	190590014	70	0	0
FpvSecCmGenCmdFifoWptrCheck_A	190590014	70	0	0
FpvSecCmMainFsmCheck_A	190590014	70	0	0
FpvSecCmRegWeOnehotCheck_A	190590014	70	0	0
FpvSecCmResCmdFifoRptrCheck_A	190590014	70	0	0
FpvSecCmResCmdFifoWptrCheck_A	190590014	70	0	0
IntrEdnCmdReqDoneKnownO_A	190590014	190422050	0	0
TlAReadyKnownO_A	190590014	190422050	0	0
TlDValidKnownO_A	190590014	190422050	0	0
gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A	190590014	70	0	0
gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A	190590014	70	0	0
gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A	190590014	70	0	0
gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A	190590014	70	0	0
gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A	190590014	70	0	0
gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A	190590014	70	0	0
gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A	190590014	70	0	0
gen_edn_if_asserts[0].EdnDataStableDisable_A	190590014	558107	0	322
gen_edn_if_asserts[0].EdnDataStable_A	190590014	25051	0	332
gen_edn_if_asserts[0].EdnEndPointOut_A	190590014	190422050	0	0
gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A	190590014	145455	0	0
gen_edn_if_asserts[1].EdnDataStableDisable_A	190590014	558107	0	322
gen_edn_if_asserts[1].EdnDataStable_A	190590014	5521	0	117
gen_edn_if_asserts[1].EdnEndPointOut_A	190590014	190422050	0	0
gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A	190590014	145455	0	0
gen_edn_if_asserts[2].EdnDataStableDisable_A	190590014	558107	0	322
gen_edn_if_asserts[2].EdnDataStable_A	190590014	4421	0	118
gen_edn_if_asserts[2].EdnEndPointOut_A	190590014	190422050	0	0
gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A	190590014	145455	0	0
gen_edn_if_asserts[3].EdnDataStableDisable_A	190590014	558107	0	322
gen_edn_if_asserts[3].EdnDataStable_A	190590014	53015	0	98
gen_edn_if_asserts[3].EdnEndPointOut_A	190590014	190422050	0	0
gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A	190590014	145455	0	0
gen_edn_if_asserts[4].EdnDataStableDisable_A	190590014	558107	0	322
gen_edn_if_asserts[4].EdnDataStable_A	190590014	3512	0	101
gen_edn_if_asserts[4].EdnEndPointOut_A	190590014	190422050	0	0
gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A	190590014	145455	0	0
gen_edn_if_asserts[5].EdnDataStableDisable_A	190590014	558107	0	322
gen_edn_if_asserts[5].EdnDataStable_A	190590014	2917	0	70
gen_edn_if_asserts[5].EdnEndPointOut_A	190590014	190422050	0	0
gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A	190590014	145455	0	0
gen_edn_if_asserts[6].EdnDataStableDisable_A	190590014	558107	0	322
gen_edn_if_asserts[6].EdnDataStable_A	190590014	5722	0	77
gen_edn_if_asserts[6].EdnEndPointOut_A	190590014	190422050	0	0
gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A	190590014	145455	0	0

AlertTxKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	190590014	190422050	0	0
T1	162132	162118	0	0
T2	2723	2646	0	0
T3	2592	2463	0	0
T4	3000	2879	0	0
T7	2286	2209	0	0
T12	1278	1164	0	0
T20	1434	1366	0	0
T21	3112	3041	0	0
T22	2176	2004	0	0
T23	1031	937	0	0

CsrngAppIfOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	190590014	190422050	0	0
T1	162132	162118	0	0
T2	2723	2646	0	0
T3	2592	2463	0	0
T4	3000	2879	0	0
T7	2286	2209	0	0
T12	1278	1164	0	0
T20	1434	1366	0	0
T21	3112	3041	0	0
T22	2176	2004	0	0
T23	1031	937	0	0

FpvSecCmCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	190590014	115	0	0
T3	2592	1	0	0
T4	3000	1	0	0
T6	0	1	0	0
T7	2286	0	0	0
T8	2243	0	0	0
T12	1278	1	0	0
T13	0	20	0	0
T14	0	10	0	0
T20	1434	0	0	0
T21	3112	0	0	0
T22	2176	0	0	0
T23	1031	0	0	0
T27	2431	0	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0

FpvSecCmGenCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	190590014	70	0	0
T13	42656	20	0	0
T14	0	10	0	0
T15	0	10	0	0
T57	0	10	0	0
T58	0	20	0	0
T59	1877	0	0	0
T60	821	0	0	0
T61	447269	0	0	0
T62	3545	0	0	0
T63	1543	0	0	0
T64	3976	0	0	0
T65	2952	0	0	0
T66	5258	0	0	0
T67	910	0	0	0

FpvSecCmGenCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	190590014	70	0	0
T13	42656	20	0	0
T14	0	10	0	0
T15	0	10	0	0
T57	0	10	0	0
T58	0	20	0	0
T59	1877	0	0	0
T60	821	0	0	0
T61	447269	0	0	0
T62	3545	0	0	0
T63	1543	0	0	0
T64	3976	0	0	0
T65	2952	0	0	0
T66	5258	0	0	0
T67	910	0	0	0

FpvSecCmMainFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	190590014	70	0	0
T13	42656	20	0	0
T14	0	10	0	0
T15	0	10	0	0
T57	0	10	0	0
T58	0	20	0	0
T59	1877	0	0	0
T60	821	0	0	0
T61	447269	0	0	0
T62	3545	0	0	0
T63	1543	0	0	0
T64	3976	0	0	0
T65	2952	0	0	0
T66	5258	0	0	0
T67	910	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	190590014	70	0	0
T13	42656	20	0	0
T14	0	10	0	0
T15	0	10	0	0
T57	0	10	0	0
T58	0	20	0	0
T59	1877	0	0	0
T60	821	0	0	0
T61	447269	0	0	0
T62	3545	0	0	0
T63	1543	0	0	0
T64	3976	0	0	0
T65	2952	0	0	0
T66	5258	0	0	0
T67	910	0	0	0

FpvSecCmResCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	190590014	70	0	0
T13	42656	20	0	0
T14	0	10	0	0
T15	0	10	0	0
T57	0	10	0	0
T58	0	20	0	0
T59	1877	0	0	0
T60	821	0	0	0
T61	447269	0	0	0
T62	3545	0	0	0
T63	1543	0	0	0
T64	3976	0	0	0
T65	2952	0	0	0
T66	5258	0	0	0
T67	910	0	0	0

FpvSecCmResCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	190590014	70	0	0
T13	42656	20	0	0
T14	0	10	0	0
T15	0	10	0	0
T57	0	10	0	0
T58	0	20	0	0
T59	1877	0	0	0
T60	821	0	0	0
T61	447269	0	0	0
T62	3545	0	0	0
T63	1543	0	0	0
T64	3976	0	0	0
T65	2952	0	0	0
T66	5258	0	0	0
T67	910	0	0	0

IntrEdnCmdReqDoneKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	190590014	190422050	0	0
T1	162132	162118	0	0
T2	2723	2646	0	0
T3	2592	2463	0	0
T4	3000	2879	0	0
T7	2286	2209	0	0
T12	1278	1164	0	0
T20	1434	1366	0	0
T21	3112	3041	0	0
T22	2176	2004	0	0
T23	1031	937	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	190590014	190422050	0	0
T1	162132	162118	0	0
T2	2723	2646	0	0
T3	2592	2463	0	0
T4	3000	2879	0	0
T7	2286	2209	0	0
T12	1278	1164	0	0
T20	1434	1366	0	0
T21	3112	3041	0	0
T22	2176	2004	0	0
T23	1031	937	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	190590014	190422050	0	0
T1	162132	162118	0	0
T2	2723	2646	0	0
T3	2592	2463	0	0
T4	3000	2879	0	0
T7	2286	2209	0	0
T12	1278	1164	0	0
T20	1434	1366	0	0
T21	3112	3041	0	0
T22	2176	2004	0	0
T23	1031	937	0	0

gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	190590014	70	0	0
T13	42656	20	0	0
T14	0	10	0	0
T15	0	10	0	0
T57	0	10	0	0
T58	0	20	0	0
T59	1877	0	0	0
T60	821	0	0	0
T61	447269	0	0	0
T62	3545	0	0	0
T63	1543	0	0	0
T64	3976	0	0	0
T65	2952	0	0	0
T66	5258	0	0	0
T67	910	0	0	0

gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	190590014	70	0	0
T13	42656	20	0	0
T14	0	10	0	0
T15	0	10	0	0
T57	0	10	0	0
T58	0	20	0	0
T59	1877	0	0	0
T60	821	0	0	0
T61	447269	0	0	0
T62	3545	0	0	0
T63	1543	0	0	0
T64	3976	0	0	0
T65	2952	0	0	0
T66	5258	0	0	0
T67	910	0	0	0

gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	190590014	70	0	0
T13	42656	20	0	0
T14	0	10	0	0
T15	0	10	0	0
T57	0	10	0	0
T58	0	20	0	0
T59	1877	0	0	0
T60	821	0	0	0
T61	447269	0	0	0
T62	3545	0	0	0
T63	1543	0	0	0
T64	3976	0	0	0
T65	2952	0	0	0
T66	5258	0	0	0
T67	910	0	0	0

gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	190590014	70	0	0
T13	42656	20	0	0
T14	0	10	0	0
T15	0	10	0	0
T57	0	10	0	0
T58	0	20	0	0
T59	1877	0	0	0
T60	821	0	0	0
T61	447269	0	0	0
T62	3545	0	0	0
T63	1543	0	0	0
T64	3976	0	0	0
T65	2952	0	0	0
T66	5258	0	0	0
T67	910	0	0	0

gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	190590014	70	0	0
T13	42656	20	0	0
T14	0	10	0	0
T15	0	10	0	0
T57	0	10	0	0
T58	0	20	0	0
T59	1877	0	0	0
T60	821	0	0	0
T61	447269	0	0	0
T62	3545	0	0	0
T63	1543	0	0	0
T64	3976	0	0	0
T65	2952	0	0	0
T66	5258	0	0	0
T67	910	0	0	0

gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	190590014	70	0	0
T13	42656	20	0	0
T14	0	10	0	0
T15	0	10	0	0
T57	0	10	0	0
T58	0	20	0	0
T59	1877	0	0	0
T60	821	0	0	0
T61	447269	0	0	0
T62	3545	0	0	0
T63	1543	0	0	0
T64	3976	0	0	0
T65	2952	0	0	0
T66	5258	0	0	0
T67	910	0	0	0

gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	190590014	70	0	0
T13	42656	20	0	0
T14	0	10	0	0
T15	0	10	0	0
T57	0	10	0	0
T58	0	20	0	0
T59	1877	0	0	0
T60	821	0	0	0
T61	447269	0	0	0
T62	3545	0	0	0
T63	1543	0	0	0
T64	3976	0	0	0
T65	2952	0	0	0
T66	5258	0	0	0
T67	910	0	0	0

gen_edn_if_asserts[0].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	190590014	558107	0	322
T1	162132	1560	0	2
T2	2723	16	0	0
T3	2592	1662	0	0
T4	3000	1196	0	0
T7	2286	238	0	0
T12	1278	548	0	0
T17	0	0	0	2
T20	1434	1364	0	2
T21	3112	31	0	0
T22	2176	1065	0	0
T23	1031	935	0	2
T37	0	0	0	2
T38	0	0	0	2
T42	0	0	0	2
T68	0	0	0	2
T69	0	0	0	2
T70	0	0	0	2

gen_edn_if_asserts[0].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	190590014	25051	0	332
T1	162132	21	0	0
T2	2723	0	0	0
T3	2592	0	0	0
T4	3000	0	0	0
T7	2286	60	0	1
T8	0	4	0	1
T9	0	32	0	1
T12	1278	0	0	0
T16	0	0	0	1
T19	0	585	0	1
T20	1434	0	0	0
T21	3112	17	0	1
T22	2176	0	0	0
T23	1031	0	0	0
T27	0	76	0	1
T37	0	36	0	0
T38	0	32	0	0
T71	0	3	0	1
T72	0	0	0	1
T73	0	0	0	1

gen_edn_if_asserts[0].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	190590014	190422050	0	0
T1	162132	162118	0	0
T2	2723	2646	0	0
T3	2592	2463	0	0
T4	3000	2879	0	0
T7	2286	2209	0	0
T12	1278	1164	0	0
T20	1434	1366	0	0
T21	3112	3041	0	0
T22	2176	2004	0	0
T23	1031	937	0	0

gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	190590014	145455	0	0
T3	2592	1173	0	0
T4	3000	1162	0	0
T5	0	402	0	0
T6	0	354	0	0
T7	2286	0	0	0
T8	2243	0	0	0
T12	1278	639	0	0
T20	1434	0	0	0
T21	3112	0	0	0
T22	2176	1108	0	0
T23	1031	0	0	0
T27	2431	0	0	0
T29	0	592	0	0
T74	0	617	0	0
T75	0	626	0	0
T76	0	389	0	0

gen_edn_if_asserts[1].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	190590014	558107	0	322
T1	162132	1560	0	2
T2	2723	16	0	0
T3	2592	1662	0	0
T4	3000	1196	0	0
T7	2286	238	0	0
T12	1278	548	0	0
T17	0	0	0	2
T20	1434	1364	0	2
T21	3112	31	0	0
T22	2176	1065	0	0
T23	1031	935	0	2
T37	0	0	0	2
T38	0	0	0	2
T42	0	0	0	2
T68	0	0	0	2
T69	0	0	0	2
T70	0	0	0	2

gen_edn_if_asserts[1].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	190590014	5521	0	117
T7	2286	0	0	0
T8	2243	0	0	0
T9	2164	0	0	0
T10	0	0	0	1
T12	1278	0	0	0
T21	3112	41	0	1
T22	2176	0	0	0
T23	1031	0	0	0
T27	2431	0	0	0
T37	899152	0	0	0
T39	0	387	0	1
T40	0	3	0	1
T44	0	45	0	1
T45	0	18	0	1
T46	0	3	0	1
T52	0	3	0	1
T71	1676	0	0	0
T77	0	8	0	1
T78	0	4	0	0
T79	0	3	0	1

gen_edn_if_asserts[1].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	190590014	190422050	0	0
T1	162132	162118	0	0
T2	2723	2646	0	0
T3	2592	2463	0	0
T4	3000	2879	0	0
T7	2286	2209	0	0
T12	1278	1164	0	0
T20	1434	1366	0	0
T21	3112	3041	0	0
T22	2176	2004	0	0
T23	1031	937	0	0

gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	190590014	145455	0	0
T3	2592	1173	0	0
T4	3000	1162	0	0
T5	0	402	0	0
T6	0	354	0	0
T7	2286	0	0	0
T8	2243	0	0	0
T12	1278	639	0	0
T20	1434	0	0	0
T21	3112	0	0	0
T22	2176	1108	0	0
T23	1031	0	0	0
T27	2431	0	0	0
T29	0	592	0	0
T74	0	617	0	0
T75	0	626	0	0
T76	0	389	0	0

gen_edn_if_asserts[2].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	190590014	558107	0	322
T1	162132	1560	0	2
T2	2723	16	0	0
T3	2592	1662	0	0
T4	3000	1196	0	0
T7	2286	238	0	0
T12	1278	548	0	0
T17	0	0	0	2
T20	1434	1364	0	2
T21	3112	31	0	0
T22	2176	1065	0	0
T23	1031	935	0	2
T37	0	0	0	2
T38	0	0	0	2
T42	0	0	0	2
T68	0	0	0	2
T69	0	0	0	2
T70	0	0	0	2

gen_edn_if_asserts[2].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	190590014	4421	0	118
T2	2723	7	0	1
T3	2592	0	0	0
T4	3000	0	0	0
T7	2286	0	0	0
T10	0	0	0	1
T12	1278	0	0	0
T17	0	4	0	0
T20	1434	0	0	0
T21	3112	47	0	1
T22	2176	1	0	0
T23	1031	0	0	0
T27	2431	0	0	0
T40	0	3	0	1
T44	0	61	0	1
T45	0	40	0	1
T47	0	19	0	1
T52	0	3	0	1
T80	0	4	0	0
T81	0	0	0	1
T82	0	0	0	1

gen_edn_if_asserts[2].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	190590014	190422050	0	0
T1	162132	162118	0	0
T2	2723	2646	0	0
T3	2592	2463	0	0
T4	3000	2879	0	0
T7	2286	2209	0	0
T12	1278	1164	0	0
T20	1434	1366	0	0
T21	3112	3041	0	0
T22	2176	2004	0	0
T23	1031	937	0	0

gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	190590014	145455	0	0
T3	2592	1173	0	0
T4	3000	1162	0	0
T5	0	402	0	0
T6	0	354	0	0
T7	2286	0	0	0
T8	2243	0	0	0
T12	1278	639	0	0
T20	1434	0	0	0
T21	3112	0	0	0
T22	2176	1108	0	0
T23	1031	0	0	0
T27	2431	0	0	0
T29	0	592	0	0
T74	0	617	0	0
T75	0	626	0	0
T76	0	389	0	0

gen_edn_if_asserts[3].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	190590014	558107	0	322
T1	162132	1560	0	2
T2	2723	16	0	0
T3	2592	1662	0	0
T4	3000	1196	0	0
T7	2286	238	0	0
T12	1278	548	0	0
T17	0	0	0	2
T20	1434	1364	0	2
T21	3112	31	0	0
T22	2176	1065	0	0
T23	1031	935	0	2
T37	0	0	0	2
T38	0	0	0	2
T42	0	0	0	2
T68	0	0	0	2
T69	0	0	0	2
T70	0	0	0	2

gen_edn_if_asserts[3].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	190590014	53015	0	98
T2	2723	3	0	1
T3	2592	0	0	0
T4	3000	0	0	0
T7	2286	0	0	0
T8	0	4	0	0
T12	1278	0	0	0
T20	1434	0	0	0
T21	3112	43	0	1
T22	2176	0	0	0
T23	1031	0	0	0
T27	2431	0	0	0
T28	0	4	0	1
T40	0	52	0	1
T42	0	4	0	0
T44	0	3	0	1
T45	0	3	0	1
T46	0	0	0	1
T48	0	0	0	1
T70	0	4	0	0
T83	0	4	0	0
T84	0	0	0	1
T85	0	0	0	1

gen_edn_if_asserts[3].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	190590014	190422050	0	0
T1	162132	162118	0	0
T2	2723	2646	0	0
T3	2592	2463	0	0
T4	3000	2879	0	0
T7	2286	2209	0	0
T12	1278	1164	0	0
T20	1434	1366	0	0
T21	3112	3041	0	0
T22	2176	2004	0	0
T23	1031	937	0	0

gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	190590014	145455	0	0
T3	2592	1173	0	0
T4	3000	1162	0	0
T5	0	402	0	0
T6	0	354	0	0
T7	2286	0	0	0
T8	2243	0	0	0
T12	1278	639	0	0
T20	1434	0	0	0
T21	3112	0	0	0
T22	2176	1108	0	0
T23	1031	0	0	0
T27	2431	0	0	0
T29	0	592	0	0
T74	0	617	0	0
T75	0	626	0	0
T76	0	389	0	0

gen_edn_if_asserts[4].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	190590014	558107	0	322
T1	162132	1560	0	2
T2	2723	16	0	0
T3	2592	1662	0	0
T4	3000	1196	0	0
T7	2286	238	0	0
T12	1278	548	0	0
T17	0	0	0	2
T20	1434	1364	0	2
T21	3112	31	0	0
T22	2176	1065	0	0
T23	1031	935	0	2
T37	0	0	0	2
T38	0	0	0	2
T42	0	0	0	2
T68	0	0	0	2
T69	0	0	0	2
T70	0	0	0	2

gen_edn_if_asserts[4].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	190590014	3512	0	101
T2	2723	36	0	1
T3	2592	0	0	0
T4	3000	0	0	0
T7	2286	0	0	0
T12	1278	0	0	0
T18	0	4	0	0
T20	1434	0	0	0
T21	3112	0	0	0
T22	2176	0	0	0
T23	1031	0	0	0
T27	2431	0	0	0
T40	0	20	0	1
T45	0	3	0	1
T47	0	44	0	1
T48	0	3	0	1
T49	0	0	0	1
T85	0	4	0	0
T86	0	3	0	1
T87	0	1	0	0
T88	0	7	0	1
T89	0	0	0	1
T90	0	0	0	1

gen_edn_if_asserts[4].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	190590014	190422050	0	0
T1	162132	162118	0	0
T2	2723	2646	0	0
T3	2592	2463	0	0
T4	3000	2879	0	0
T7	2286	2209	0	0
T12	1278	1164	0	0
T20	1434	1366	0	0
T21	3112	3041	0	0
T22	2176	2004	0	0
T23	1031	937	0	0

gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	190590014	145455	0	0
T3	2592	1173	0	0
T4	3000	1162	0	0
T5	0	402	0	0
T6	0	354	0	0
T7	2286	0	0	0
T8	2243	0	0	0
T12	1278	639	0	0
T20	1434	0	0	0
T21	3112	0	0	0
T22	2176	1108	0	0
T23	1031	0	0	0
T27	2431	0	0	0
T29	0	592	0	0
T74	0	617	0	0
T75	0	626	0	0
T76	0	389	0	0

gen_edn_if_asserts[5].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	190590014	558107	0	322
T1	162132	1560	0	2
T2	2723	16	0	0
T3	2592	1662	0	0
T4	3000	1196	0	0
T7	2286	238	0	0
T12	1278	548	0	0
T17	0	0	0	2
T20	1434	1364	0	2
T21	3112	31	0	0
T22	2176	1065	0	0
T23	1031	935	0	2
T37	0	0	0	2
T38	0	0	0	2
T42	0	0	0	2
T68	0	0	0	2
T69	0	0	0	2
T70	0	0	0	2

gen_edn_if_asserts[5].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	190590014	2917	0	70
T5	1470	0	0	0
T7	2286	0	0	0
T8	2243	0	0	0
T9	2164	0	0	0
T12	1278	1	0	0
T19	5056	0	0	0
T27	2431	0	0	0
T37	899152	0	0	0
T38	441329	0	0	0
T40	0	3	0	1
T41	0	4	0	0
T44	0	3	0	1
T45	0	64	0	1
T46	0	3	0	1
T48	0	32	0	1
T49	0	0	0	1
T71	1676	0	0	0
T84	0	3	0	1
T87	0	4	0	0
T89	0	0	0	1
T90	0	0	0	1
T91	0	1	0	0
T92	0	0	0	1

gen_edn_if_asserts[5].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	190590014	190422050	0	0
T1	162132	162118	0	0
T2	2723	2646	0	0
T3	2592	2463	0	0
T4	3000	2879	0	0
T7	2286	2209	0	0
T12	1278	1164	0	0
T20	1434	1366	0	0
T21	3112	3041	0	0
T22	2176	2004	0	0
T23	1031	937	0	0

gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	190590014	145455	0	0
T3	2592	1173	0	0
T4	3000	1162	0	0
T5	0	402	0	0
T6	0	354	0	0
T7	2286	0	0	0
T8	2243	0	0	0
T12	1278	639	0	0
T20	1434	0	0	0
T21	3112	0	0	0
T22	2176	1108	0	0
T23	1031	0	0	0
T27	2431	0	0	0
T29	0	592	0	0
T74	0	617	0	0
T75	0	626	0	0
T76	0	389	0	0

gen_edn_if_asserts[6].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	190590014	558107	0	322
T1	162132	1560	0	2
T2	2723	16	0	0
T3	2592	1662	0	0
T4	3000	1196	0	0
T7	2286	238	0	0
T12	1278	548	0	0
T17	0	0	0	2
T20	1434	1364	0	2
T21	3112	31	0	0
T22	2176	1065	0	0
T23	1031	935	0	2
T37	0	0	0	2
T38	0	0	0	2
T42	0	0	0	2
T68	0	0	0	2
T69	0	0	0	2
T70	0	0	0	2

gen_edn_if_asserts[6].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	190590014	5722	0	77
T7	2286	0	0	0
T8	2243	0	0	0
T9	2164	0	0	0
T12	1278	0	0	0
T21	3112	3	0	1
T22	2176	0	0	0
T23	1031	0	0	0
T27	2431	0	0	0
T37	899152	0	0	0
T42	0	1	0	0
T43	0	3	0	1
T48	0	783	0	1
T49	0	35	0	1
T50	0	4	0	0
T51	0	3	0	1
T52	0	22	0	1
T65	0	0	0	1
T71	1676	0	0	0
T89	0	22	0	1
T91	0	4	0	0
T93	0	0	0	1
T94	0	0	0	1

gen_edn_if_asserts[6].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	190590014	190422050	0	0
T1	162132	162118	0	0
T2	2723	2646	0	0
T3	2592	2463	0	0
T4	3000	2879	0	0
T7	2286	2209	0	0
T12	1278	1164	0	0
T20	1434	1366	0	0
T21	3112	3041	0	0
T22	2176	2004	0	0
T23	1031	937	0	0

gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	190590014	145455	0	0
T3	2592	1173	0	0
T4	3000	1162	0	0
T5	0	402	0	0
T6	0	354	0	0
T7	2286	0	0	0
T8	2243	0	0	0
T12	1278	639	0	0
T20	1434	0	0	0
T21	3112	0	0	0
T22	2176	1108	0	0
T23	1031	0	0	0
T27	2431	0	0	0
T29	0	592	0	0
T74	0	617	0	0
T75	0	626	0	0
T76	0	389	0	0