Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44		83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	191153561	8202251	0	0
boot_gen_cmd_rd_A	191153561	72225	0	0
boot_ins_cmd_rd_A	191153561	82515	0	0
ctrl_rd_A	191153561	71079	0	0
err_code_test_rd_A	191153561	82968	0	0
intr_enable_rd_A	191153561	80005	0	0
max_num_reqs_between_reseeds_rd_A	191153561	73078	0	0
regwen_rd_A	191153561	84358	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191153561	8202251	0	0
T1	162132	63926	0	0
T2	2723	0	0	0
T3	2592	0	0	0
T4	3000	0	0	0
T7	2286	0	0	0
T12	1278	0	0	0
T20	1434	0	0	0
T21	3112	0	0	0
T22	2176	0	0	0
T23	1031	0	0	0
T37	0	51068	0	0
T38	0	176479	0	0
T61	0	249124	0	0
T160	0	85597	0	0
T161	0	399623	0	0
T164	0	327552	0	0
T201	0	194457	0	0
T202	0	120058	0	0
T203	0	77431	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191153561	72225	0	0
T13	42656	0	0	0
T59	1877	0	0	0
T60	821	0	0	0
T61	447269	0	0	0
T62	3545	0	0	0
T63	1543	0	0	0
T64	3976	0	0	0
T65	2952	0	0	0
T120	759	0	0	0
T164	941701	9303	0	0
T203	0	2355	0	0
T204	0	7071	0	0
T205	0	7575	0	0
T206	0	5010	0	0
T207	0	6632	0	0
T208	0	1661	0	0
T209	0	1309	0	0
T210	0	5159	0	0
T211	0	4512	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191153561	82515	0	0
T13	42656	0	0	0
T59	1877	0	0	0
T60	821	0	0	0
T61	447269	0	0	0
T62	3545	0	0	0
T63	1543	0	0	0
T64	3976	0	0	0
T65	2952	0	0	0
T120	759	0	0	0
T164	941701	11164	0	0
T203	0	2673	0	0
T204	0	8245	0	0
T205	0	8090	0	0
T206	0	5771	0	0
T207	0	7706	0	0
T208	0	2032	0	0
T209	0	1885	0	0
T210	0	5693	0	0
T211	0	4954	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191153561	71079	0	0
T13	42656	0	0	0
T24	0	6	0	0
T59	1877	0	0	0
T60	821	0	0	0
T61	447269	0	0	0
T62	3545	0	0	0
T63	1543	0	0	0
T64	3976	0	0	0
T65	2952	0	0	0
T120	759	0	0	0
T164	941701	9567	0	0
T203	0	2239	0	0
T204	0	6683	0	0
T205	0	7282	0	0
T206	0	4930	0	0
T207	0	6546	0	0
T208	0	1469	0	0
T212	0	1	0	0
T213	0	3	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191153561	82968	0	0
T13	42656	0	0	0
T59	1877	0	0	0
T60	821	0	0	0
T61	447269	0	0	0
T62	3545	0	0	0
T63	1543	0	0	0
T64	3976	0	0	0
T65	2952	0	0	0
T120	759	0	0	0
T164	941701	11016	0	0
T203	0	2642	0	0
T204	0	7934	0	0
T205	0	8149	0	0
T206	0	5864	0	0
T207	0	7984	0	0
T208	0	1694	0	0
T209	0	1778	0	0
T210	0	5708	0	0
T211	0	5049	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191153561	80005	0	0
T45	2642	0	0	0
T46	218610	0	0	0
T50	1947	0	0	0
T75	1151	0	0	0
T76	751	0	0	0
T83	2616	0	0	0
T129	1820	0	0	0
T163	13984	70	0	0
T164	0	9556	0	0
T203	0	2769	0	0
T204	0	7122	0	0
T205	0	7643	0	0
T206	0	5706	0	0
T207	0	7468	0	0
T208	0	1903	0	0
T213	0	54	0	0
T214	0	34	0	0
T215	3918	0	0	0
T216	1730	0	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191153561	73078	0	0
T13	42656	0	0	0
T59	1877	0	0	0
T60	821	0	0	0
T61	447269	0	0	0
T62	3545	0	0	0
T63	1543	0	0	0
T64	3976	0	0	0
T65	2952	0	0	0
T120	759	0	0	0
T164	941701	9693	0	0
T203	0	2350	0	0
T204	0	6687	0	0
T205	0	6889	0	0
T206	0	5043	0	0
T207	0	6859	0	0
T208	0	1568	0	0
T209	0	1537	0	0
T210	0	4892	0	0
T211	0	4136	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191153561	84358	0	0
T13	42656	0	0	0
T59	1877	0	0	0
T60	821	0	0	0
T61	447269	0	0	0
T62	3545	0	0	0
T63	1543	0	0	0
T64	3976	0	0	0
T65	2952	0	0	0
T120	759	0	0	0
T164	941701	11233	0	0
T203	0	2869	0	0
T204	0	7896	0	0
T205	0	8310	0	0
T206	0	5481	0	0
T207	0	8339	0	0
T208	0	1866	0	0
T209	0	1802	0	0
T210	0	6393	0	0
T211	0	4563	0	0