Unified Coverage Report :: Module :: edn

Module : edn

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	94.44		83.33	100.00			100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.97	98.24	93.80	97.07	84.30	96.62	99.77

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
edn_csr_assert	100.00						100.00
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_edn_core	92.95	99.92	92.46	82.84	84.30	99.28	98.88
u_edn_cov_if	25.00	50.00	0.00
u_reg	96.95	95.02	97.57	100.00		92.16	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Cond Coverage for Module : edn

	Total	Covered	Percent
Conditions	6	5	83.33
Logical	6	5	83.33
Non-Logical	0	0
Event	0	0

 LINE       98
 EXPRESSION (alert[0] || intg_err_alert[0])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T10,T30,T31

 LINE       98
 EXPRESSION (alert[1] || intg_err_alert[1])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T16,T17,T18
1	0	Covered	T3,T34,T37

---

Toggle Coverage for Module : edn

	Total	Covered	Percent
Totals	69	69	100.00
Total Bits	1172	1172	100.00
Total Bits 0->1	586	586	100.00
Total Bits 1->0	586	586	100.00

Ports	69	69	100.00
Port Bits	1172	1172	100.00
Port Bits 0->1	586	586	100.00
Port Bits 1->0	586	586	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T3,T4,T5	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T3,T4,T9	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T3,T4,T9	Yes	T3,T4,T9	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T4,T5,T24	Yes	T4,T5,T24	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i[0].edn_req	Yes	Yes	T2,T4,T9	Yes	T2,T4,T9	INPUT
edn_i[1].edn_req	Yes	Yes	T1,T10,T19	Yes	T1,T10,T19	INPUT
edn_i[2].edn_req	Yes	Yes	T19,T29,T42	Yes	T19,T29,T42	INPUT
edn_i[3].edn_req	Yes	Yes	T1,T29,T30	Yes	T1,T29,T30	INPUT
edn_i[4].edn_req	Yes	Yes	T1,T3,T29	Yes	T1,T3,T29	INPUT
edn_i[5].edn_req	Yes	Yes	T1,T29,T43	Yes	T1,T29,T43	INPUT
edn_i[6].edn_req	Yes	Yes	T29,T21,T42	Yes	T29,T21,T42	INPUT
edn_o[0].edn_bus[31:0]	Yes	Yes	T2,T4,T9	Yes	T2,T4,T9	OUTPUT
edn_o[0].edn_fips	Yes	Yes	T2,T4,T9	Yes	T2,T4,T9	OUTPUT
edn_o[0].edn_ack	Yes	Yes	T2,T4,T9	Yes	T2,T4,T9	OUTPUT
edn_o[1].edn_bus[31:0]	Yes	Yes	T1,T10,T19	Yes	T1,T10,T19	OUTPUT
edn_o[1].edn_fips	Yes	Yes	T19,T44,T45	Yes	T1,T10,T19	OUTPUT
edn_o[1].edn_ack	Yes	Yes	T1,T10,T19	Yes	T1,T10,T19	OUTPUT
edn_o[2].edn_bus[31:0]	Yes	Yes	T19,T42,T44	Yes	T19,T29,T42	OUTPUT
edn_o[2].edn_fips	Yes	Yes	T42,T45,T46	Yes	T42,T44,T45	OUTPUT
edn_o[2].edn_ack	Yes	Yes	T19,T29,T42	Yes	T19,T29,T42	OUTPUT
edn_o[3].edn_bus[31:0]	Yes	Yes	T1,T29,T30	Yes	T1,T29,T30	OUTPUT
edn_o[3].edn_fips	Yes	Yes	T1,T42,T45	Yes	T1,T29,T42	OUTPUT
edn_o[3].edn_ack	Yes	Yes	T1,T29,T30	Yes	T1,T29,T30	OUTPUT
edn_o[4].edn_bus[31:0]	Yes	Yes	T1,T29,T42	Yes	T1,T29,T42	OUTPUT
edn_o[4].edn_fips	Yes	Yes	T1,T29,T44	Yes	T1,T29,T44	OUTPUT
edn_o[4].edn_ack	Yes	Yes	T1,T29,T42	Yes	T1,T29,T42	OUTPUT
edn_o[5].edn_bus[31:0]	Yes	Yes	T29,T43,T42	Yes	T1,T29,T43	OUTPUT
edn_o[5].edn_fips	Yes	Yes	T42,T47,T48	Yes	T43,T42,T44	OUTPUT
edn_o[5].edn_ack	Yes	Yes	T1,T29,T43	Yes	T1,T29,T43	OUTPUT
edn_o[6].edn_bus[31:0]	Yes	Yes	T42,T44,T48	Yes	T29,T21,T42	OUTPUT
edn_o[6].edn_fips	Yes	Yes	T44,T49,T50	Yes	T21,T44,T49	OUTPUT
edn_o[6].edn_ack	Yes	Yes	T29,T21,T42	Yes	T29,T21,T42	OUTPUT
csrng_cmd_o.genbits_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_bus[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_i.genbits_bus[127:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
csrng_cmd_i.genbits_fips	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
csrng_cmd_i.genbits_valid	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
csrng_cmd_i.csrng_rsp_sts[2:0]	Yes	Yes	T10,T30,T15	Yes	T10,T30,T15	INPUT
csrng_cmd_i.csrng_rsp_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_req_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T22,T10,T30	Yes	T22,T10,T30	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T3,T22,T34	Yes	T3,T22,T34	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T22,T10,T30	Yes	T22,T10,T30	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T3,T22,T34	Yes	T3,T22,T34	OUTPUT
intr_edn_cmd_req_done_o	Yes	Yes	T4,T5,T24	Yes	T4,T5,T24	OUTPUT
intr_edn_fatal_err_o	Yes	Yes	T4,T5,T24	Yes	T4,T5,T24	OUTPUT

*Tests covering at least one bit in the range

---

Assert Coverage for Module : edn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	47	47	100.00	47	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	47	47	100.00	47	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxKnownO_A	237504159	237335563	0	0
CsrngAppIfOut_A	237504159	237335563	0	0
FpvSecCmCntAlertCheck_A	237504159	108	0	0
FpvSecCmGenCmdFifoRptrCheck_A	237504159	70	0	0
FpvSecCmGenCmdFifoWptrCheck_A	237504159	70	0	0
FpvSecCmMainFsmCheck_A	237504159	70	0	0
FpvSecCmRegWeOnehotCheck_A	237504159	70	0	0
FpvSecCmResCmdFifoRptrCheck_A	237504159	70	0	0
FpvSecCmResCmdFifoWptrCheck_A	237504159	70	0	0
IntrEdnCmdReqDoneKnownO_A	237504159	237335563	0	0
TlAReadyKnownO_A	237504159	237335563	0	0
TlDValidKnownO_A	237504159	237335563	0	0
gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A	237504159	70	0	0
gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A	237504159	70	0	0
gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A	237504159	70	0	0
gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A	237504159	70	0	0
gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A	237504159	70	0	0
gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A	237504159	70	0	0
gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A	237504159	70	0	0
gen_edn_if_asserts[0].EdnDataStableDisable_A	237504159	555082	0	332
gen_edn_if_asserts[0].EdnDataStable_A	237504159	23171	0	350
gen_edn_if_asserts[0].EdnEndPointOut_A	237504159	237335563	0	0
gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A	237504159	154485	0	0
gen_edn_if_asserts[1].EdnDataStableDisable_A	237504159	555082	0	332
gen_edn_if_asserts[1].EdnDataStable_A	237504159	3326	0	121
gen_edn_if_asserts[1].EdnEndPointOut_A	237504159	237335563	0	0
gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A	237504159	154485	0	0
gen_edn_if_asserts[2].EdnDataStableDisable_A	237504159	555082	0	332
gen_edn_if_asserts[2].EdnDataStable_A	237504159	3481	0	111
gen_edn_if_asserts[2].EdnEndPointOut_A	237504159	237335563	0	0
gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A	237504159	154485	0	0
gen_edn_if_asserts[3].EdnDataStableDisable_A	237504159	555082	0	332
gen_edn_if_asserts[3].EdnDataStable_A	237504159	6200	0	116
gen_edn_if_asserts[3].EdnEndPointOut_A	237504159	237335563	0	0
gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A	237504159	154485	0	0
gen_edn_if_asserts[4].EdnDataStableDisable_A	237504159	555082	0	332
gen_edn_if_asserts[4].EdnDataStable_A	237504159	3425	0	80
gen_edn_if_asserts[4].EdnEndPointOut_A	237504159	237335563	0	0
gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A	237504159	154485	0	0
gen_edn_if_asserts[5].EdnDataStableDisable_A	237504159	555082	0	332
gen_edn_if_asserts[5].EdnDataStable_A	237504159	2259	0	92
gen_edn_if_asserts[5].EdnEndPointOut_A	237504159	237335563	0	0
gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A	237504159	154485	0	0
gen_edn_if_asserts[6].EdnDataStableDisable_A	237504159	555082	0	332
gen_edn_if_asserts[6].EdnDataStable_A	237504159	3045	0	78
gen_edn_if_asserts[6].EdnEndPointOut_A	237504159	237335563	0	0
gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A	237504159	154485	0	0

AlertTxKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	237504159	237335563	0	0
T1	1915	1862	0	0
T2	4551	4480	0	0
T3	1134	974	0	0
T4	100502	100500	0	0
T5	545957	545946	0	0
T9	4853	4767	0	0
T22	1057	972	0	0
T23	1814	1716	0	0
T24	452281	452265	0	0
T25	2027	1955	0	0

CsrngAppIfOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	237504159	237335563	0	0
T1	1915	1862	0	0
T2	4551	4480	0	0
T3	1134	974	0	0
T4	100502	100500	0	0
T5	545957	545946	0	0
T9	4853	4767	0	0
T22	1057	972	0	0
T23	1814	1716	0	0
T24	452281	452265	0	0
T25	2027	1955	0	0

FpvSecCmCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	237504159	108	0	0
T3	1134	1	0	0
T4	100502	0	0	0
T5	545957	0	0	0
T9	4853	0	0	0
T14	0	1	0	0
T15	0	1	0	0
T16	0	20	0	0
T22	1057	0	0	0
T23	1814	0	0	0
T24	452281	0	0	0
T25	2027	0	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	438279	0	0	0
T58	15006	0	0	0

FpvSecCmGenCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	237504159	70	0	0
T16	46510	20	0	0
T17	0	20	0	0
T18	0	10	0	0
T53	637	0	0	0
T54	2843	0	0	0
T59	0	10	0	0
T60	0	10	0	0
T61	970737	0	0	0
T62	4143	0	0	0
T63	940	0	0	0
T64	2404	0	0	0
T65	1039	0	0	0
T66	292218	0	0	0
T67	5169	0	0	0

FpvSecCmGenCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	237504159	70	0	0
T16	46510	20	0	0
T17	0	20	0	0
T18	0	10	0	0
T53	637	0	0	0
T54	2843	0	0	0
T59	0	10	0	0
T60	0	10	0	0
T61	970737	0	0	0
T62	4143	0	0	0
T63	940	0	0	0
T64	2404	0	0	0
T65	1039	0	0	0
T66	292218	0	0	0
T67	5169	0	0	0

FpvSecCmMainFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	237504159	70	0	0
T16	46510	20	0	0
T17	0	20	0	0
T18	0	10	0	0
T53	637	0	0	0
T54	2843	0	0	0
T59	0	10	0	0
T60	0	10	0	0
T61	970737	0	0	0
T62	4143	0	0	0
T63	940	0	0	0
T64	2404	0	0	0
T65	1039	0	0	0
T66	292218	0	0	0
T67	5169	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	237504159	70	0	0
T16	46510	20	0	0
T17	0	20	0	0
T18	0	10	0	0
T53	637	0	0	0
T54	2843	0	0	0
T59	0	10	0	0
T60	0	10	0	0
T61	970737	0	0	0
T62	4143	0	0	0
T63	940	0	0	0
T64	2404	0	0	0
T65	1039	0	0	0
T66	292218	0	0	0
T67	5169	0	0	0

FpvSecCmResCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	237504159	70	0	0
T16	46510	20	0	0
T17	0	20	0	0
T18	0	10	0	0
T53	637	0	0	0
T54	2843	0	0	0
T59	0	10	0	0
T60	0	10	0	0
T61	970737	0	0	0
T62	4143	0	0	0
T63	940	0	0	0
T64	2404	0	0	0
T65	1039	0	0	0
T66	292218	0	0	0
T67	5169	0	0	0

FpvSecCmResCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	237504159	70	0	0
T16	46510	20	0	0
T17	0	20	0	0
T18	0	10	0	0
T53	637	0	0	0
T54	2843	0	0	0
T59	0	10	0	0
T60	0	10	0	0
T61	970737	0	0	0
T62	4143	0	0	0
T63	940	0	0	0
T64	2404	0	0	0
T65	1039	0	0	0
T66	292218	0	0	0
T67	5169	0	0	0

IntrEdnCmdReqDoneKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	237504159	237335563	0	0
T1	1915	1862	0	0
T2	4551	4480	0	0
T3	1134	974	0	0
T4	100502	100500	0	0
T5	545957	545946	0	0
T9	4853	4767	0	0
T22	1057	972	0	0
T23	1814	1716	0	0
T24	452281	452265	0	0
T25	2027	1955	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	237504159	237335563	0	0
T1	1915	1862	0	0
T2	4551	4480	0	0
T3	1134	974	0	0
T4	100502	100500	0	0
T5	545957	545946	0	0
T9	4853	4767	0	0
T22	1057	972	0	0
T23	1814	1716	0	0
T24	452281	452265	0	0
T25	2027	1955	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	237504159	237335563	0	0
T1	1915	1862	0	0
T2	4551	4480	0	0
T3	1134	974	0	0
T4	100502	100500	0	0
T5	545957	545946	0	0
T9	4853	4767	0	0
T22	1057	972	0	0
T23	1814	1716	0	0
T24	452281	452265	0	0
T25	2027	1955	0	0

gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	237504159	70	0	0
T16	46510	20	0	0
T17	0	20	0	0
T18	0	10	0	0
T53	637	0	0	0
T54	2843	0	0	0
T59	0	10	0	0
T60	0	10	0	0
T61	970737	0	0	0
T62	4143	0	0	0
T63	940	0	0	0
T64	2404	0	0	0
T65	1039	0	0	0
T66	292218	0	0	0
T67	5169	0	0	0

gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	237504159	70	0	0
T16	46510	20	0	0
T17	0	20	0	0
T18	0	10	0	0
T53	637	0	0	0
T54	2843	0	0	0
T59	0	10	0	0
T60	0	10	0	0
T61	970737	0	0	0
T62	4143	0	0	0
T63	940	0	0	0
T64	2404	0	0	0
T65	1039	0	0	0
T66	292218	0	0	0
T67	5169	0	0	0

gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	237504159	70	0	0
T16	46510	20	0	0
T17	0	20	0	0
T18	0	10	0	0
T53	637	0	0	0
T54	2843	0	0	0
T59	0	10	0	0
T60	0	10	0	0
T61	970737	0	0	0
T62	4143	0	0	0
T63	940	0	0	0
T64	2404	0	0	0
T65	1039	0	0	0
T66	292218	0	0	0
T67	5169	0	0	0

gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	237504159	70	0	0
T16	46510	20	0	0
T17	0	20	0	0
T18	0	10	0	0
T53	637	0	0	0
T54	2843	0	0	0
T59	0	10	0	0
T60	0	10	0	0
T61	970737	0	0	0
T62	4143	0	0	0
T63	940	0	0	0
T64	2404	0	0	0
T65	1039	0	0	0
T66	292218	0	0	0
T67	5169	0	0	0

gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	237504159	70	0	0
T16	46510	20	0	0
T17	0	20	0	0
T18	0	10	0	0
T53	637	0	0	0
T54	2843	0	0	0
T59	0	10	0	0
T60	0	10	0	0
T61	970737	0	0	0
T62	4143	0	0	0
T63	940	0	0	0
T64	2404	0	0	0
T65	1039	0	0	0
T66	292218	0	0	0
T67	5169	0	0	0

gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	237504159	70	0	0
T16	46510	20	0	0
T17	0	20	0	0
T18	0	10	0	0
T53	637	0	0	0
T54	2843	0	0	0
T59	0	10	0	0
T60	0	10	0	0
T61	970737	0	0	0
T62	4143	0	0	0
T63	940	0	0	0
T64	2404	0	0	0
T65	1039	0	0	0
T66	292218	0	0	0
T67	5169	0	0	0

gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	237504159	70	0	0
T16	46510	20	0	0
T17	0	20	0	0
T18	0	10	0	0
T53	637	0	0	0
T54	2843	0	0	0
T59	0	10	0	0
T60	0	10	0	0
T61	970737	0	0	0
T62	4143	0	0	0
T63	940	0	0	0
T64	2404	0	0	0
T65	1039	0	0	0
T66	292218	0	0	0
T67	5169	0	0	0

gen_edn_if_asserts[0].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	237504159	555082	0	332
T1	1915	18	0	0
T2	4551	63	0	0
T3	1134	583	0	0
T4	100502	2563	0	2
T5	545957	2017	0	2
T9	4853	206	0	0
T21	0	0	0	2
T22	1057	970	0	2
T23	1814	147	0	0
T24	452281	2819	0	2
T25	2027	52	0	0
T57	0	0	0	2
T68	0	0	0	2
T69	0	0	0	2
T70	0	0	0	2
T71	0	0	0	2

gen_edn_if_asserts[0].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	237504159	23171	0	350
T2	4551	652	0	1
T3	1134	0	0	0
T4	100502	58	0	0
T5	545957	48	0	0
T9	4853	315	0	1
T19	0	0	0	1
T20	0	0	0	1
T22	1057	0	0	0
T23	1814	3	0	1
T24	452281	114	0	0
T25	2027	7	0	1
T31	0	0	0	1
T34	0	1	0	0
T57	438279	159	0	0
T58	0	9	0	0
T72	0	0	0	1
T73	0	0	0	1
T74	0	0	0	1

gen_edn_if_asserts[0].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	237504159	237335563	0	0
T1	1915	1862	0	0
T2	4551	4480	0	0
T3	1134	974	0	0
T4	100502	100500	0	0
T5	545957	545946	0	0
T9	4853	4767	0	0
T22	1057	972	0	0
T23	1814	1716	0	0
T24	452281	452265	0	0
T25	2027	1955	0	0

gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	237504159	154485	0	0
T3	1134	640	0	0
T4	100502	0	0	0
T5	545957	0	0	0
T6	0	1151	0	0
T7	0	631	0	0
T8	0	1072	0	0
T9	4853	0	0	0
T14	0	1135	0	0
T15	0	604	0	0
T22	1057	0	0	0
T23	1814	0	0	0
T24	452281	0	0	0
T25	2027	0	0	0
T34	0	7	0	0
T37	0	1120	0	0
T38	0	1072	0	0
T57	438279	0	0	0
T58	15006	0	0	0
T75	0	645	0	0

gen_edn_if_asserts[1].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	237504159	555082	0	332
T1	1915	18	0	0
T2	4551	63	0	0
T3	1134	583	0	0
T4	100502	2563	0	2
T5	545957	2017	0	2
T9	4853	206	0	0
T21	0	0	0	2
T22	1057	970	0	2
T23	1814	147	0	0
T24	452281	2819	0	2
T25	2027	52	0	0
T57	0	0	0	2
T68	0	0	0	2
T69	0	0	0	2
T70	0	0	0	2
T71	0	0	0	2

gen_edn_if_asserts[1].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	237504159	3326	0	121
T1	1915	5	0	1
T2	4551	0	0	0
T3	1134	0	0	0
T4	100502	0	0	0
T5	545957	0	0	0
T9	4853	0	0	0
T10	0	4	0	1
T19	0	15	0	1
T22	1057	0	0	0
T23	1814	0	0	0
T24	452281	0	0	0
T25	2027	0	0	0
T30	0	4	0	1
T42	0	3	0	1
T44	0	30	0	1
T45	0	31	0	1
T46	0	59	0	1
T76	0	4	0	1
T77	0	3	0	1

gen_edn_if_asserts[1].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	237504159	237335563	0	0
T1	1915	1862	0	0
T2	4551	4480	0	0
T3	1134	974	0	0
T4	100502	100500	0	0
T5	545957	545946	0	0
T9	4853	4767	0	0
T22	1057	972	0	0
T23	1814	1716	0	0
T24	452281	452265	0	0
T25	2027	1955	0	0

gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	237504159	154485	0	0
T3	1134	640	0	0
T4	100502	0	0	0
T5	545957	0	0	0
T6	0	1151	0	0
T7	0	631	0	0
T8	0	1072	0	0
T9	4853	0	0	0
T14	0	1135	0	0
T15	0	604	0	0
T22	1057	0	0	0
T23	1814	0	0	0
T24	452281	0	0	0
T25	2027	0	0	0
T34	0	7	0	0
T37	0	1120	0	0
T38	0	1072	0	0
T57	438279	0	0	0
T58	15006	0	0	0
T75	0	645	0	0

gen_edn_if_asserts[2].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	237504159	555082	0	332
T1	1915	18	0	0
T2	4551	63	0	0
T3	1134	583	0	0
T4	100502	2563	0	2
T5	545957	2017	0	2
T9	4853	206	0	0
T21	0	0	0	2
T22	1057	970	0	2
T23	1814	147	0	0
T24	452281	2819	0	2
T25	2027	52	0	0
T57	0	0	0	2
T68	0	0	0	2
T69	0	0	0	2
T70	0	0	0	2
T71	0	0	0	2

gen_edn_if_asserts[2].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	237504159	3481	0	111
T19	2053	3	0	1
T20	4776	0	0	0
T21	2304	0	0	0
T29	2272	3	0	1
T30	2807	0	0	0
T37	2130	0	0	0
T38	1800	0	0	0
T42	0	17	0	1
T44	0	3	0	1
T45	0	49	0	1
T46	0	42	0	1
T72	12713	0	0	0
T73	1310	0	0	0
T74	981	0	0	0
T76	0	4	0	0
T78	0	4	0	0
T79	0	1	0	0
T80	0	19	0	1
T81	0	0	0	1
T82	0	0	0	1
T83	0	0	0	1

gen_edn_if_asserts[2].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	237504159	237335563	0	0
T1	1915	1862	0	0
T2	4551	4480	0	0
T3	1134	974	0	0
T4	100502	100500	0	0
T5	545957	545946	0	0
T9	4853	4767	0	0
T22	1057	972	0	0
T23	1814	1716	0	0
T24	452281	452265	0	0
T25	2027	1955	0	0

gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	237504159	154485	0	0
T3	1134	640	0	0
T4	100502	0	0	0
T5	545957	0	0	0
T6	0	1151	0	0
T7	0	631	0	0
T8	0	1072	0	0
T9	4853	0	0	0
T14	0	1135	0	0
T15	0	604	0	0
T22	1057	0	0	0
T23	1814	0	0	0
T24	452281	0	0	0
T25	2027	0	0	0
T34	0	7	0	0
T37	0	1120	0	0
T38	0	1072	0	0
T57	438279	0	0	0
T58	15006	0	0	0
T75	0	645	0	0

gen_edn_if_asserts[3].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	237504159	555082	0	332
T1	1915	18	0	0
T2	4551	63	0	0
T3	1134	583	0	0
T4	100502	2563	0	2
T5	545957	2017	0	2
T9	4853	206	0	0
T21	0	0	0	2
T22	1057	970	0	2
T23	1814	147	0	0
T24	452281	2819	0	2
T25	2027	52	0	0
T57	0	0	0	2
T68	0	0	0	2
T69	0	0	0	2
T70	0	0	0	2
T71	0	0	0	2

gen_edn_if_asserts[3].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	237504159	6200	0	116
T1	1915	49	0	1
T2	4551	0	0	0
T3	1134	0	0	0
T4	100502	0	0	0
T5	545957	0	0	0
T9	4853	0	0	0
T22	1057	0	0	0
T23	1814	0	0	0
T24	452281	0	0	0
T25	2027	0	0	0
T29	0	3	0	1
T30	0	4	0	0
T42	0	28	0	1
T44	0	7	0	1
T45	0	33	0	1
T48	0	51	0	1
T77	0	36	0	1
T80	0	0	0	1
T84	0	4	0	1
T85	0	62	0	1

gen_edn_if_asserts[3].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	237504159	237335563	0	0
T1	1915	1862	0	0
T2	4551	4480	0	0
T3	1134	974	0	0
T4	100502	100500	0	0
T5	545957	545946	0	0
T9	4853	4767	0	0
T22	1057	972	0	0
T23	1814	1716	0	0
T24	452281	452265	0	0
T25	2027	1955	0	0

gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	237504159	154485	0	0
T3	1134	640	0	0
T4	100502	0	0	0
T5	545957	0	0	0
T6	0	1151	0	0
T7	0	631	0	0
T8	0	1072	0	0
T9	4853	0	0	0
T14	0	1135	0	0
T15	0	604	0	0
T22	1057	0	0	0
T23	1814	0	0	0
T24	452281	0	0	0
T25	2027	0	0	0
T34	0	7	0	0
T37	0	1120	0	0
T38	0	1072	0	0
T57	438279	0	0	0
T58	15006	0	0	0
T75	0	645	0	0

gen_edn_if_asserts[4].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	237504159	555082	0	332
T1	1915	18	0	0
T2	4551	63	0	0
T3	1134	583	0	0
T4	100502	2563	0	2
T5	545957	2017	0	2
T9	4853	206	0	0
T21	0	0	0	2
T22	1057	970	0	2
T23	1814	147	0	0
T24	452281	2819	0	2
T25	2027	52	0	0
T57	0	0	0	2
T68	0	0	0	2
T69	0	0	0	2
T70	0	0	0	2
T71	0	0	0	2

gen_edn_if_asserts[4].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	237504159	3425	0	80
T1	1915	25	0	1
T2	4551	0	0	0
T3	1134	0	0	0
T4	100502	0	0	0
T5	545957	0	0	0
T9	4853	0	0	0
T22	1057	0	0	0
T23	1814	0	0	0
T24	452281	0	0	0
T25	2027	0	0	0
T29	0	52	0	1
T42	0	14	0	1
T44	0	52	0	1
T45	0	3	0	1
T48	0	19	0	1
T49	0	0	0	1
T81	0	3	0	1
T86	0	1	0	0
T87	0	4	0	0
T88	0	61	0	1
T89	0	0	0	1

gen_edn_if_asserts[4].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	237504159	237335563	0	0
T1	1915	1862	0	0
T2	4551	4480	0	0
T3	1134	974	0	0
T4	100502	100500	0	0
T5	545957	545946	0	0
T9	4853	4767	0	0
T22	1057	972	0	0
T23	1814	1716	0	0
T24	452281	452265	0	0
T25	2027	1955	0	0

gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	237504159	154485	0	0
T3	1134	640	0	0
T4	100502	0	0	0
T5	545957	0	0	0
T6	0	1151	0	0
T7	0	631	0	0
T8	0	1072	0	0
T9	4853	0	0	0
T14	0	1135	0	0
T15	0	604	0	0
T22	1057	0	0	0
T23	1814	0	0	0
T24	452281	0	0	0
T25	2027	0	0	0
T34	0	7	0	0
T37	0	1120	0	0
T38	0	1072	0	0
T57	438279	0	0	0
T58	15006	0	0	0
T75	0	645	0	0

gen_edn_if_asserts[5].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	237504159	555082	0	332
T1	1915	18	0	0
T2	4551	63	0	0
T3	1134	583	0	0
T4	100502	2563	0	2
T5	545957	2017	0	2
T9	4853	206	0	0
T21	0	0	0	2
T22	1057	970	0	2
T23	1814	147	0	0
T24	452281	2819	0	2
T25	2027	52	0	0
T57	0	0	0	2
T68	0	0	0	2
T69	0	0	0	2
T70	0	0	0	2
T71	0	0	0	2

gen_edn_if_asserts[5].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	237504159	2259	0	92
T1	1915	3	0	1
T2	4551	0	0	0
T3	1134	0	0	0
T4	100502	0	0	0
T5	545957	0	0	0
T9	4853	0	0	0
T22	1057	0	0	0
T23	1814	0	0	0
T24	452281	0	0	0
T25	2027	0	0	0
T29	0	11	0	1
T32	0	1	0	0
T42	0	17	0	1
T43	0	3	0	1
T44	0	3	0	1
T47	0	27	0	1
T48	0	45	0	1
T85	0	0	0	1
T90	0	3	0	1
T91	0	4	0	1

gen_edn_if_asserts[5].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	237504159	237335563	0	0
T1	1915	1862	0	0
T2	4551	4480	0	0
T3	1134	974	0	0
T4	100502	100500	0	0
T5	545957	545946	0	0
T9	4853	4767	0	0
T22	1057	972	0	0
T23	1814	1716	0	0
T24	452281	452265	0	0
T25	2027	1955	0	0

gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	237504159	154485	0	0
T3	1134	640	0	0
T4	100502	0	0	0
T5	545957	0	0	0
T6	0	1151	0	0
T7	0	631	0	0
T8	0	1072	0	0
T9	4853	0	0	0
T14	0	1135	0	0
T15	0	604	0	0
T22	1057	0	0	0
T23	1814	0	0	0
T24	452281	0	0	0
T25	2027	0	0	0
T34	0	7	0	0
T37	0	1120	0	0
T38	0	1072	0	0
T57	438279	0	0	0
T58	15006	0	0	0
T75	0	645	0	0

gen_edn_if_asserts[6].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	237504159	555082	0	332
T1	1915	18	0	0
T2	4551	63	0	0
T3	1134	583	0	0
T4	100502	2563	0	2
T5	545957	2017	0	2
T9	4853	206	0	0
T21	0	0	0	2
T22	1057	970	0	2
T23	1814	147	0	0
T24	452281	2819	0	2
T25	2027	52	0	0
T57	0	0	0	2
T68	0	0	0	2
T69	0	0	0	2
T70	0	0	0	2
T71	0	0	0	2

gen_edn_if_asserts[6].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	237504159	3045	0	78
T20	4776	0	0	0
T21	2304	4	0	0
T29	2272	3	0	1
T30	2807	0	0	0
T31	1992	0	0	0
T37	2130	0	0	0
T38	1800	0	0	0
T42	0	3	0	1
T44	0	58	0	1
T48	0	3	0	1
T49	0	47	0	1
T50	0	40	0	1
T72	12713	0	0	0
T73	1310	0	0	0
T74	981	0	0	0
T83	0	3	0	1
T85	0	3	0	1
T92	0	54	0	1
T93	0	0	0	1

gen_edn_if_asserts[6].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	237504159	237335563	0	0
T1	1915	1862	0	0
T2	4551	4480	0	0
T3	1134	974	0	0
T4	100502	100500	0	0
T5	545957	545946	0	0
T9	4853	4767	0	0
T22	1057	972	0	0
T23	1814	1716	0	0
T24	452281	452265	0	0
T25	2027	1955	0	0

gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	237504159	154485	0	0
T3	1134	640	0	0
T4	100502	0	0	0
T5	545957	0	0	0
T6	0	1151	0	0
T7	0	631	0	0
T8	0	1072	0	0
T9	4853	0	0	0
T14	0	1135	0	0
T15	0	604	0	0
T22	1057	0	0	0
T23	1814	0	0	0
T24	452281	0	0	0
T25	2027	0	0	0
T34	0	7	0	0
T37	0	1120	0	0
T38	0	1072	0	0
T57	438279	0	0	0
T58	15006	0	0	0
T75	0	645	0	0