Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44		83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	237983103	11062447	0	0
boot_gen_cmd_rd_A	237983103	44570	0	0
boot_ins_cmd_rd_A	237983103	50531	0	0
ctrl_rd_A	237983103	44051	0	0
err_code_test_rd_A	237983103	49724	0	0
intr_enable_rd_A	237983103	48519	0	0
max_num_reqs_between_reseeds_rd_A	237983103	44331	0	0
regwen_rd_A	237983103	51060	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	237983103	11062447	0	0
T4	100502	342238	0	0
T5	545957	224266	0	0
T9	4853	0	0	0
T22	1057	0	0	0
T23	1814	0	0	0
T24	452281	177406	0	0
T25	2027	0	0	0
T34	1944	0	0	0
T57	438279	240838	0	0
T58	15006	0	0	0
T69	0	221939	0	0
T161	0	654815	0	0
T193	0	104067	0	0
T194	0	472856	0	0
T195	0	397294	0	0
T196	0	63788	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	237983103	44570	0	0
T4	100502	10119	0	0
T5	545957	0	0	0
T9	4853	0	0	0
T22	1057	0	0	0
T23	1814	0	0	0
T24	452281	0	0	0
T25	2027	0	0	0
T34	1944	0	0	0
T57	438279	0	0	0
T58	15006	0	0	0
T66	0	296	0	0
T193	0	2904	0	0
T197	0	797	0	0
T198	0	13140	0	0
T199	0	4736	0	0
T200	0	1018	0	0
T201	0	6930	0	0
T202	0	4338	0	0
T203	0	8	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	237983103	50531	0	0
T4	100502	11554	0	0
T5	545957	0	0	0
T9	4853	0	0	0
T22	1057	0	0	0
T23	1814	0	0	0
T24	452281	0	0	0
T25	2027	0	0	0
T34	1944	0	0	0
T57	438279	0	0	0
T58	15006	0	0	0
T66	0	335	0	0
T193	0	3510	0	0
T197	0	930	0	0
T198	0	14938	0	0
T199	0	5732	0	0
T200	0	1258	0	0
T201	0	6832	0	0
T202	0	5148	0	0
T204	0	2	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	237983103	44051	0	0
T4	100502	9679	0	0
T5	545957	0	0	0
T9	4853	0	0	0
T22	1057	0	0	0
T23	1814	0	0	0
T24	452281	0	0	0
T25	2027	0	0	0
T34	1944	0	0	0
T51	0	1	0	0
T57	438279	0	0	0
T58	15006	0	0	0
T66	0	292	0	0
T137	0	4	0	0
T193	0	2689	0	0
T197	0	1009	0	0
T205	0	5	0	0
T206	0	3	0	0
T207	0	8	0	0
T208	0	5	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	237983103	49724	0	0
T4	100502	11217	0	0
T5	545957	0	0	0
T9	4853	0	0	0
T22	1057	0	0	0
T23	1814	0	0	0
T24	452281	0	0	0
T25	2027	0	0	0
T34	1944	0	0	0
T57	438279	0	0	0
T58	15006	0	0	0
T66	0	295	0	0
T193	0	3186	0	0
T197	0	1057	0	0
T198	0	14831	0	0
T199	0	5519	0	0
T200	0	1303	0	0
T201	0	7113	0	0
T202	0	4911	0	0
T204	0	3	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	237983103	48519	0	0
T4	100502	9928	0	0
T5	545957	0	0	0
T9	4853	0	0	0
T22	1057	0	0	0
T23	1814	0	0	0
T24	452281	0	0	0
T25	2027	0	0	0
T34	1944	0	0	0
T57	438279	0	0	0
T58	15006	0	0	0
T66	0	517	0	0
T68	0	154	0	0
T193	0	3735	0	0
T197	0	1089	0	0
T198	0	13577	0	0
T209	0	25	0	0
T210	0	19	0	0
T211	0	103	0	0
T212	0	9	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	237983103	44331	0	0
T4	100502	9473	0	0
T5	545957	0	0	0
T9	4853	0	0	0
T22	1057	0	0	0
T23	1814	0	0	0
T24	452281	0	0	0
T25	2027	0	0	0
T34	1944	0	0	0
T57	438279	0	0	0
T58	15006	0	0	0
T66	0	313	0	0
T193	0	2868	0	0
T197	0	864	0	0
T198	0	13290	0	0
T199	0	4770	0	0
T200	0	1239	0	0
T201	0	6479	0	0
T202	0	4359	0	0
T204	0	6	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	237983103	51060	0	0
T4	100502	11103	0	0
T5	545957	0	0	0
T9	4853	0	0	0
T22	1057	0	0	0
T23	1814	0	0	0
T24	452281	0	0	0
T25	2027	0	0	0
T34	1944	0	0	0
T57	438279	0	0	0
T58	15006	0	0	0
T66	0	388	0	0
T193	0	3280	0	0
T197	0	987	0	0
T198	0	14387	0	0
T199	0	5906	0	0
T200	0	1451	0	0
T201	0	7544	0	0
T202	0	5349	0	0
T204	0	9	0	0