Unified Coverage Report :: Module :: edn

Module : edn

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	94.44		83.33	100.00			100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.05	98.24	93.80	97.02	84.88	96.62	99.77

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
edn_csr_assert	100.00						100.00
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_edn_core	92.99	99.92	92.46	82.54	84.88	99.28	98.88
u_edn_cov_if	25.00	50.00	0.00
u_reg	96.95	95.02	97.57	100.00		92.16	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Cond Coverage for Module : edn

	Total	Covered	Percent
Conditions	6	5	83.33
Logical	6	5	83.33
Non-Logical	0	0
Event	0	0

 LINE       98
 EXPRESSION (alert[0] || intg_err_alert[0])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T29,T30,T31

 LINE       98
 EXPRESSION (alert[1] || intg_err_alert[1])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T18,T19,T20
1	0	Covered	T15,T6,T16

---

Toggle Coverage for Module : edn

	Total	Covered	Percent
Totals	69	69	100.00
Total Bits	1172	1172	100.00
Total Bits 0->1	586	586	100.00
Total Bits 1->0	586	586	100.00

Ports	69	69	100.00
Port Bits	1172	1172	100.00
Port Bits 0->1	586	586	100.00
Port Bits 1->0	586	586	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T10,T4	Yes	T1,T10,T4	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T1,T125,T126	Yes	T1,T125,T126	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i[0].edn_req	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
edn_i[1].edn_req	Yes	Yes	T9,T25,T106	Yes	T9,T25,T106	INPUT
edn_i[2].edn_req	Yes	Yes	T10,T109,T127	Yes	T10,T109,T127	INPUT
edn_i[3].edn_req	Yes	Yes	T10,T25,T128	Yes	T10,T25,T128	INPUT
edn_i[4].edn_req	Yes	Yes	T23,T127,T49	Yes	T23,T127,T49	INPUT
edn_i[5].edn_req	Yes	Yes	T23,T29,T127	Yes	T23,T29,T127	INPUT
edn_i[6].edn_req	Yes	Yes	T109,T21,T22	Yes	T109,T21,T22	INPUT
edn_o[0].edn_bus[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_o[0].edn_fips	Yes	Yes	T1,T11,T4	Yes	T1,T3,T11	OUTPUT
edn_o[0].edn_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_o[1].edn_bus[31:0]	Yes	Yes	T9,T25,T106	Yes	T9,T25,T106	OUTPUT
edn_o[1].edn_fips	Yes	Yes	T25,T129,T130	Yes	T9,T25,T129	OUTPUT
edn_o[1].edn_ack	Yes	Yes	T9,T25,T106	Yes	T9,T25,T106	OUTPUT
edn_o[2].edn_bus[31:0]	Yes	Yes	T109,T127,T49	Yes	T10,T109,T127	OUTPUT
edn_o[2].edn_fips	Yes	Yes	T127,T131,T13	Yes	T127,T49,T131	OUTPUT
edn_o[2].edn_ack	Yes	Yes	T10,T109,T127	Yes	T10,T109,T127	OUTPUT
edn_o[3].edn_bus[31:0]	Yes	Yes	T10,T25,T128	Yes	T10,T25,T128	OUTPUT
edn_o[3].edn_fips	Yes	Yes	T25,T109,T49	Yes	T25,T109,T127	OUTPUT
edn_o[3].edn_ack	Yes	Yes	T10,T25,T128	Yes	T10,T25,T128	OUTPUT
edn_o[4].edn_bus[31:0]	Yes	Yes	T127,T49,T132	Yes	T127,T49,T132	OUTPUT
edn_o[4].edn_fips	Yes	Yes	T127,T133,T134	Yes	T127,T49,T132	OUTPUT
edn_o[4].edn_ack	Yes	Yes	T23,T127,T49	Yes	T23,T127,T49	OUTPUT
edn_o[5].edn_bus[31:0]	Yes	Yes	T29,T127,T51	Yes	T23,T29,T127	OUTPUT
edn_o[5].edn_fips	Yes	Yes	T127,T132,T135	Yes	T23,T127,T132	OUTPUT
edn_o[5].edn_ack	Yes	Yes	T23,T29,T127	Yes	T23,T29,T127	OUTPUT
edn_o[6].edn_bus[31:0]	Yes	Yes	T109,T127,T26	Yes	T109,T21,T22	OUTPUT
edn_o[6].edn_fips	Yes	Yes	T109,T127,T26	Yes	T109,T127,T26	OUTPUT
edn_o[6].edn_ack	Yes	Yes	T109,T21,T22	Yes	T109,T21,T22	OUTPUT
csrng_cmd_o.genbits_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_bus[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_i.genbits_bus[127:0]	Yes	Yes	T1,T9,T11	Yes	T1,T9,T11	INPUT
csrng_cmd_i.genbits_fips	Yes	Yes	T1,T9,T10	Yes	T1,T3,T9	INPUT
csrng_cmd_i.genbits_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_rsp_sts[2:0]	Yes	Yes	T31,T34,T102	Yes	T31,T34,T102	INPUT
csrng_cmd_i.csrng_rsp_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_req_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T113,T29,T136	Yes	T113,T29,T136	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T15,T6,T16	Yes	T15,T6,T16	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T113,T29,T136	Yes	T113,T29,T136	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T15,T6,T16	Yes	T15,T6,T16	OUTPUT
intr_edn_cmd_req_done_o	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
intr_edn_fatal_err_o	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT

*Tests covering at least one bit in the range

---

Assert Coverage for Module : edn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	47	47	100.00	47	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	47	47	100.00	47	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxKnownO_A	195383773	195223484	0	0
CsrngAppIfOut_A	195383773	195223484	0	0
FpvSecCmCntAlertCheck_A	195383773	110	0	0
FpvSecCmGenCmdFifoRptrCheck_A	195383773	60	0	0
FpvSecCmGenCmdFifoWptrCheck_A	195383773	60	0	0
FpvSecCmMainFsmCheck_A	195383773	60	0	0
FpvSecCmRegWeOnehotCheck_A	195383773	60	0	0
FpvSecCmResCmdFifoRptrCheck_A	195383773	60	0	0
FpvSecCmResCmdFifoWptrCheck_A	195383773	60	0	0
IntrEdnCmdReqDoneKnownO_A	195383773	195223484	0	0
TlAReadyKnownO_A	195383773	195223484	0	0
TlDValidKnownO_A	195383773	195223484	0	0
gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A	195383773	60	0	0
gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A	195383773	60	0	0
gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A	195383773	60	0	0
gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A	195383773	60	0	0
gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A	195383773	60	0	0
gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A	195383773	60	0	0
gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A	195383773	60	0	0
gen_edn_if_asserts[0].EdnDataStableDisable_A	195383773	539516	0	322
gen_edn_if_asserts[0].EdnDataStable_A	195383773	75196	0	339
gen_edn_if_asserts[0].EdnEndPointOut_A	195383773	195223484	0	0
gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A	195383773	132107	0	0
gen_edn_if_asserts[1].EdnDataStableDisable_A	195383773	539516	0	322
gen_edn_if_asserts[1].EdnDataStable_A	195383773	5406	0	116
gen_edn_if_asserts[1].EdnEndPointOut_A	195383773	195223484	0	0
gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A	195383773	132107	0	0
gen_edn_if_asserts[2].EdnDataStableDisable_A	195383773	539516	0	322
gen_edn_if_asserts[2].EdnDataStable_A	195383773	3496	0	101
gen_edn_if_asserts[2].EdnEndPointOut_A	195383773	195223484	0	0
gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A	195383773	132107	0	0
gen_edn_if_asserts[3].EdnDataStableDisable_A	195383773	539516	0	322
gen_edn_if_asserts[3].EdnDataStable_A	195383773	2430	0	99
gen_edn_if_asserts[3].EdnEndPointOut_A	195383773	195223484	0	0
gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A	195383773	132107	0	0
gen_edn_if_asserts[4].EdnDataStableDisable_A	195383773	539516	0	322
gen_edn_if_asserts[4].EdnDataStable_A	195383773	4813	0	78
gen_edn_if_asserts[4].EdnEndPointOut_A	195383773	195223484	0	0
gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A	195383773	132107	0	0
gen_edn_if_asserts[5].EdnDataStableDisable_A	195383773	539516	0	322
gen_edn_if_asserts[5].EdnDataStable_A	195383773	3143	0	69
gen_edn_if_asserts[5].EdnEndPointOut_A	195383773	195223484	0	0
gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A	195383773	132107	0	0
gen_edn_if_asserts[6].EdnDataStableDisable_A	195383773	539516	0	322
gen_edn_if_asserts[6].EdnDataStable_A	195383773	3032	0	73
gen_edn_if_asserts[6].EdnEndPointOut_A	195383773	195223484	0	0
gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A	195383773	132107	0	0

AlertTxKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195383773	195223484	0	0
T1	128423	128415	0	0
T2	1425	1356	0	0
T3	2188	2134	0	0
T4	24010	23410	0	0
T9	2245	2170	0	0
T10	3270	3210	0	0
T11	5458	5378	0	0
T23	3201	3137	0	0
T24	2809	2751	0	0
T25	4524	4436	0	0

CsrngAppIfOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195383773	195223484	0	0
T1	128423	128415	0	0
T2	1425	1356	0	0
T3	2188	2134	0	0
T4	24010	23410	0	0
T9	2245	2170	0	0
T10	3270	3210	0	0
T11	5458	5378	0	0
T23	3201	3137	0	0
T24	2809	2751	0	0
T25	4524	4436	0	0

FpvSecCmCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195383773	110	0	0
T6	1686	0	0	0
T15	698	1	0	0
T16	2122	1	0	0
T17	0	1	0	0
T21	1645	0	0	0
T27	0	1	0	0
T41	0	1	0	0
T82	0	1	0	0
T88	0	1	0	0
T102	0	1	0	0
T105	0	1	0	0
T106	1126	0	0	0
T109	2473	0	0	0
T110	1845	0	0	0
T111	1425	0	0	0
T112	1124	0	0	0
T113	892	0	0	0
T137	0	1	0	0

FpvSecCmGenCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195383773	60	0	0
T18	22039	10	0	0
T19	0	10	0	0
T20	0	20	0	0
T75	3062	0	0	0
T101	2624	0	0	0
T138	0	10	0	0
T139	0	10	0	0
T140	1169	0	0	0
T141	5124	0	0	0
T142	1647	0	0	0
T143	2721	0	0	0
T144	3677	0	0	0
T145	999	0	0	0
T146	327191	0	0	0

FpvSecCmGenCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195383773	60	0	0
T18	22039	10	0	0
T19	0	10	0	0
T20	0	20	0	0
T75	3062	0	0	0
T101	2624	0	0	0
T138	0	10	0	0
T139	0	10	0	0
T140	1169	0	0	0
T141	5124	0	0	0
T142	1647	0	0	0
T143	2721	0	0	0
T144	3677	0	0	0
T145	999	0	0	0
T146	327191	0	0	0

FpvSecCmMainFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195383773	60	0	0
T18	22039	10	0	0
T19	0	10	0	0
T20	0	20	0	0
T75	3062	0	0	0
T101	2624	0	0	0
T138	0	10	0	0
T139	0	10	0	0
T140	1169	0	0	0
T141	5124	0	0	0
T142	1647	0	0	0
T143	2721	0	0	0
T144	3677	0	0	0
T145	999	0	0	0
T146	327191	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195383773	60	0	0
T18	22039	10	0	0
T19	0	10	0	0
T20	0	20	0	0
T75	3062	0	0	0
T101	2624	0	0	0
T138	0	10	0	0
T139	0	10	0	0
T140	1169	0	0	0
T141	5124	0	0	0
T142	1647	0	0	0
T143	2721	0	0	0
T144	3677	0	0	0
T145	999	0	0	0
T146	327191	0	0	0

FpvSecCmResCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195383773	60	0	0
T18	22039	10	0	0
T19	0	10	0	0
T20	0	20	0	0
T75	3062	0	0	0
T101	2624	0	0	0
T138	0	10	0	0
T139	0	10	0	0
T140	1169	0	0	0
T141	5124	0	0	0
T142	1647	0	0	0
T143	2721	0	0	0
T144	3677	0	0	0
T145	999	0	0	0
T146	327191	0	0	0

FpvSecCmResCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195383773	60	0	0
T18	22039	10	0	0
T19	0	10	0	0
T20	0	20	0	0
T75	3062	0	0	0
T101	2624	0	0	0
T138	0	10	0	0
T139	0	10	0	0
T140	1169	0	0	0
T141	5124	0	0	0
T142	1647	0	0	0
T143	2721	0	0	0
T144	3677	0	0	0
T145	999	0	0	0
T146	327191	0	0	0

IntrEdnCmdReqDoneKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195383773	195223484	0	0
T1	128423	128415	0	0
T2	1425	1356	0	0
T3	2188	2134	0	0
T4	24010	23410	0	0
T9	2245	2170	0	0
T10	3270	3210	0	0
T11	5458	5378	0	0
T23	3201	3137	0	0
T24	2809	2751	0	0
T25	4524	4436	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195383773	195223484	0	0
T1	128423	128415	0	0
T2	1425	1356	0	0
T3	2188	2134	0	0
T4	24010	23410	0	0
T9	2245	2170	0	0
T10	3270	3210	0	0
T11	5458	5378	0	0
T23	3201	3137	0	0
T24	2809	2751	0	0
T25	4524	4436	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195383773	195223484	0	0
T1	128423	128415	0	0
T2	1425	1356	0	0
T3	2188	2134	0	0
T4	24010	23410	0	0
T9	2245	2170	0	0
T10	3270	3210	0	0
T11	5458	5378	0	0
T23	3201	3137	0	0
T24	2809	2751	0	0
T25	4524	4436	0	0

gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195383773	60	0	0
T18	22039	10	0	0
T19	0	10	0	0
T20	0	20	0	0
T75	3062	0	0	0
T101	2624	0	0	0
T138	0	10	0	0
T139	0	10	0	0
T140	1169	0	0	0
T141	5124	0	0	0
T142	1647	0	0	0
T143	2721	0	0	0
T144	3677	0	0	0
T145	999	0	0	0
T146	327191	0	0	0

gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195383773	60	0	0
T18	22039	10	0	0
T19	0	10	0	0
T20	0	20	0	0
T75	3062	0	0	0
T101	2624	0	0	0
T138	0	10	0	0
T139	0	10	0	0
T140	1169	0	0	0
T141	5124	0	0	0
T142	1647	0	0	0
T143	2721	0	0	0
T144	3677	0	0	0
T145	999	0	0	0
T146	327191	0	0	0

gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195383773	60	0	0
T18	22039	10	0	0
T19	0	10	0	0
T20	0	20	0	0
T75	3062	0	0	0
T101	2624	0	0	0
T138	0	10	0	0
T139	0	10	0	0
T140	1169	0	0	0
T141	5124	0	0	0
T142	1647	0	0	0
T143	2721	0	0	0
T144	3677	0	0	0
T145	999	0	0	0
T146	327191	0	0	0

gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195383773	60	0	0
T18	22039	10	0	0
T19	0	10	0	0
T20	0	20	0	0
T75	3062	0	0	0
T101	2624	0	0	0
T138	0	10	0	0
T139	0	10	0	0
T140	1169	0	0	0
T141	5124	0	0	0
T142	1647	0	0	0
T143	2721	0	0	0
T144	3677	0	0	0
T145	999	0	0	0
T146	327191	0	0	0

gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195383773	60	0	0
T18	22039	10	0	0
T19	0	10	0	0
T20	0	20	0	0
T75	3062	0	0	0
T101	2624	0	0	0
T138	0	10	0	0
T139	0	10	0	0
T140	1169	0	0	0
T141	5124	0	0	0
T142	1647	0	0	0
T143	2721	0	0	0
T144	3677	0	0	0
T145	999	0	0	0
T146	327191	0	0	0

gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195383773	60	0	0
T18	22039	10	0	0
T19	0	10	0	0
T20	0	20	0	0
T75	3062	0	0	0
T101	2624	0	0	0
T138	0	10	0	0
T139	0	10	0	0
T140	1169	0	0	0
T141	5124	0	0	0
T142	1647	0	0	0
T143	2721	0	0	0
T144	3677	0	0	0
T145	999	0	0	0
T146	327191	0	0	0

gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195383773	60	0	0
T18	22039	10	0	0
T19	0	10	0	0
T20	0	20	0	0
T75	3062	0	0	0
T101	2624	0	0	0
T138	0	10	0	0
T139	0	10	0	0
T140	1169	0	0	0
T141	5124	0	0	0
T142	1647	0	0	0
T143	2721	0	0	0
T144	3677	0	0	0
T145	999	0	0	0
T146	327191	0	0	0

gen_edn_if_asserts[0].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195383773	539516	0	322
T1	128423	1687	0	2
T2	1425	21	0	0
T3	2188	92	0	0
T4	24010	1579	0	0
T5	0	0	0	2
T9	2245	835	0	2
T10	3270	1059	0	2
T11	5458	63	0	0
T21	0	0	0	2
T22	0	0	0	2
T23	3201	1644	0	2
T24	2809	25	0	0
T25	4524	23	0	0
T51	0	0	0	2
T113	0	0	0	2
T136	0	0	0	2

gen_edn_if_asserts[0].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195383773	75196	0	339
T1	128423	25	0	0
T2	1425	3	0	1
T3	2188	7	0	1
T4	24010	27	0	1
T5	0	6	0	0
T9	2245	0	0	0
T10	3270	0	0	0
T11	5458	579	0	1
T23	3201	0	0	0
T24	2809	3	0	1
T25	4524	0	0	0
T28	0	11	0	1
T110	0	66	0	1
T111	0	3	0	1
T112	0	0	0	1
T127	0	0	0	1

gen_edn_if_asserts[0].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195383773	195223484	0	0
T1	128423	128415	0	0
T2	1425	1356	0	0
T3	2188	2134	0	0
T4	24010	23410	0	0
T9	2245	2170	0	0
T10	3270	3210	0	0
T11	5458	5378	0	0
T23	3201	3137	0	0
T24	2809	2751	0	0
T25	4524	4436	0	0

gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195383773	132107	0	0
T6	1686	656	0	0
T7	0	397	0	0
T8	0	1111	0	0
T15	698	354	0	0
T16	2122	1100	0	0
T17	0	1090	0	0
T21	1645	0	0	0
T27	0	174	0	0
T41	0	641	0	0
T105	0	1135	0	0
T106	1126	0	0	0
T107	0	412	0	0
T109	2473	0	0	0
T110	1845	0	0	0
T111	1425	0	0	0
T112	1124	0	0	0
T113	892	0	0	0

gen_edn_if_asserts[1].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195383773	539516	0	322
T1	128423	1687	0	2
T2	1425	21	0	0
T3	2188	92	0	0
T4	24010	1579	0	0
T5	0	0	0	2
T9	2245	835	0	2
T10	3270	1059	0	2
T11	5458	63	0	0
T21	0	0	0	2
T22	0	0	0	2
T23	3201	1644	0	2
T24	2809	25	0	0
T25	4524	23	0	0
T51	0	0	0	2
T113	0	0	0	2
T136	0	0	0	2

gen_edn_if_asserts[1].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195383773	5406	0	116
T4	24010	0	0	0
T5	8073	0	0	0
T9	2245	4	0	0
T10	3270	0	0	0
T11	5458	0	0	0
T17	0	1	0	0
T22	0	4	0	0
T23	3201	0	0	0
T24	2809	0	0	0
T25	4524	30	0	1
T28	1737	0	0	0
T106	0	3	0	1
T109	0	3	0	1
T127	0	3	0	1
T128	2115	0	0	0
T129	0	30	0	1
T130	0	63	0	1
T131	0	3	0	1
T135	0	0	0	1
T147	0	0	0	1
T148	0	0	0	1

gen_edn_if_asserts[1].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195383773	195223484	0	0
T1	128423	128415	0	0
T2	1425	1356	0	0
T3	2188	2134	0	0
T4	24010	23410	0	0
T9	2245	2170	0	0
T10	3270	3210	0	0
T11	5458	5378	0	0
T23	3201	3137	0	0
T24	2809	2751	0	0
T25	4524	4436	0	0

gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195383773	132107	0	0
T6	1686	656	0	0
T7	0	397	0	0
T8	0	1111	0	0
T15	698	354	0	0
T16	2122	1100	0	0
T17	0	1090	0	0
T21	1645	0	0	0
T27	0	174	0	0
T41	0	641	0	0
T105	0	1135	0	0
T106	1126	0	0	0
T107	0	412	0	0
T109	2473	0	0	0
T110	1845	0	0	0
T111	1425	0	0	0
T112	1124	0	0	0
T113	892	0	0	0

gen_edn_if_asserts[2].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195383773	539516	0	322
T1	128423	1687	0	2
T2	1425	21	0	0
T3	2188	92	0	0
T4	24010	1579	0	0
T5	0	0	0	2
T9	2245	835	0	2
T10	3270	1059	0	2
T11	5458	63	0	0
T21	0	0	0	2
T22	0	0	0	2
T23	3201	1644	0	2
T24	2809	25	0	0
T25	4524	23	0	0
T51	0	0	0	2
T113	0	0	0	2
T136	0	0	0	2

gen_edn_if_asserts[2].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195383773	3496	0	101
T4	24010	0	0	0
T5	8073	0	0	0
T10	3270	1	0	0
T11	5458	0	0	0
T13	0	25	0	1
T15	698	0	0	0
T23	3201	0	0	0
T24	2809	0	0	0
T25	4524	0	0	0
T28	1737	0	0	0
T34	0	4	0	0
T49	0	3	0	1
T105	0	1	0	0
T109	0	3	0	1
T127	0	51	0	1
T128	2115	0	0	0
T130	0	3	0	1
T131	0	41	0	1
T132	0	11	0	1
T133	0	0	0	1
T147	0	0	0	1
T148	0	0	0	1

gen_edn_if_asserts[2].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195383773	195223484	0	0
T1	128423	128415	0	0
T2	1425	1356	0	0
T3	2188	2134	0	0
T4	24010	23410	0	0
T9	2245	2170	0	0
T10	3270	3210	0	0
T11	5458	5378	0	0
T23	3201	3137	0	0
T24	2809	2751	0	0
T25	4524	4436	0	0

gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195383773	132107	0	0
T6	1686	656	0	0
T7	0	397	0	0
T8	0	1111	0	0
T15	698	354	0	0
T16	2122	1100	0	0
T17	0	1090	0	0
T21	1645	0	0	0
T27	0	174	0	0
T41	0	641	0	0
T105	0	1135	0	0
T106	1126	0	0	0
T107	0	412	0	0
T109	2473	0	0	0
T110	1845	0	0	0
T111	1425	0	0	0
T112	1124	0	0	0
T113	892	0	0	0

gen_edn_if_asserts[3].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195383773	539516	0	322
T1	128423	1687	0	2
T2	1425	21	0	0
T3	2188	92	0	0
T4	24010	1579	0	0
T5	0	0	0	2
T9	2245	835	0	2
T10	3270	1059	0	2
T11	5458	63	0	0
T21	0	0	0	2
T22	0	0	0	2
T23	3201	1644	0	2
T24	2809	25	0	0
T25	4524	23	0	0
T51	0	0	0	2
T113	0	0	0	2
T136	0	0	0	2

gen_edn_if_asserts[3].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195383773	2430	0	99
T4	24010	0	0	0
T5	8073	0	0	0
T10	3270	4	0	0
T11	5458	0	0	0
T15	698	0	0	0
T23	3201	0	0	0
T24	2809	0	0	0
T25	4524	44	0	1
T28	1737	0	0	0
T49	0	50	0	1
T53	0	4	0	0
T73	0	0	0	1
T109	0	12	0	1
T127	0	11	0	1
T128	2115	3	0	1
T132	0	3	0	1
T134	0	42	0	1
T147	0	3	0	1
T149	0	0	0	1

gen_edn_if_asserts[3].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195383773	195223484	0	0
T1	128423	128415	0	0
T2	1425	1356	0	0
T3	2188	2134	0	0
T4	24010	23410	0	0
T9	2245	2170	0	0
T10	3270	3210	0	0
T11	5458	5378	0	0
T23	3201	3137	0	0
T24	2809	2751	0	0
T25	4524	4436	0	0

gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195383773	132107	0	0
T6	1686	656	0	0
T7	0	397	0	0
T8	0	1111	0	0
T15	698	354	0	0
T16	2122	1100	0	0
T17	0	1090	0	0
T21	1645	0	0	0
T27	0	174	0	0
T41	0	641	0	0
T105	0	1135	0	0
T106	1126	0	0	0
T107	0	412	0	0
T109	2473	0	0	0
T110	1845	0	0	0
T111	1425	0	0	0
T112	1124	0	0	0
T113	892	0	0	0

gen_edn_if_asserts[4].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195383773	539516	0	322
T1	128423	1687	0	2
T2	1425	21	0	0
T3	2188	92	0	0
T4	24010	1579	0	0
T5	0	0	0	2
T9	2245	835	0	2
T10	3270	1059	0	2
T11	5458	63	0	0
T21	0	0	0	2
T22	0	0	0	2
T23	3201	1644	0	2
T24	2809	25	0	0
T25	4524	23	0	0
T51	0	0	0	2
T113	0	0	0	2
T136	0	0	0	2

gen_edn_if_asserts[4].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195383773	4813	0	78
T5	8073	0	0	0
T6	1686	0	0	0
T15	698	0	0	0
T23	3201	1	0	0
T28	1737	0	0	0
T49	0	3	0	1
T106	1126	0	0	0
T109	2473	0	0	0
T110	1845	0	0	0
T111	1425	0	0	0
T127	0	22	0	1
T128	2115	0	0	0
T132	0	7	0	1
T133	0	24	0	1
T134	0	4	0	1
T135	0	3	0	1
T147	0	3	0	1
T149	0	26	0	1
T150	0	1008	0	1
T151	0	0	0	1

gen_edn_if_asserts[4].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195383773	195223484	0	0
T1	128423	128415	0	0
T2	1425	1356	0	0
T3	2188	2134	0	0
T4	24010	23410	0	0
T9	2245	2170	0	0
T10	3270	3210	0	0
T11	5458	5378	0	0
T23	3201	3137	0	0
T24	2809	2751	0	0
T25	4524	4436	0	0

gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195383773	132107	0	0
T6	1686	656	0	0
T7	0	397	0	0
T8	0	1111	0	0
T15	698	354	0	0
T16	2122	1100	0	0
T17	0	1090	0	0
T21	1645	0	0	0
T27	0	174	0	0
T41	0	641	0	0
T105	0	1135	0	0
T106	1126	0	0	0
T107	0	412	0	0
T109	2473	0	0	0
T110	1845	0	0	0
T111	1425	0	0	0
T112	1124	0	0	0
T113	892	0	0	0

gen_edn_if_asserts[5].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195383773	539516	0	322
T1	128423	1687	0	2
T2	1425	21	0	0
T3	2188	92	0	0
T4	24010	1579	0	0
T5	0	0	0	2
T9	2245	835	0	2
T10	3270	1059	0	2
T11	5458	63	0	0
T21	0	0	0	2
T22	0	0	0	2
T23	3201	1644	0	2
T24	2809	25	0	0
T25	4524	23	0	0
T51	0	0	0	2
T113	0	0	0	2
T136	0	0	0	2

gen_edn_if_asserts[5].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195383773	3143	0	69
T5	8073	0	0	0
T6	1686	0	0	0
T15	698	0	0	0
T23	3201	4	0	0
T28	1737	0	0	0
T29	0	4	0	1
T41	0	1	0	0
T49	0	3	0	1
T51	0	4	0	0
T60	0	4	0	0
T90	0	3	0	1
T106	1126	0	0	0
T109	2473	0	0	0
T110	1845	0	0	0
T111	1425	0	0	0
T127	0	21	0	1
T128	2115	0	0	0
T132	0	48	0	1
T134	0	0	0	1
T135	0	0	0	1
T147	0	3	0	1
T149	0	0	0	1
T152	0	0	0	1

gen_edn_if_asserts[5].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195383773	195223484	0	0
T1	128423	128415	0	0
T2	1425	1356	0	0
T3	2188	2134	0	0
T4	24010	23410	0	0
T9	2245	2170	0	0
T10	3270	3210	0	0
T11	5458	5378	0	0
T23	3201	3137	0	0
T24	2809	2751	0	0
T25	4524	4436	0	0

gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195383773	132107	0	0
T6	1686	656	0	0
T7	0	397	0	0
T8	0	1111	0	0
T15	698	354	0	0
T16	2122	1100	0	0
T17	0	1090	0	0
T21	1645	0	0	0
T27	0	174	0	0
T41	0	641	0	0
T105	0	1135	0	0
T106	1126	0	0	0
T107	0	412	0	0
T109	2473	0	0	0
T110	1845	0	0	0
T111	1425	0	0	0
T112	1124	0	0	0
T113	892	0	0	0

gen_edn_if_asserts[6].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195383773	539516	0	322
T1	128423	1687	0	2
T2	1425	21	0	0
T3	2188	92	0	0
T4	24010	1579	0	0
T5	0	0	0	2
T9	2245	835	0	2
T10	3270	1059	0	2
T11	5458	63	0	0
T21	0	0	0	2
T22	0	0	0	2
T23	3201	1644	0	2
T24	2809	25	0	0
T25	4524	23	0	0
T51	0	0	0	2
T113	0	0	0	2
T136	0	0	0	2

gen_edn_if_asserts[6].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195383773	3032	0	73
T16	2122	0	0	0
T17	2025	0	0	0
T21	1645	4	0	0
T22	4707	1	0	0
T26	0	4	0	0
T29	1922	0	0	0
T34	0	4	0	1
T109	2473	4	0	1
T110	1845	0	0	0
T111	1425	0	0	0
T112	1124	0	0	0
T113	892	0	0	0
T127	0	62	0	1
T132	0	43	0	1
T135	0	3	0	1
T147	0	30	0	1
T151	0	57	0	1
T153	0	0	0	1
T154	0	0	0	1
T155	0	0	0	1

gen_edn_if_asserts[6].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195383773	195223484	0	0
T1	128423	128415	0	0
T2	1425	1356	0	0
T3	2188	2134	0	0
T4	24010	23410	0	0
T9	2245	2170	0	0
T10	3270	3210	0	0
T11	5458	5378	0	0
T23	3201	3137	0	0
T24	2809	2751	0	0
T25	4524	4436	0	0

gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195383773	132107	0	0
T6	1686	656	0	0
T7	0	397	0	0
T8	0	1111	0	0
T15	698	354	0	0
T16	2122	1100	0	0
T17	0	1090	0	0
T21	1645	0	0	0
T27	0	174	0	0
T41	0	641	0	0
T105	0	1135	0	0
T106	1126	0	0	0
T107	0	412	0	0
T109	2473	0	0	0
T110	1845	0	0	0
T111	1425	0	0	0
T112	1124	0	0	0
T113	892	0	0	0