Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44		83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	195880277	8460422	0	0
boot_gen_cmd_rd_A	195880277	61795	0	0
boot_ins_cmd_rd_A	195880277	68928	0	0
ctrl_rd_A	195880277	60654	0	0
err_code_test_rd_A	195880277	69531	0	0
intr_enable_rd_A	195880277	68503	0	0
max_num_reqs_between_reseeds_rd_A	195880277	61865	0	0
regwen_rd_A	195880277	72004	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195880277	8460422	0	0
T1	128423	48771	0	0
T2	1425	0	0	0
T3	2188	0	0	0
T4	24010	0	0	0
T9	2245	0	0	0
T10	3270	0	0	0
T11	5458	0	0	0
T23	3201	0	0	0
T24	2809	0	0	0
T25	4524	0	0	0
T125	0	281583	0	0
T126	0	248866	0	0
T146	0	115134	0	0
T160	0	167538	0	0
T162	0	115427	0	0
T164	0	39894	0	0
T204	0	40039	0	0
T205	0	134307	0	0
T206	0	163148	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195880277	61795	0	0
T1	128423	876	0	0
T2	1425	0	0	0
T3	2188	0	0	0
T4	24010	0	0	0
T9	2245	0	0	0
T10	3270	0	0	0
T11	5458	0	0	0
T23	3201	0	0	0
T24	2809	0	0	0
T25	4524	0	0	0
T125	0	8633	0	0
T146	0	3563	0	0
T162	0	3606	0	0
T204	0	1307	0	0
T207	0	2020	0	0
T208	0	4278	0	0
T209	0	1612	0	0
T210	0	4919	0	0
T211	0	7520	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195880277	68928	0	0
T1	128423	901	0	0
T2	1425	0	0	0
T3	2188	0	0	0
T4	24010	0	0	0
T9	2245	0	0	0
T10	3270	0	0	0
T11	5458	0	0	0
T23	3201	0	0	0
T24	2809	0	0	0
T25	4524	0	0	0
T125	0	9852	0	0
T146	0	3934	0	0
T162	0	3742	0	0
T204	0	1334	0	0
T207	0	2084	0	0
T208	0	5172	0	0
T209	0	1732	0	0
T210	0	5155	0	0
T211	0	8771	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195880277	60654	0	0
T1	128423	708	0	0
T2	1425	0	0	0
T3	2188	0	0	0
T4	24010	5	0	0
T9	2245	0	0	0
T10	3270	0	0	0
T11	5458	0	0	0
T23	3201	0	0	0
T24	2809	0	0	0
T25	4524	0	0	0
T75	0	7	0	0
T114	0	10	0	0
T125	0	8345	0	0
T146	0	3622	0	0
T155	0	2	0	0
T162	0	3251	0	0
T204	0	1299	0	0
T212	0	5	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195880277	69531	0	0
T1	128423	988	0	0
T2	1425	0	0	0
T3	2188	0	0	0
T4	24010	0	0	0
T9	2245	0	0	0
T10	3270	0	0	0
T11	5458	0	0	0
T23	3201	0	0	0
T24	2809	0	0	0
T25	4524	0	0	0
T125	0	9279	0	0
T146	0	3871	0	0
T162	0	3621	0	0
T204	0	1294	0	0
T207	0	2348	0	0
T208	0	5391	0	0
T209	0	1881	0	0
T210	0	5556	0	0
T211	0	8372	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195880277	68503	0	0
T1	128423	950	0	0
T2	1425	0	0	0
T3	2188	0	0	0
T4	24010	29	0	0
T9	2245	0	0	0
T10	3270	0	0	0
T11	5458	0	0	0
T23	3201	0	0	0
T24	2809	0	0	0
T25	4524	0	0	0
T125	0	8627	0	0
T146	0	3957	0	0
T162	0	3673	0	0
T204	0	1738	0	0
T207	0	1981	0	0
T213	0	47	0	0
T214	0	6	0	0
T215	0	99	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195880277	61865	0	0
T1	128423	741	0	0
T2	1425	0	0	0
T3	2188	0	0	0
T4	24010	0	0	0
T9	2245	0	0	0
T10	3270	0	0	0
T11	5458	0	0	0
T23	3201	0	0	0
T24	2809	0	0	0
T25	4524	0	0	0
T125	0	8231	0	0
T146	0	3410	0	0
T162	0	3103	0	0
T204	0	1131	0	0
T207	0	1917	0	0
T208	0	4546	0	0
T209	0	1436	0	0
T210	0	4761	0	0
T211	0	7923	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195880277	72004	0	0
T1	128423	877	0	0
T2	1425	0	0	0
T3	2188	0	0	0
T4	24010	0	0	0
T9	2245	0	0	0
T10	3270	0	0	0
T11	5458	0	0	0
T23	3201	0	0	0
T24	2809	0	0	0
T25	4524	0	0	0
T125	0	9937	0	0
T146	0	3915	0	0
T162	0	3700	0	0
T204	0	1481	0	0
T207	0	2099	0	0
T208	0	5403	0	0
T209	0	1724	0	0
T210	0	5441	0	0
T211	0	9025	0	0