Unified Coverage Report :: Module :: edn

Module : edn

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	94.44		83.33	100.00			100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.96	98.24	93.74	97.07	84.30	96.62	99.77

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
edn_csr_assert	100.00						100.00
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_edn_core	92.93	99.92	92.37	82.84	84.30	99.28	98.88
u_edn_cov_if	25.00	50.00	0.00
u_reg	96.95	95.02	97.57	100.00		92.16	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Cond Coverage for Module : edn

	Total	Covered	Percent
Conditions	6	5	83.33
Logical	6	5	83.33
Non-Logical	0	0
Event	0	0

 LINE       98
 EXPRESSION (alert[0] || intg_err_alert[0])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T8,T16,T29

 LINE       98
 EXPRESSION (alert[1] || intg_err_alert[1])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T19,T20
1	0	Covered	T2,T4,T18

---

Toggle Coverage for Module : edn

	Total	Covered	Percent
Totals	69	69	100.00
Total Bits	1172	1172	100.00
Total Bits 0->1	586	586	100.00
Total Bits 1->0	586	586	100.00

Ports	69	69	100.00
Port Bits	1172	1172	100.00
Port Bits 0->1	586	586	100.00
Port Bits 1->0	586	586	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T1,T24,T112	Yes	T1,T24,T112	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T3,T23	Yes	T1,T3,T23	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i[0].edn_req	Yes	Yes	T1,T4,T23	Yes	T1,T4,T23	INPUT
edn_i[1].edn_req	Yes	Yes	T23,T27,T8	Yes	T23,T27,T8	INPUT
edn_i[2].edn_req	Yes	Yes	T27,T8,T106	Yes	T27,T8,T106	INPUT
edn_i[3].edn_req	Yes	Yes	T2,T3,T30	Yes	T2,T3,T30	INPUT
edn_i[4].edn_req	Yes	Yes	T27,T30,T60	Yes	T27,T30,T60	INPUT
edn_i[5].edn_req	Yes	Yes	T30,T113,T114	Yes	T30,T113,T114	INPUT
edn_i[6].edn_req	Yes	Yes	T30,T29,T115	Yes	T30,T29,T115	INPUT
edn_o[0].edn_bus[31:0]	Yes	Yes	T1,T23,T24	Yes	T1,T23,T24	OUTPUT
edn_o[0].edn_fips	Yes	Yes	T1,T23,T24	Yes	T1,T23,T24	OUTPUT
edn_o[0].edn_ack	Yes	Yes	T1,T23,T24	Yes	T1,T23,T24	OUTPUT
edn_o[1].edn_bus[31:0]	Yes	Yes	T23,T27,T8	Yes	T23,T27,T8	OUTPUT
edn_o[1].edn_fips	Yes	Yes	T27,T8,T10	Yes	T27,T8,T113	OUTPUT
edn_o[1].edn_ack	Yes	Yes	T23,T27,T8	Yes	T23,T27,T8	OUTPUT
edn_o[2].edn_bus[31:0]	Yes	Yes	T8,T106,T114	Yes	T27,T8,T106	OUTPUT
edn_o[2].edn_fips	Yes	Yes	T106,T98,T9	Yes	T27,T106,T98	OUTPUT
edn_o[2].edn_ack	Yes	Yes	T27,T8,T106	Yes	T27,T8,T106	OUTPUT
edn_o[3].edn_bus[31:0]	Yes	Yes	T3,T30,T114	Yes	T3,T30,T114	OUTPUT
edn_o[3].edn_fips	Yes	Yes	T116,T11,T117	Yes	T3,T30,T114	OUTPUT
edn_o[3].edn_ack	Yes	Yes	T3,T30,T114	Yes	T3,T30,T114	OUTPUT
edn_o[4].edn_bus[31:0]	Yes	Yes	T27,T30,T60	Yes	T27,T30,T60	OUTPUT
edn_o[4].edn_fips	Yes	Yes	T30,T118,T119	Yes	T27,T30,T34	OUTPUT
edn_o[4].edn_ack	Yes	Yes	T27,T30,T60	Yes	T27,T30,T60	OUTPUT
edn_o[5].edn_bus[31:0]	Yes	Yes	T30,T113,T114	Yes	T30,T113,T114	OUTPUT
edn_o[5].edn_fips	Yes	Yes	T30,T113,T116	Yes	T30,T113,T116	OUTPUT
edn_o[5].edn_ack	Yes	Yes	T30,T113,T114	Yes	T30,T113,T114	OUTPUT
edn_o[6].edn_bus[31:0]	Yes	Yes	T30,T29,T115	Yes	T30,T29,T115	OUTPUT
edn_o[6].edn_fips	Yes	Yes	T120,T121,T122	Yes	T29,T120,T56	OUTPUT
edn_o[6].edn_ack	Yes	Yes	T30,T29,T115	Yes	T30,T29,T115	OUTPUT
csrng_cmd_o.genbits_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_bus[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_i.genbits_bus[127:0]	Yes	Yes	T1,T23,T24	Yes	T1,T23,T24	INPUT
csrng_cmd_i.genbits_fips	Yes	Yes	T1,T23,T24	Yes	T1,T24,T25	INPUT
csrng_cmd_i.genbits_valid	Yes	Yes	T1,T3,T23	Yes	T1,T3,T23	INPUT
csrng_cmd_i.csrng_rsp_sts[2:0]	Yes	Yes	T8,T73,T99	Yes	T8,T73,T99	INPUT
csrng_cmd_i.csrng_rsp_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_req_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T102,T8,T16	Yes	T102,T8,T16	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T2,T4,T18	Yes	T2,T4,T18	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T102,T8,T16	Yes	T102,T8,T16	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T2,T4,T18	Yes	T2,T4,T18	OUTPUT
intr_edn_cmd_req_done_o	Yes	Yes	T1,T24,T26	Yes	T1,T24,T26	OUTPUT
intr_edn_fatal_err_o	Yes	Yes	T1,T24,T26	Yes	T1,T24,T26	OUTPUT

*Tests covering at least one bit in the range

---

Assert Coverage for Module : edn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	47	47	100.00	47	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	47	47	100.00	47	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxKnownO_A	200749460	200562176	0	0
CsrngAppIfOut_A	200749460	200562176	0	0
FpvSecCmCntAlertCheck_A	200749460	130	0	0
FpvSecCmGenCmdFifoRptrCheck_A	200749460	90	0	0
FpvSecCmGenCmdFifoWptrCheck_A	200749460	90	0	0
FpvSecCmMainFsmCheck_A	200749460	90	0	0
FpvSecCmRegWeOnehotCheck_A	200749460	90	0	0
FpvSecCmResCmdFifoRptrCheck_A	200749460	90	0	0
FpvSecCmResCmdFifoWptrCheck_A	200749460	90	0	0
IntrEdnCmdReqDoneKnownO_A	200749460	200562176	0	0
TlAReadyKnownO_A	200749460	200562176	0	0
TlDValidKnownO_A	200749460	200562176	0	0
gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A	200749460	90	0	0
gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A	200749460	90	0	0
gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A	200749460	90	0	0
gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A	200749460	90	0	0
gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A	200749460	90	0	0
gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A	200749460	90	0	0
gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A	200749460	90	0	0
gen_edn_if_asserts[0].EdnDataStableDisable_A	200749460	585931	0	326
gen_edn_if_asserts[0].EdnDataStable_A	200749460	71407	0	346
gen_edn_if_asserts[0].EdnEndPointOut_A	200749460	200562176	0	0
gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A	200749460	161759	0	0
gen_edn_if_asserts[1].EdnDataStableDisable_A	200749460	585931	0	326
gen_edn_if_asserts[1].EdnDataStable_A	200749460	3907	0	128
gen_edn_if_asserts[1].EdnEndPointOut_A	200749460	200562176	0	0
gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A	200749460	161759	0	0
gen_edn_if_asserts[2].EdnDataStableDisable_A	200749460	585931	0	326
gen_edn_if_asserts[2].EdnDataStable_A	200749460	4590	0	104
gen_edn_if_asserts[2].EdnEndPointOut_A	200749460	200562176	0	0
gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A	200749460	161759	0	0
gen_edn_if_asserts[3].EdnDataStableDisable_A	200749460	585931	0	326
gen_edn_if_asserts[3].EdnDataStable_A	200749460	4651	0	98
gen_edn_if_asserts[3].EdnEndPointOut_A	200749460	200562176	0	0
gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A	200749460	161759	0	0
gen_edn_if_asserts[4].EdnDataStableDisable_A	200749460	585931	0	326
gen_edn_if_asserts[4].EdnDataStable_A	200749460	4542	0	98
gen_edn_if_asserts[4].EdnEndPointOut_A	200749460	200562176	0	0
gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A	200749460	161759	0	0
gen_edn_if_asserts[5].EdnDataStableDisable_A	200749460	585931	0	326
gen_edn_if_asserts[5].EdnDataStable_A	200749460	2186	0	84
gen_edn_if_asserts[5].EdnEndPointOut_A	200749460	200562176	0	0
gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A	200749460	161759	0	0
gen_edn_if_asserts[6].EdnDataStableDisable_A	200749460	585931	0	326
gen_edn_if_asserts[6].EdnDataStable_A	200749460	2400	0	72
gen_edn_if_asserts[6].EdnEndPointOut_A	200749460	200562176	0	0
gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A	200749460	161759	0	0

AlertTxKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200749460	200562176	0	0
T1	134184	134174	0	0
T2	2162	2009	0	0
T3	4436	4378	0	0
T4	906	753	0	0
T18	1076	950	0	0
T23	1366	1305	0	0
T24	286141	286130	0	0
T25	2050	1954	0	0
T26	29936	29441	0	0
T27	4152	4065	0	0

CsrngAppIfOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200749460	200562176	0	0
T1	134184	134174	0	0
T2	2162	2009	0	0
T3	4436	4378	0	0
T4	906	753	0	0
T18	1076	950	0	0
T23	1366	1305	0	0
T24	286141	286130	0	0
T25	2050	1954	0	0
T26	29936	29441	0	0
T27	4152	4065	0	0

FpvSecCmCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200749460	130	0	0
T5	2251	0	0	0
T6	0	1	0	0
T7	0	1	0	0
T9	3680	0	0	0
T10	1883	0	0	0
T13	22305	10	0	0
T14	0	1	0	0
T15	0	1	0	0
T58	0	1	0	0
T69	0	1	0	0
T74	0	1	0	0
T113	1937	0	0	0
T114	3366	0	0	0
T123	0	1	0	0
T124	0	1	0	0
T125	24951	0	0	0
T126	240929	0	0	0
T127	1967	0	0	0
T128	13654	0	0	0

FpvSecCmGenCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200749460	90	0	0
T5	2251	0	0	0
T9	3680	0	0	0
T10	1883	0	0	0
T13	22305	10	0	0
T19	0	20	0	0
T20	0	20	0	0
T113	1937	0	0	0
T114	3366	0	0	0
T125	24951	0	0	0
T126	240929	0	0	0
T127	1967	0	0	0
T128	13654	0	0	0
T129	0	20	0	0
T130	0	20	0	0

FpvSecCmGenCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200749460	90	0	0
T5	2251	0	0	0
T9	3680	0	0	0
T10	1883	0	0	0
T13	22305	10	0	0
T19	0	20	0	0
T20	0	20	0	0
T113	1937	0	0	0
T114	3366	0	0	0
T125	24951	0	0	0
T126	240929	0	0	0
T127	1967	0	0	0
T128	13654	0	0	0
T129	0	20	0	0
T130	0	20	0	0

FpvSecCmMainFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200749460	90	0	0
T5	2251	0	0	0
T9	3680	0	0	0
T10	1883	0	0	0
T13	22305	10	0	0
T19	0	20	0	0
T20	0	20	0	0
T113	1937	0	0	0
T114	3366	0	0	0
T125	24951	0	0	0
T126	240929	0	0	0
T127	1967	0	0	0
T128	13654	0	0	0
T129	0	20	0	0
T130	0	20	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200749460	90	0	0
T5	2251	0	0	0
T9	3680	0	0	0
T10	1883	0	0	0
T13	22305	10	0	0
T19	0	20	0	0
T20	0	20	0	0
T113	1937	0	0	0
T114	3366	0	0	0
T125	24951	0	0	0
T126	240929	0	0	0
T127	1967	0	0	0
T128	13654	0	0	0
T129	0	20	0	0
T130	0	20	0	0

FpvSecCmResCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200749460	90	0	0
T5	2251	0	0	0
T9	3680	0	0	0
T10	1883	0	0	0
T13	22305	10	0	0
T19	0	20	0	0
T20	0	20	0	0
T113	1937	0	0	0
T114	3366	0	0	0
T125	24951	0	0	0
T126	240929	0	0	0
T127	1967	0	0	0
T128	13654	0	0	0
T129	0	20	0	0
T130	0	20	0	0

FpvSecCmResCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200749460	90	0	0
T5	2251	0	0	0
T9	3680	0	0	0
T10	1883	0	0	0
T13	22305	10	0	0
T19	0	20	0	0
T20	0	20	0	0
T113	1937	0	0	0
T114	3366	0	0	0
T125	24951	0	0	0
T126	240929	0	0	0
T127	1967	0	0	0
T128	13654	0	0	0
T129	0	20	0	0
T130	0	20	0	0

IntrEdnCmdReqDoneKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200749460	200562176	0	0
T1	134184	134174	0	0
T2	2162	2009	0	0
T3	4436	4378	0	0
T4	906	753	0	0
T18	1076	950	0	0
T23	1366	1305	0	0
T24	286141	286130	0	0
T25	2050	1954	0	0
T26	29936	29441	0	0
T27	4152	4065	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200749460	200562176	0	0
T1	134184	134174	0	0
T2	2162	2009	0	0
T3	4436	4378	0	0
T4	906	753	0	0
T18	1076	950	0	0
T23	1366	1305	0	0
T24	286141	286130	0	0
T25	2050	1954	0	0
T26	29936	29441	0	0
T27	4152	4065	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200749460	200562176	0	0
T1	134184	134174	0	0
T2	2162	2009	0	0
T3	4436	4378	0	0
T4	906	753	0	0
T18	1076	950	0	0
T23	1366	1305	0	0
T24	286141	286130	0	0
T25	2050	1954	0	0
T26	29936	29441	0	0
T27	4152	4065	0	0

gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200749460	90	0	0
T5	2251	0	0	0
T9	3680	0	0	0
T10	1883	0	0	0
T13	22305	10	0	0
T19	0	20	0	0
T20	0	20	0	0
T113	1937	0	0	0
T114	3366	0	0	0
T125	24951	0	0	0
T126	240929	0	0	0
T127	1967	0	0	0
T128	13654	0	0	0
T129	0	20	0	0
T130	0	20	0	0

gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200749460	90	0	0
T5	2251	0	0	0
T9	3680	0	0	0
T10	1883	0	0	0
T13	22305	10	0	0
T19	0	20	0	0
T20	0	20	0	0
T113	1937	0	0	0
T114	3366	0	0	0
T125	24951	0	0	0
T126	240929	0	0	0
T127	1967	0	0	0
T128	13654	0	0	0
T129	0	20	0	0
T130	0	20	0	0

gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200749460	90	0	0
T5	2251	0	0	0
T9	3680	0	0	0
T10	1883	0	0	0
T13	22305	10	0	0
T19	0	20	0	0
T20	0	20	0	0
T113	1937	0	0	0
T114	3366	0	0	0
T125	24951	0	0	0
T126	240929	0	0	0
T127	1967	0	0	0
T128	13654	0	0	0
T129	0	20	0	0
T130	0	20	0	0

gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200749460	90	0	0
T5	2251	0	0	0
T9	3680	0	0	0
T10	1883	0	0	0
T13	22305	10	0	0
T19	0	20	0	0
T20	0	20	0	0
T113	1937	0	0	0
T114	3366	0	0	0
T125	24951	0	0	0
T126	240929	0	0	0
T127	1967	0	0	0
T128	13654	0	0	0
T129	0	20	0	0
T130	0	20	0	0

gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200749460	90	0	0
T5	2251	0	0	0
T9	3680	0	0	0
T10	1883	0	0	0
T13	22305	10	0	0
T19	0	20	0	0
T20	0	20	0	0
T113	1937	0	0	0
T114	3366	0	0	0
T125	24951	0	0	0
T126	240929	0	0	0
T127	1967	0	0	0
T128	13654	0	0	0
T129	0	20	0	0
T130	0	20	0	0

gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200749460	90	0	0
T5	2251	0	0	0
T9	3680	0	0	0
T10	1883	0	0	0
T13	22305	10	0	0
T19	0	20	0	0
T20	0	20	0	0
T113	1937	0	0	0
T114	3366	0	0	0
T125	24951	0	0	0
T126	240929	0	0	0
T127	1967	0	0	0
T128	13654	0	0	0
T129	0	20	0	0
T130	0	20	0	0

gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200749460	90	0	0
T5	2251	0	0	0
T9	3680	0	0	0
T10	1883	0	0	0
T13	22305	10	0	0
T19	0	20	0	0
T20	0	20	0	0
T113	1937	0	0	0
T114	3366	0	0	0
T125	24951	0	0	0
T126	240929	0	0	0
T127	1967	0	0	0
T128	13654	0	0	0
T129	0	20	0	0
T130	0	20	0	0

gen_edn_if_asserts[0].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200749460	585931	0	326
T1	134184	1263	0	2
T2	2162	617	0	0
T3	4436	15	0	0
T4	906	444	0	0
T13	0	0	0	2
T18	1076	569	0	0
T23	1366	42	0	0
T24	286141	1335	0	2
T25	2050	19	0	0
T26	29936	2227	0	2
T27	4152	28	0	0
T28	0	0	0	2
T102	0	0	0	2
T112	0	0	0	2
T126	0	0	0	2
T131	0	0	0	2
T132	0	0	0	2

gen_edn_if_asserts[0].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200749460	71407	0	346
T1	134184	68	0	0
T2	2162	0	0	0
T3	4436	0	0	0
T4	906	0	0	0
T10	0	0	0	1
T16	0	8	0	1
T17	0	1	0	0
T18	1076	0	0	0
T23	1366	7	0	1
T24	286141	147	0	0
T25	2050	62	0	1
T26	29936	3	0	0
T27	4152	32	0	1
T94	0	15	0	1
T103	0	0	0	1
T112	0	45	0	0
T113	0	0	0	1
T125	0	0	0	1
T127	0	0	0	1

gen_edn_if_asserts[0].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200749460	200562176	0	0
T1	134184	134174	0	0
T2	2162	2009	0	0
T3	4436	4378	0	0
T4	906	753	0	0
T18	1076	950	0	0
T23	1366	1305	0	0
T24	286141	286130	0	0
T25	2050	1954	0	0
T26	29936	29441	0	0
T27	4152	4065	0	0

gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200749460	161759	0	0
T2	2162	635	0	0
T3	4436	0	0	0
T4	906	461	0	0
T5	0	411	0	0
T13	0	7381	0	0
T17	0	24	0	0
T18	1076	612	0	0
T23	1366	0	0	0
T24	286141	0	0	0
T25	2050	0	0	0
T26	29936	0	0	0
T27	4152	0	0	0
T79	0	292	0	0
T98	0	1100	0	0
T101	0	397	0	0
T102	1726	0	0	0
T106	0	7	0	0

gen_edn_if_asserts[1].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200749460	585931	0	326
T1	134184	1263	0	2
T2	2162	617	0	0
T3	4436	15	0	0
T4	906	444	0	0
T13	0	0	0	2
T18	1076	569	0	0
T23	1366	42	0	0
T24	286141	1335	0	2
T25	2050	19	0	0
T26	29936	2227	0	2
T27	4152	28	0	0
T28	0	0	0	2
T102	0	0	0	2
T112	0	0	0	2
T126	0	0	0	2
T131	0	0	0	2
T132	0	0	0	2

gen_edn_if_asserts[1].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200749460	3907	0	128
T8	2637	4	0	0
T9	0	41	0	1
T10	0	21	0	1
T11	0	34	0	1
T16	2609	0	0	0
T18	1076	0	0	0
T21	0	15	0	1
T23	1366	9	0	1
T24	286141	0	0	0
T25	2050	0	0	0
T26	29936	0	0	0
T27	4152	51	0	1
T30	2589	0	0	0
T102	1726	0	0	0
T113	0	3	0	1
T114	0	3	0	1
T115	0	3	0	1
T133	0	0	0	1

gen_edn_if_asserts[1].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200749460	200562176	0	0
T1	134184	134174	0	0
T2	2162	2009	0	0
T3	4436	4378	0	0
T4	906	753	0	0
T18	1076	950	0	0
T23	1366	1305	0	0
T24	286141	286130	0	0
T25	2050	1954	0	0
T26	29936	29441	0	0
T27	4152	4065	0	0

gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200749460	161759	0	0
T2	2162	635	0	0
T3	4436	0	0	0
T4	906	461	0	0
T5	0	411	0	0
T13	0	7381	0	0
T17	0	24	0	0
T18	1076	612	0	0
T23	1366	0	0	0
T24	286141	0	0	0
T25	2050	0	0	0
T26	29936	0	0	0
T27	4152	0	0	0
T79	0	292	0	0
T98	0	1100	0	0
T101	0	397	0	0
T102	1726	0	0	0
T106	0	7	0	0

gen_edn_if_asserts[2].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200749460	585931	0	326
T1	134184	1263	0	2
T2	2162	617	0	0
T3	4436	15	0	0
T4	906	444	0	0
T13	0	0	0	2
T18	1076	569	0	0
T23	1366	42	0	0
T24	286141	1335	0	2
T25	2050	19	0	0
T26	29936	2227	0	2
T27	4152	28	0	0
T28	0	0	0	2
T102	0	0	0	2
T112	0	0	0	2
T126	0	0	0	2
T131	0	0	0	2
T132	0	0	0	2

gen_edn_if_asserts[2].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200749460	4590	0	104
T8	2637	4	0	1
T9	0	567	0	1
T11	0	35	0	1
T16	2609	0	0	0
T17	927	0	0	0
T27	4152	3	0	1
T30	2589	0	0	0
T94	2217	0	0	0
T98	2083	1	0	0
T102	1726	0	0	0
T106	1706	1	0	0
T112	296604	0	0	0
T114	0	3	0	1
T115	0	17	0	1
T116	0	13	0	1
T117	0	0	0	1
T133	0	0	0	1
T134	0	3	0	1

gen_edn_if_asserts[2].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200749460	200562176	0	0
T1	134184	134174	0	0
T2	2162	2009	0	0
T3	4436	4378	0	0
T4	906	753	0	0
T18	1076	950	0	0
T23	1366	1305	0	0
T24	286141	286130	0	0
T25	2050	1954	0	0
T26	29936	29441	0	0
T27	4152	4065	0	0

gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200749460	161759	0	0
T2	2162	635	0	0
T3	4436	0	0	0
T4	906	461	0	0
T5	0	411	0	0
T13	0	7381	0	0
T17	0	24	0	0
T18	1076	612	0	0
T23	1366	0	0	0
T24	286141	0	0	0
T25	2050	0	0	0
T26	29936	0	0	0
T27	4152	0	0	0
T79	0	292	0	0
T98	0	1100	0	0
T101	0	397	0	0
T102	1726	0	0	0
T106	0	7	0	0

gen_edn_if_asserts[3].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200749460	585931	0	326
T1	134184	1263	0	2
T2	2162	617	0	0
T3	4436	15	0	0
T4	906	444	0	0
T13	0	0	0	2
T18	1076	569	0	0
T23	1366	42	0	0
T24	286141	1335	0	2
T25	2050	19	0	0
T26	29936	2227	0	2
T27	4152	28	0	0
T28	0	0	0	2
T102	0	0	0	2
T112	0	0	0	2
T126	0	0	0	2
T131	0	0	0	2
T132	0	0	0	2

gen_edn_if_asserts[3].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200749460	4651	0	98
T3	4436	3	0	1
T4	906	0	0	0
T8	2637	0	0	0
T11	0	31	0	1
T18	1076	0	0	0
T23	1366	0	0	0
T24	286141	0	0	0
T25	2050	0	0	0
T26	29936	0	0	0
T27	4152	0	0	0
T30	0	3	0	1
T35	0	4	0	1
T88	0	4	0	0
T102	1726	0	0	0
T114	0	4	0	1
T115	0	3	0	1
T116	0	40	0	1
T117	0	11	0	1
T118	0	0	0	1
T135	0	4	0	0
T136	0	0	0	1

gen_edn_if_asserts[3].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200749460	200562176	0	0
T1	134184	134174	0	0
T2	2162	2009	0	0
T3	4436	4378	0	0
T4	906	753	0	0
T18	1076	950	0	0
T23	1366	1305	0	0
T24	286141	286130	0	0
T25	2050	1954	0	0
T26	29936	29441	0	0
T27	4152	4065	0	0

gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200749460	161759	0	0
T2	2162	635	0	0
T3	4436	0	0	0
T4	906	461	0	0
T5	0	411	0	0
T13	0	7381	0	0
T17	0	24	0	0
T18	1076	612	0	0
T23	1366	0	0	0
T24	286141	0	0	0
T25	2050	0	0	0
T26	29936	0	0	0
T27	4152	0	0	0
T79	0	292	0	0
T98	0	1100	0	0
T101	0	397	0	0
T102	1726	0	0	0
T106	0	7	0	0

gen_edn_if_asserts[4].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200749460	585931	0	326
T1	134184	1263	0	2
T2	2162	617	0	0
T3	4436	15	0	0
T4	906	444	0	0
T13	0	0	0	2
T18	1076	569	0	0
T23	1366	42	0	0
T24	286141	1335	0	2
T25	2050	19	0	0
T26	29936	2227	0	2
T27	4152	28	0	0
T28	0	0	0	2
T102	0	0	0	2
T112	0	0	0	2
T126	0	0	0	2
T131	0	0	0	2
T132	0	0	0	2

gen_edn_if_asserts[4].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200749460	4542	0	98
T8	2637	0	0	0
T16	2609	0	0	0
T17	927	0	0	0
T27	4152	19	0	1
T30	2589	11	0	1
T33	0	4	0	0
T34	0	4	0	0
T60	0	4	0	0
T72	0	4	0	1
T94	2217	0	0	0
T98	2083	0	0	0
T102	1726	0	0	0
T106	1706	0	0	0
T112	296604	0	0	0
T114	0	3	0	1
T115	0	3	0	1
T116	0	3	0	1
T117	0	3	0	1
T118	0	0	0	1
T120	0	0	0	1
T137	0	0	0	1

gen_edn_if_asserts[4].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200749460	200562176	0	0
T1	134184	134174	0	0
T2	2162	2009	0	0
T3	4436	4378	0	0
T4	906	753	0	0
T18	1076	950	0	0
T23	1366	1305	0	0
T24	286141	286130	0	0
T25	2050	1954	0	0
T26	29936	29441	0	0
T27	4152	4065	0	0

gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200749460	161759	0	0
T2	2162	635	0	0
T3	4436	0	0	0
T4	906	461	0	0
T5	0	411	0	0
T13	0	7381	0	0
T17	0	24	0	0
T18	1076	612	0	0
T23	1366	0	0	0
T24	286141	0	0	0
T25	2050	0	0	0
T26	29936	0	0	0
T27	4152	0	0	0
T79	0	292	0	0
T98	0	1100	0	0
T101	0	397	0	0
T102	1726	0	0	0
T106	0	7	0	0

gen_edn_if_asserts[5].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200749460	585931	0	326
T1	134184	1263	0	2
T2	2162	617	0	0
T3	4436	15	0	0
T4	906	444	0	0
T13	0	0	0	2
T18	1076	569	0	0
T23	1366	42	0	0
T24	286141	1335	0	2
T25	2050	19	0	0
T26	29936	2227	0	2
T27	4152	28	0	0
T28	0	0	0	2
T102	0	0	0	2
T112	0	0	0	2
T126	0	0	0	2
T131	0	0	0	2
T132	0	0	0	2

gen_edn_if_asserts[5].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200749460	2186	0	84
T13	22305	0	0	0
T17	927	0	0	0
T30	2589	38	0	1
T60	1132	0	0	0
T94	2217	0	0	0
T98	2083	0	0	0
T103	1838	0	0	0
T106	1706	0	0	0
T112	296604	0	0	0
T113	0	53	0	1
T114	0	3	0	1
T115	0	3	0	1
T116	0	63	0	1
T117	0	3	0	1
T125	24951	0	0	0
T137	0	5	0	1
T138	0	34	0	1
T139	0	23	0	1
T140	0	3	0	1

gen_edn_if_asserts[5].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200749460	200562176	0	0
T1	134184	134174	0	0
T2	2162	2009	0	0
T3	4436	4378	0	0
T4	906	753	0	0
T18	1076	950	0	0
T23	1366	1305	0	0
T24	286141	286130	0	0
T25	2050	1954	0	0
T26	29936	29441	0	0
T27	4152	4065	0	0

gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200749460	161759	0	0
T2	2162	635	0	0
T3	4436	0	0	0
T4	906	461	0	0
T5	0	411	0	0
T13	0	7381	0	0
T17	0	24	0	0
T18	1076	612	0	0
T23	1366	0	0	0
T24	286141	0	0	0
T25	2050	0	0	0
T26	29936	0	0	0
T27	4152	0	0	0
T79	0	292	0	0
T98	0	1100	0	0
T101	0	397	0	0
T102	1726	0	0	0
T106	0	7	0	0

gen_edn_if_asserts[6].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200749460	585931	0	326
T1	134184	1263	0	2
T2	2162	617	0	0
T3	4436	15	0	0
T4	906	444	0	0
T13	0	0	0	2
T18	1076	569	0	0
T23	1366	42	0	0
T24	286141	1335	0	2
T25	2050	19	0	0
T26	29936	2227	0	2
T27	4152	28	0	0
T28	0	0	0	2
T102	0	0	0	2
T112	0	0	0	2
T126	0	0	0	2
T131	0	0	0	2
T132	0	0	0	2

gen_edn_if_asserts[6].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200749460	2400	0	72
T13	22305	0	0	0
T17	927	0	0	0
T28	0	1	0	0
T29	0	4	0	1
T30	2589	3	0	1
T56	0	4	0	0
T60	1132	0	0	0
T94	2217	0	0	0
T98	2083	0	0	0
T103	1838	0	0	0
T106	1706	0	0	0
T112	296604	0	0	0
T115	0	11	0	1
T117	0	3	0	1
T118	0	3	0	1
T120	0	52	0	1
T121	0	48	0	1
T122	0	13	0	1
T125	24951	0	0	0
T141	0	0	0	1
T142	0	0	0	1

gen_edn_if_asserts[6].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200749460	200562176	0	0
T1	134184	134174	0	0
T2	2162	2009	0	0
T3	4436	4378	0	0
T4	906	753	0	0
T18	1076	950	0	0
T23	1366	1305	0	0
T24	286141	286130	0	0
T25	2050	1954	0	0
T26	29936	29441	0	0
T27	4152	4065	0	0

gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200749460	161759	0	0
T2	2162	635	0	0
T3	4436	0	0	0
T4	906	461	0	0
T5	0	411	0	0
T13	0	7381	0	0
T17	0	24	0	0
T18	1076	612	0	0
T23	1366	0	0	0
T24	286141	0	0	0
T25	2050	0	0	0
T26	29936	0	0	0
T27	4152	0	0	0
T79	0	292	0	0
T98	0	1100	0	0
T101	0	397	0	0
T102	1726	0	0	0
T106	0	7	0	0