Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44		83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	201249744	8991358	0	0
boot_gen_cmd_rd_A	201249744	43148	0	0
boot_ins_cmd_rd_A	201249744	49792	0	0
ctrl_rd_A	201249744	43699	0	0
err_code_test_rd_A	201249744	49432	0	0
intr_enable_rd_A	201249744	50332	0	0
max_num_reqs_between_reseeds_rd_A	201249744	43645	0	0
regwen_rd_A	201249744	51243	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	201249744	8991358	0	0
T1	134184	56038	0	0
T2	2162	0	0	0
T3	4436	0	0	0
T4	906	0	0	0
T18	1076	0	0	0
T23	1366	0	0	0
T24	286141	177754	0	0
T25	2050	0	0	0
T26	29936	0	0	0
T27	4152	0	0	0
T112	0	99918	0	0
T126	0	137217	0	0
T131	0	80403	0	0
T132	0	143071	0	0
T189	0	286567	0	0
T190	0	265278	0	0
T191	0	114222	0	0
T192	0	108538	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	201249744	43148	0	0
T5	2251	0	0	0
T13	22305	0	0	0
T60	1132	0	0	0
T98	2083	0	0	0
T103	1838	0	0	0
T106	1706	0	0	0
T112	296604	2909	0	0
T113	1937	0	0	0
T125	24951	0	0	0
T126	240929	0	0	0
T193	0	1225	0	0
T194	0	2135	0	0
T195	0	5003	0	0
T196	0	4163	0	0
T197	0	7867	0	0
T198	0	2919	0	0
T199	0	3666	0	0
T200	0	810	0	0
T201	0	2579	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	201249744	49792	0	0
T5	2251	0	0	0
T13	22305	0	0	0
T60	1132	0	0	0
T98	2083	0	0	0
T103	1838	0	0	0
T106	1706	0	0	0
T112	296604	3190	0	0
T113	1937	0	0	0
T125	24951	0	0	0
T126	240929	0	0	0
T193	0	1298	0	0
T194	0	2650	0	0
T195	0	5846	0	0
T196	0	4420	0	0
T197	0	9612	0	0
T198	0	3228	0	0
T199	0	4251	0	0
T200	0	845	0	0
T201	0	3261	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	201249744	43699	0	0
T5	2251	0	0	0
T13	22305	0	0	0
T53	0	3	0	0
T60	1132	0	0	0
T98	2083	0	0	0
T103	1838	10	0	0
T105	0	1	0	0
T106	1706	0	0	0
T111	0	4	0	0
T112	296604	3125	0	0
T113	1937	0	0	0
T125	24951	0	0	0
T126	240929	0	0	0
T193	0	1270	0	0
T194	0	2256	0	0
T195	0	4915	0	0
T202	0	2	0	0
T203	0	3	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	201249744	49432	0	0
T5	2251	0	0	0
T13	22305	0	0	0
T60	1132	0	0	0
T98	2083	0	0	0
T103	1838	0	0	0
T106	1706	0	0	0
T112	296604	3139	0	0
T113	1937	0	0	0
T125	24951	0	0	0
T126	240929	0	0	0
T193	0	1282	0	0
T194	0	2551	0	0
T195	0	5899	0	0
T196	0	4324	0	0
T197	0	9638	0	0
T198	0	3125	0	0
T199	0	4206	0	0
T200	0	1015	0	0
T201	0	3334	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	201249744	50332	0	0
T5	2251	0	0	0
T13	22305	0	0	0
T60	1132	0	0	0
T98	2083	0	0	0
T103	1838	0	0	0
T106	1706	0	0	0
T112	296604	3237	0	0
T113	1937	0	0	0
T125	24951	0	0	0
T126	240929	0	0	0
T128	0	51	0	0
T193	0	1447	0	0
T194	0	2528	0	0
T195	0	5227	0	0
T196	0	4495	0	0
T197	0	9152	0	0
T203	0	23	0	0
T204	0	98	0	0
T205	0	18	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	201249744	43645	0	0
T5	2251	0	0	0
T13	22305	0	0	0
T60	1132	0	0	0
T98	2083	0	0	0
T103	1838	0	0	0
T106	1706	0	0	0
T112	296604	2799	0	0
T113	1937	0	0	0
T125	24951	0	0	0
T126	240929	0	0	0
T193	0	1263	0	0
T194	0	2336	0	0
T195	0	5173	0	0
T196	0	4052	0	0
T197	0	8180	0	0
T198	0	2532	0	0
T199	0	3558	0	0
T200	0	920	0	0
T201	0	2628	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	201249744	51243	0	0
T5	2251	0	0	0
T13	22305	0	0	0
T60	1132	0	0	0
T98	2083	0	0	0
T103	1838	0	0	0
T106	1706	0	0	0
T112	296604	3375	0	0
T113	1937	0	0	0
T125	24951	0	0	0
T126	240929	0	0	0
T193	0	1451	0	0
T194	0	2668	0	0
T195	0	5874	0	0
T196	0	4786	0	0
T197	0	9638	0	0
T198	0	3041	0	0
T199	0	4054	0	0
T200	0	976	0	0
T201	0	3526	0	0