Unified Coverage Report :: Module :: edn

Module : edn

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	94.44		83.33	100.00			100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.06	98.24	93.80	97.07	84.88	96.62	99.77

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
edn_csr_assert	100.00						100.00
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_edn_core	93.04	99.92	92.46	82.84	84.88	99.28	98.88
u_edn_cov_if	25.00	50.00	0.00
u_reg	96.95	95.02	97.57	100.00		92.16	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Cond Coverage for Module : edn

	Total	Covered	Percent
Conditions	6	5	83.33
Logical	6	5	83.33
Non-Logical	0	0
Event	0	0

 LINE       98
 EXPRESSION (alert[0] || intg_err_alert[0])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T26,T27,T28

 LINE       98
 EXPRESSION (alert[1] || intg_err_alert[1])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T15,T16,T17
1	0	Covered	T1,T3,T14

---

Toggle Coverage for Module : edn

	Total	Covered	Percent
Totals	69	69	100.00
Total Bits	1172	1172	100.00
Total Bits 0->1	586	586	100.00
Total Bits 1->0	586	586	100.00

Ports	69	69	100.00
Port Bits	1172	1172	100.00
Port Bits 0->1	586	586	100.00
Port Bits 1->0	586	586	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T20,T4,T114	Yes	T20,T4,T114	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T2,T3,T20	Yes	T2,T3,T20	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T20,T4	Yes	T1,T20,T4	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T104,T115,T116	Yes	T104,T115,T116	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T4,T7	Yes	T1,T2,T20	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i[0].edn_req	Yes	Yes	T2,T3,T20	Yes	T2,T3,T20	INPUT
edn_i[1].edn_req	Yes	Yes	T1,T20,T7	Yes	T1,T20,T7	INPUT
edn_i[2].edn_req	Yes	Yes	T20,T117,T118	Yes	T20,T117,T118	INPUT
edn_i[3].edn_req	Yes	Yes	T20,T7,T26	Yes	T20,T7,T26	INPUT
edn_i[4].edn_req	Yes	Yes	T20,T25,T8	Yes	T20,T25,T8	INPUT
edn_i[5].edn_req	Yes	Yes	T20,T24,T26	Yes	T20,T24,T26	INPUT
edn_i[6].edn_req	Yes	Yes	T8,T117,T118	Yes	T8,T117,T118	INPUT
edn_o[0].edn_bus[31:0]	Yes	Yes	T2,T20,T4	Yes	T2,T20,T4	OUTPUT
edn_o[0].edn_fips	Yes	Yes	T2,T3,T20	Yes	T2,T3,T20	OUTPUT
edn_o[0].edn_ack	Yes	Yes	T2,T3,T20	Yes	T2,T3,T20	OUTPUT
edn_o[1].edn_bus[31:0]	Yes	Yes	T20,T7,T5	Yes	T20,T7,T5	OUTPUT
edn_o[1].edn_fips	Yes	Yes	T7,T5,T119	Yes	T20,T7,T5	OUTPUT
edn_o[1].edn_ack	Yes	Yes	T20,T7,T8	Yes	T20,T7,T8	OUTPUT
edn_o[2].edn_bus[31:0]	Yes	Yes	T20,T118,T69	Yes	T20,T117,T118	OUTPUT
edn_o[2].edn_fips	Yes	Yes	T20,T118,T120	Yes	T20,T117,T118	OUTPUT
edn_o[2].edn_ack	Yes	Yes	T20,T117,T118	Yes	T20,T117,T118	OUTPUT
edn_o[3].edn_bus[31:0]	Yes	Yes	T20,T7,T26	Yes	T20,T7,T26	OUTPUT
edn_o[3].edn_fips	Yes	Yes	T20,T26,T6	Yes	T20,T7,T26	OUTPUT
edn_o[3].edn_ack	Yes	Yes	T20,T7,T26	Yes	T20,T7,T26	OUTPUT
edn_o[4].edn_bus[31:0]	Yes	Yes	T20,T25,T8	Yes	T20,T25,T8	OUTPUT
edn_o[4].edn_fips	Yes	Yes	T8,T118,T121	Yes	T8,T74,T118	OUTPUT
edn_o[4].edn_ack	Yes	Yes	T20,T25,T8	Yes	T20,T25,T8	OUTPUT
edn_o[5].edn_bus[31:0]	Yes	Yes	T20,T26,T118	Yes	T20,T24,T26	OUTPUT
edn_o[5].edn_fips	Yes	Yes	T122,T123,T124	Yes	T24,T26,T118	OUTPUT
edn_o[5].edn_ack	Yes	Yes	T20,T24,T26	Yes	T20,T24,T26	OUTPUT
edn_o[6].edn_bus[31:0]	Yes	Yes	T8,T121,T122	Yes	T8,T117,T118	OUTPUT
edn_o[6].edn_fips	Yes	Yes	T122,T125,T126	Yes	T8,T122,T123	OUTPUT
edn_o[6].edn_ack	Yes	Yes	T8,T117,T118	Yes	T8,T117,T118	OUTPUT
csrng_cmd_o.genbits_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_bus[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_i.genbits_bus[127:0]	Yes	Yes	T2,T20,T4	Yes	T2,T20,T4	INPUT
csrng_cmd_i.genbits_fips	Yes	Yes	T2,T20,T4	Yes	T2,T20,T4	INPUT
csrng_cmd_i.genbits_valid	Yes	Yes	T2,T3,T20	Yes	T2,T3,T20	INPUT
csrng_cmd_i.csrng_rsp_sts[2:0]	Yes	Yes	T26,T27,T99	Yes	T26,T27,T99	INPUT
csrng_cmd_i.csrng_rsp_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_req_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T26,T127,T128	Yes	T26,T127,T128	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T26,T127,T128	Yes	T26,T127,T128	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T1,T3,T14	Yes	T1,T3,T14	OUTPUT
intr_edn_cmd_req_done_o	Yes	Yes	T4,T103,T104	Yes	T4,T103,T104	OUTPUT
intr_edn_fatal_err_o	Yes	Yes	T3,T4,T103	Yes	T3,T4,T103	OUTPUT

*Tests covering at least one bit in the range

---

Assert Coverage for Module : edn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	47	47	100.00	47	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	47	47	100.00	47	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxKnownO_A	247498109	247330593	0	0
CsrngAppIfOut_A	247498109	247330593	0	0
FpvSecCmCntAlertCheck_A	247498109	114	0	0
FpvSecCmGenCmdFifoRptrCheck_A	247498109	70	0	0
FpvSecCmGenCmdFifoWptrCheck_A	247498109	70	0	0
FpvSecCmMainFsmCheck_A	247498109	70	0	0
FpvSecCmRegWeOnehotCheck_A	247498109	70	0	0
FpvSecCmResCmdFifoRptrCheck_A	247498109	70	0	0
FpvSecCmResCmdFifoWptrCheck_A	247498109	70	0	0
IntrEdnCmdReqDoneKnownO_A	247498109	247330593	0	0
TlAReadyKnownO_A	247498109	247330593	0	0
TlDValidKnownO_A	247498109	247330593	0	0
gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A	247498109	70	0	0
gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A	247498109	70	0	0
gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A	247498109	70	0	0
gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A	247498109	70	0	0
gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A	247498109	70	0	0
gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A	247498109	70	0	0
gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A	247498109	70	0	0
gen_edn_if_asserts[0].EdnDataStableDisable_A	247498109	566176	0	332
gen_edn_if_asserts[0].EdnDataStable_A	247498109	23264	0	333
gen_edn_if_asserts[0].EdnEndPointOut_A	247498109	247330593	0	0
gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A	247498109	141952	0	0
gen_edn_if_asserts[1].EdnDataStableDisable_A	247498109	566176	0	332
gen_edn_if_asserts[1].EdnDataStable_A	247498109	6067	0	127
gen_edn_if_asserts[1].EdnEndPointOut_A	247498109	247330593	0	0
gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A	247498109	141952	0	0
gen_edn_if_asserts[2].EdnDataStableDisable_A	247498109	566176	0	332
gen_edn_if_asserts[2].EdnDataStable_A	247498109	3740	0	109
gen_edn_if_asserts[2].EdnEndPointOut_A	247498109	247330593	0	0
gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A	247498109	141952	0	0
gen_edn_if_asserts[3].EdnDataStableDisable_A	247498109	566176	0	332
gen_edn_if_asserts[3].EdnDataStable_A	247498109	2218	0	95
gen_edn_if_asserts[3].EdnEndPointOut_A	247498109	247330593	0	0
gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A	247498109	141952	0	0
gen_edn_if_asserts[4].EdnDataStableDisable_A	247498109	566176	0	332
gen_edn_if_asserts[4].EdnDataStable_A	247498109	6685	0	97
gen_edn_if_asserts[4].EdnEndPointOut_A	247498109	247330593	0	0
gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A	247498109	141952	0	0
gen_edn_if_asserts[5].EdnDataStableDisable_A	247498109	566176	0	332
gen_edn_if_asserts[5].EdnDataStable_A	247498109	3868	0	81
gen_edn_if_asserts[5].EdnEndPointOut_A	247498109	247330593	0	0
gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A	247498109	141952	0	0
gen_edn_if_asserts[6].EdnDataStableDisable_A	247498109	566176	0	332
gen_edn_if_asserts[6].EdnDataStable_A	247498109	2825	0	80
gen_edn_if_asserts[6].EdnEndPointOut_A	247498109	247330593	0	0
gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A	247498109	141952	0	0

AlertTxKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	247498109	247330593	0	0
T1	1674	1502	0	0
T2	2896	2817	0	0
T3	984	838	0	0
T4	23695	22720	0	0
T7	2265	2188	0	0
T20	5605	5525	0	0
T21	1007	913	0	0
T22	1913	1824	0	0
T23	2599	2536	0	0
T24	680	584	0	0

CsrngAppIfOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	247498109	247330593	0	0
T1	1674	1502	0	0
T2	2896	2817	0	0
T3	984	838	0	0
T4	23695	22720	0	0
T7	2265	2188	0	0
T20	5605	5525	0	0
T21	1007	913	0	0
T22	1913	1824	0	0
T23	2599	2536	0	0
T24	680	584	0	0

FpvSecCmCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	247498109	114	0	0
T5	2062	0	0	0
T6	889	1	0	0
T8	2130	0	0	0
T11	1469	0	0	0
T12	1826	1	0	0
T13	0	1	0	0
T15	0	10	0	0
T43	0	1	0	0
T66	0	1	0	0
T72	0	1	0	0
T74	1105	0	0	0
T101	0	1	0	0
T104	373496	0	0	0
T105	2905	0	0	0
T127	1614	0	0	0
T129	0	1	0	0
T130	0	1	0	0
T131	2377	0	0	0

FpvSecCmGenCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	247498109	70	0	0
T15	32248	10	0	0
T16	0	20	0	0
T17	0	10	0	0
T40	2150	0	0	0
T132	0	20	0	0
T133	0	10	0	0
T134	1404	0	0	0
T135	2112	0	0	0
T136	919593	0	0	0
T137	4614	0	0	0
T138	3450	0	0	0
T139	1103	0	0	0
T140	2700	0	0	0
T141	2016	0	0	0

FpvSecCmGenCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	247498109	70	0	0
T15	32248	10	0	0
T16	0	20	0	0
T17	0	10	0	0
T40	2150	0	0	0
T132	0	20	0	0
T133	0	10	0	0
T134	1404	0	0	0
T135	2112	0	0	0
T136	919593	0	0	0
T137	4614	0	0	0
T138	3450	0	0	0
T139	1103	0	0	0
T140	2700	0	0	0
T141	2016	0	0	0

FpvSecCmMainFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	247498109	70	0	0
T15	32248	10	0	0
T16	0	20	0	0
T17	0	10	0	0
T40	2150	0	0	0
T132	0	20	0	0
T133	0	10	0	0
T134	1404	0	0	0
T135	2112	0	0	0
T136	919593	0	0	0
T137	4614	0	0	0
T138	3450	0	0	0
T139	1103	0	0	0
T140	2700	0	0	0
T141	2016	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	247498109	70	0	0
T15	32248	10	0	0
T16	0	20	0	0
T17	0	10	0	0
T40	2150	0	0	0
T132	0	20	0	0
T133	0	10	0	0
T134	1404	0	0	0
T135	2112	0	0	0
T136	919593	0	0	0
T137	4614	0	0	0
T138	3450	0	0	0
T139	1103	0	0	0
T140	2700	0	0	0
T141	2016	0	0	0

FpvSecCmResCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	247498109	70	0	0
T15	32248	10	0	0
T16	0	20	0	0
T17	0	10	0	0
T40	2150	0	0	0
T132	0	20	0	0
T133	0	10	0	0
T134	1404	0	0	0
T135	2112	0	0	0
T136	919593	0	0	0
T137	4614	0	0	0
T138	3450	0	0	0
T139	1103	0	0	0
T140	2700	0	0	0
T141	2016	0	0	0

FpvSecCmResCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	247498109	70	0	0
T15	32248	10	0	0
T16	0	20	0	0
T17	0	10	0	0
T40	2150	0	0	0
T132	0	20	0	0
T133	0	10	0	0
T134	1404	0	0	0
T135	2112	0	0	0
T136	919593	0	0	0
T137	4614	0	0	0
T138	3450	0	0	0
T139	1103	0	0	0
T140	2700	0	0	0
T141	2016	0	0	0

IntrEdnCmdReqDoneKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	247498109	247330593	0	0
T1	1674	1502	0	0
T2	2896	2817	0	0
T3	984	838	0	0
T4	23695	22720	0	0
T7	2265	2188	0	0
T20	5605	5525	0	0
T21	1007	913	0	0
T22	1913	1824	0	0
T23	2599	2536	0	0
T24	680	584	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	247498109	247330593	0	0
T1	1674	1502	0	0
T2	2896	2817	0	0
T3	984	838	0	0
T4	23695	22720	0	0
T7	2265	2188	0	0
T20	5605	5525	0	0
T21	1007	913	0	0
T22	1913	1824	0	0
T23	2599	2536	0	0
T24	680	584	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	247498109	247330593	0	0
T1	1674	1502	0	0
T2	2896	2817	0	0
T3	984	838	0	0
T4	23695	22720	0	0
T7	2265	2188	0	0
T20	5605	5525	0	0
T21	1007	913	0	0
T22	1913	1824	0	0
T23	2599	2536	0	0
T24	680	584	0	0

gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	247498109	70	0	0
T15	32248	10	0	0
T16	0	20	0	0
T17	0	10	0	0
T40	2150	0	0	0
T132	0	20	0	0
T133	0	10	0	0
T134	1404	0	0	0
T135	2112	0	0	0
T136	919593	0	0	0
T137	4614	0	0	0
T138	3450	0	0	0
T139	1103	0	0	0
T140	2700	0	0	0
T141	2016	0	0	0

gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	247498109	70	0	0
T15	32248	10	0	0
T16	0	20	0	0
T17	0	10	0	0
T40	2150	0	0	0
T132	0	20	0	0
T133	0	10	0	0
T134	1404	0	0	0
T135	2112	0	0	0
T136	919593	0	0	0
T137	4614	0	0	0
T138	3450	0	0	0
T139	1103	0	0	0
T140	2700	0	0	0
T141	2016	0	0	0

gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	247498109	70	0	0
T15	32248	10	0	0
T16	0	20	0	0
T17	0	10	0	0
T40	2150	0	0	0
T132	0	20	0	0
T133	0	10	0	0
T134	1404	0	0	0
T135	2112	0	0	0
T136	919593	0	0	0
T137	4614	0	0	0
T138	3450	0	0	0
T139	1103	0	0	0
T140	2700	0	0	0
T141	2016	0	0	0

gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	247498109	70	0	0
T15	32248	10	0	0
T16	0	20	0	0
T17	0	10	0	0
T40	2150	0	0	0
T132	0	20	0	0
T133	0	10	0	0
T134	1404	0	0	0
T135	2112	0	0	0
T136	919593	0	0	0
T137	4614	0	0	0
T138	3450	0	0	0
T139	1103	0	0	0
T140	2700	0	0	0
T141	2016	0	0	0

gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	247498109	70	0	0
T15	32248	10	0	0
T16	0	20	0	0
T17	0	10	0	0
T40	2150	0	0	0
T132	0	20	0	0
T133	0	10	0	0
T134	1404	0	0	0
T135	2112	0	0	0
T136	919593	0	0	0
T137	4614	0	0	0
T138	3450	0	0	0
T139	1103	0	0	0
T140	2700	0	0	0
T141	2016	0	0	0

gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	247498109	70	0	0
T15	32248	10	0	0
T16	0	20	0	0
T17	0	10	0	0
T40	2150	0	0	0
T132	0	20	0	0
T133	0	10	0	0
T134	1404	0	0	0
T135	2112	0	0	0
T136	919593	0	0	0
T137	4614	0	0	0
T138	3450	0	0	0
T139	1103	0	0	0
T140	2700	0	0	0
T141	2016	0	0	0

gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	247498109	70	0	0
T15	32248	10	0	0
T16	0	20	0	0
T17	0	10	0	0
T40	2150	0	0	0
T132	0	20	0	0
T133	0	10	0	0
T134	1404	0	0	0
T135	2112	0	0	0
T136	919593	0	0	0
T137	4614	0	0	0
T138	3450	0	0	0
T139	1103	0	0	0
T140	2700	0	0	0
T141	2016	0	0	0

gen_edn_if_asserts[0].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	247498109	566176	0	332
T1	1674	1041	0	0
T2	2896	48	0	0
T3	984	333	0	0
T4	23695	3612	0	0
T7	2265	1237	0	2
T20	5605	40	0	0
T21	1007	14	0	0
T22	1913	19	0	0
T23	2599	22	0	0
T24	680	63	0	0
T31	0	0	0	2
T104	0	0	0	2
T115	0	0	0	2
T116	0	0	0	2
T127	0	0	0	2
T128	0	0	0	2
T142	0	0	0	2
T143	0	0	0	2
T144	0	0	0	2

gen_edn_if_asserts[0].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	247498109	23264	0	333
T2	2896	11	0	1
T3	984	1	0	0
T4	23695	16	0	0
T7	2265	0	0	0
T20	5605	35	0	1
T21	1007	3	0	1
T22	1913	3	0	1
T23	2599	3	0	1
T24	680	0	0	0
T29	0	22	0	1
T103	0	6	0	1
T114	1884	3	0	1
T145	0	0	0	1
T146	0	0	0	1

gen_edn_if_asserts[0].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	247498109	247330593	0	0
T1	1674	1502	0	0
T2	2896	2817	0	0
T3	984	838	0	0
T4	23695	22720	0	0
T7	2265	2188	0	0
T20	5605	5525	0	0
T21	1007	913	0	0
T22	1913	1824	0	0
T23	2599	2536	0	0
T24	680	584	0	0

gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	247498109	141952	0	0
T1	1674	625	0	0
T2	2896	0	0	0
T3	984	379	0	0
T4	23695	0	0	0
T5	0	1112	0	0
T6	0	354	0	0
T7	2265	0	0	0
T12	0	1116	0	0
T14	0	352	0	0
T20	5605	0	0	0
T21	1007	0	0	0
T22	1913	0	0	0
T23	2599	0	0	0
T24	680	0	0	0
T27	0	1112	0	0
T71	0	1083	0	0
T105	0	1112	0	0
T109	0	7	0	0

gen_edn_if_asserts[1].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	247498109	566176	0	332
T1	1674	1041	0	0
T2	2896	48	0	0
T3	984	333	0	0
T4	23695	3612	0	0
T7	2265	1237	0	2
T20	5605	40	0	0
T21	1007	14	0	0
T22	1913	19	0	0
T23	2599	22	0	0
T24	680	63	0	0
T31	0	0	0	2
T104	0	0	0	2
T115	0	0	0	2
T116	0	0	0	2
T127	0	0	0	2
T128	0	0	0	2
T142	0	0	0	2
T143	0	0	0	2
T144	0	0	0	2

gen_edn_if_asserts[1].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	247498109	6067	0	127
T4	23695	0	0	0
T7	2265	4	0	0
T8	0	3	0	1
T19	0	28	0	1
T20	5605	19	0	1
T21	1007	0	0	0
T22	1913	0	0	0
T23	2599	0	0	0
T24	680	0	0	0
T29	2172	0	0	0
T103	9042	0	0	0
T114	1884	0	0	0
T118	0	3	0	1
T119	0	16	0	1
T122	0	45	0	1
T131	0	6	0	1
T147	0	15	0	1
T148	0	3	0	1
T149	0	0	0	1

gen_edn_if_asserts[1].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	247498109	247330593	0	0
T1	1674	1502	0	0
T2	2896	2817	0	0
T3	984	838	0	0
T4	23695	22720	0	0
T7	2265	2188	0	0
T20	5605	5525	0	0
T21	1007	913	0	0
T22	1913	1824	0	0
T23	2599	2536	0	0
T24	680	584	0	0

gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	247498109	141952	0	0
T1	1674	625	0	0
T2	2896	0	0	0
T3	984	379	0	0
T4	23695	0	0	0
T5	0	1112	0	0
T6	0	354	0	0
T7	2265	0	0	0
T12	0	1116	0	0
T14	0	352	0	0
T20	5605	0	0	0
T21	1007	0	0	0
T22	1913	0	0	0
T23	2599	0	0	0
T24	680	0	0	0
T27	0	1112	0	0
T71	0	1083	0	0
T105	0	1112	0	0
T109	0	7	0	0

gen_edn_if_asserts[2].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	247498109	566176	0	332
T1	1674	1041	0	0
T2	2896	48	0	0
T3	984	333	0	0
T4	23695	3612	0	0
T7	2265	1237	0	2
T20	5605	40	0	0
T21	1007	14	0	0
T22	1913	19	0	0
T23	2599	22	0	0
T24	680	63	0	0
T31	0	0	0	2
T104	0	0	0	2
T115	0	0	0	2
T116	0	0	0	2
T127	0	0	0	2
T128	0	0	0	2
T142	0	0	0	2
T143	0	0	0	2
T144	0	0	0	2

gen_edn_if_asserts[2].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	247498109	3740	0	109
T4	23695	0	0	0
T7	2265	0	0	0
T20	5605	20	0	1
T21	1007	0	0	0
T22	1913	0	0	0
T23	2599	0	0	0
T24	680	0	0	0
T29	2172	0	0	0
T69	0	4	0	0
T103	9042	0	0	0
T114	1884	0	0	0
T117	0	5	0	1
T118	0	16	0	1
T122	0	3	0	1
T123	0	13	0	1
T124	0	7	0	1
T149	0	11	0	1
T150	0	3	0	1
T151	0	3	0	1
T152	0	0	0	1

gen_edn_if_asserts[2].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	247498109	247330593	0	0
T1	1674	1502	0	0
T2	2896	2817	0	0
T3	984	838	0	0
T4	23695	22720	0	0
T7	2265	2188	0	0
T20	5605	5525	0	0
T21	1007	913	0	0
T22	1913	1824	0	0
T23	2599	2536	0	0
T24	680	584	0	0

gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	247498109	141952	0	0
T1	1674	625	0	0
T2	2896	0	0	0
T3	984	379	0	0
T4	23695	0	0	0
T5	0	1112	0	0
T6	0	354	0	0
T7	2265	0	0	0
T12	0	1116	0	0
T14	0	352	0	0
T20	5605	0	0	0
T21	1007	0	0	0
T22	1913	0	0	0
T23	2599	0	0	0
T24	680	0	0	0
T27	0	1112	0	0
T71	0	1083	0	0
T105	0	1112	0	0
T109	0	7	0	0

gen_edn_if_asserts[3].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	247498109	566176	0	332
T1	1674	1041	0	0
T2	2896	48	0	0
T3	984	333	0	0
T4	23695	3612	0	0
T7	2265	1237	0	2
T20	5605	40	0	0
T21	1007	14	0	0
T22	1913	19	0	0
T23	2599	22	0	0
T24	680	63	0	0
T31	0	0	0	2
T104	0	0	0	2
T115	0	0	0	2
T116	0	0	0	2
T127	0	0	0	2
T128	0	0	0	2
T142	0	0	0	2
T143	0	0	0	2
T144	0	0	0	2

gen_edn_if_asserts[3].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	247498109	2218	0	95
T4	23695	0	0	0
T6	0	1	0	0
T7	2265	4	0	0
T20	5605	24	0	1
T21	1007	0	0	0
T22	1913	0	0	0
T23	2599	0	0	0
T24	680	0	0	0
T26	0	4	0	0
T29	2172	0	0	0
T69	0	4	0	1
T103	9042	0	0	0
T109	0	1	0	0
T114	1884	0	0	0
T118	0	3	0	1
T122	0	0	0	1
T124	0	0	0	1
T151	0	0	0	1
T153	0	3	0	1
T154	0	7	0	1
T155	0	3	0	1
T156	0	0	0	1

gen_edn_if_asserts[3].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	247498109	247330593	0	0
T1	1674	1502	0	0
T2	2896	2817	0	0
T3	984	838	0	0
T4	23695	22720	0	0
T7	2265	2188	0	0
T20	5605	5525	0	0
T21	1007	913	0	0
T22	1913	1824	0	0
T23	2599	2536	0	0
T24	680	584	0	0

gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	247498109	141952	0	0
T1	1674	625	0	0
T2	2896	0	0	0
T3	984	379	0	0
T4	23695	0	0	0
T5	0	1112	0	0
T6	0	354	0	0
T7	2265	0	0	0
T12	0	1116	0	0
T14	0	352	0	0
T20	5605	0	0	0
T21	1007	0	0	0
T22	1913	0	0	0
T23	2599	0	0	0
T24	680	0	0	0
T27	0	1112	0	0
T71	0	1083	0	0
T105	0	1112	0	0
T109	0	7	0	0

gen_edn_if_asserts[4].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	247498109	566176	0	332
T1	1674	1041	0	0
T2	2896	48	0	0
T3	984	333	0	0
T4	23695	3612	0	0
T7	2265	1237	0	2
T20	5605	40	0	0
T21	1007	14	0	0
T22	1913	19	0	0
T23	2599	22	0	0
T24	680	63	0	0
T31	0	0	0	2
T104	0	0	0	2
T115	0	0	0	2
T116	0	0	0	2
T127	0	0	0	2
T128	0	0	0	2
T142	0	0	0	2
T143	0	0	0	2
T144	0	0	0	2

gen_edn_if_asserts[4].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	247498109	6685	0	97
T4	23695	0	0	0
T7	2265	0	0	0
T8	0	15	0	1
T20	5605	3	0	1
T21	1007	0	0	0
T22	1913	0	0	0
T23	2599	0	0	0
T24	680	0	0	0
T25	0	4	0	0
T29	2172	0	0	0
T74	0	3	0	1
T103	9042	0	0	0
T107	0	1	0	0
T114	1884	0	0	0
T118	0	25	0	1
T121	0	55	0	1
T123	0	0	0	1
T149	0	3	0	1
T151	0	0	0	1
T156	0	3	0	1
T157	0	6	0	1

gen_edn_if_asserts[4].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	247498109	247330593	0	0
T1	1674	1502	0	0
T2	2896	2817	0	0
T3	984	838	0	0
T4	23695	22720	0	0
T7	2265	2188	0	0
T20	5605	5525	0	0
T21	1007	913	0	0
T22	1913	1824	0	0
T23	2599	2536	0	0
T24	680	584	0	0

gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	247498109	141952	0	0
T1	1674	625	0	0
T2	2896	0	0	0
T3	984	379	0	0
T4	23695	0	0	0
T5	0	1112	0	0
T6	0	354	0	0
T7	2265	0	0	0
T12	0	1116	0	0
T14	0	352	0	0
T20	5605	0	0	0
T21	1007	0	0	0
T22	1913	0	0	0
T23	2599	0	0	0
T24	680	0	0	0
T27	0	1112	0	0
T71	0	1083	0	0
T105	0	1112	0	0
T109	0	7	0	0

gen_edn_if_asserts[5].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	247498109	566176	0	332
T1	1674	1041	0	0
T2	2896	48	0	0
T3	984	333	0	0
T4	23695	3612	0	0
T7	2265	1237	0	2
T20	5605	40	0	0
T21	1007	14	0	0
T22	1913	19	0	0
T23	2599	22	0	0
T24	680	63	0	0
T31	0	0	0	2
T104	0	0	0	2
T115	0	0	0	2
T116	0	0	0	2
T127	0	0	0	2
T128	0	0	0	2
T142	0	0	0	2
T143	0	0	0	2
T144	0	0	0	2

gen_edn_if_asserts[5].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	247498109	3868	0	81
T4	23695	0	0	0
T7	2265	0	0	0
T20	5605	3	0	1
T21	1007	0	0	0
T22	1913	0	0	0
T23	2599	0	0	0
T24	680	3	0	1
T26	0	4	0	1
T29	2172	0	0	0
T103	9042	0	0	0
T114	1884	0	0	0
T118	0	19	0	1
T120	0	20	0	1
T122	0	46	0	1
T123	0	28	0	1
T124	0	47	0	1
T158	0	15	0	1
T159	0	34	0	1

gen_edn_if_asserts[5].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	247498109	247330593	0	0
T1	1674	1502	0	0
T2	2896	2817	0	0
T3	984	838	0	0
T4	23695	22720	0	0
T7	2265	2188	0	0
T20	5605	5525	0	0
T21	1007	913	0	0
T22	1913	1824	0	0
T23	2599	2536	0	0
T24	680	584	0	0

gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	247498109	141952	0	0
T1	1674	625	0	0
T2	2896	0	0	0
T3	984	379	0	0
T4	23695	0	0	0
T5	0	1112	0	0
T6	0	354	0	0
T7	2265	0	0	0
T12	0	1116	0	0
T14	0	352	0	0
T20	5605	0	0	0
T21	1007	0	0	0
T22	1913	0	0	0
T23	2599	0	0	0
T24	680	0	0	0
T27	0	1112	0	0
T71	0	1083	0	0
T105	0	1112	0	0
T109	0	7	0	0

gen_edn_if_asserts[6].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	247498109	566176	0	332
T1	1674	1041	0	0
T2	2896	48	0	0
T3	984	333	0	0
T4	23695	3612	0	0
T7	2265	1237	0	2
T20	5605	40	0	0
T21	1007	14	0	0
T22	1913	19	0	0
T23	2599	22	0	0
T24	680	63	0	0
T31	0	0	0	2
T104	0	0	0	2
T115	0	0	0	2
T116	0	0	0	2
T127	0	0	0	2
T128	0	0	0	2
T142	0	0	0	2
T143	0	0	0	2
T144	0	0	0	2

gen_edn_if_asserts[6].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	247498109	2825	0	80
T8	2130	34	0	1
T71	1866	0	0	0
T74	1105	0	0	0
T105	2905	0	0	0
T117	1520	3	0	1
T118	0	3	0	1
T120	0	3	0	1
T121	0	3	0	1
T122	0	19	0	1
T123	0	3	0	1
T128	1090	0	0	0
T131	2377	0	0	0
T151	0	3	0	1
T154	2427	0	0	0
T158	0	3	0	1
T159	0	3	0	1
T160	2618	0	0	0
T161	2543	0	0	0

gen_edn_if_asserts[6].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	247498109	247330593	0	0
T1	1674	1502	0	0
T2	2896	2817	0	0
T3	984	838	0	0
T4	23695	22720	0	0
T7	2265	2188	0	0
T20	5605	5525	0	0
T21	1007	913	0	0
T22	1913	1824	0	0
T23	2599	2536	0	0
T24	680	584	0	0

gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	247498109	141952	0	0
T1	1674	625	0	0
T2	2896	0	0	0
T3	984	379	0	0
T4	23695	0	0	0
T5	0	1112	0	0
T6	0	354	0	0
T7	2265	0	0	0
T12	0	1116	0	0
T14	0	352	0	0
T20	5605	0	0	0
T21	1007	0	0	0
T22	1913	0	0	0
T23	2599	0	0	0
T24	680	0	0	0
T27	0	1112	0	0
T71	0	1083	0	0
T105	0	1112	0	0
T109	0	7	0	0