Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44		83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	247953636	10594258	0	0
boot_gen_cmd_rd_A	247953636	69831	0	0
boot_ins_cmd_rd_A	247953636	79791	0	0
ctrl_rd_A	247953636	70025	0	0
err_code_test_rd_A	247953636	80200	0	0
intr_enable_rd_A	247953636	76558	0	0
max_num_reqs_between_reseeds_rd_A	247953636	71201	0	0
regwen_rd_A	247953636	81133	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	247953636	10594258	0	0
T8	2130	0	0	0
T71	1866	0	0	0
T74	1105	0	0	0
T104	373496	127968	0	0
T105	2905	0	0	0
T115	0	89431	0	0
T116	0	271427	0	0
T117	1520	0	0	0
T128	1090	0	0	0
T131	2377	0	0	0
T136	0	308691	0	0
T144	0	479601	0	0
T160	2618	0	0	0
T161	2543	0	0	0
T170	0	133007	0	0
T196	0	191672	0	0
T197	0	244673	0	0
T198	0	257691	0	0
T199	0	90091	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	247953636	69831	0	0
T8	2130	0	0	0
T71	1866	0	0	0
T74	1105	0	0	0
T104	373496	3697	0	0
T105	2905	0	0	0
T117	1520	0	0	0
T128	1090	0	0	0
T131	2377	0	0	0
T136	0	8913	0	0
T160	2618	0	0	0
T161	2543	0	0	0
T170	0	3863	0	0
T197	0	7165	0	0
T199	0	2596	0	0
T200	0	10354	0	0
T201	0	1894	0	0
T202	0	3055	0	0
T203	0	3417	0	0
T204	0	1656	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	247953636	79791	0	0
T8	2130	0	0	0
T71	1866	0	0	0
T74	1105	0	0	0
T104	373496	4362	0	0
T105	2905	0	0	0
T117	1520	0	0	0
T128	1090	0	0	0
T131	2377	0	0	0
T136	0	9944	0	0
T160	2618	0	0	0
T161	2543	0	0	0
T170	0	4289	0	0
T197	0	8193	0	0
T199	0	2979	0	0
T200	0	11601	0	0
T201	0	1880	0	0
T202	0	3185	0	0
T203	0	3800	0	0
T204	0	1822	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	247953636	70025	0	0
T2	2896	7	0	0
T3	984	0	0	0
T4	23695	0	0	0
T7	2265	0	0	0
T20	5605	0	0	0
T21	1007	6	0	0
T22	1913	10	0	0
T23	2599	0	0	0
T24	680	0	0	0
T104	0	3597	0	0
T108	0	10	0	0
T114	1884	0	0	0
T136	0	8861	0	0
T170	0	4027	0	0
T197	0	7250	0	0
T199	0	2515	0	0
T205	0	4	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	247953636	80200	0	0
T8	2130	0	0	0
T71	1866	0	0	0
T74	1105	0	0	0
T104	373496	4229	0	0
T105	2905	0	0	0
T117	1520	0	0	0
T128	1090	0	0	0
T131	2377	0	0	0
T136	0	10080	0	0
T160	2618	0	0	0
T161	2543	0	0	0
T170	0	4320	0	0
T197	0	7956	0	0
T199	0	3026	0	0
T200	0	12268	0	0
T201	0	2151	0	0
T202	0	3306	0	0
T203	0	3905	0	0
T204	0	2119	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	247953636	76558	0	0
T4	23695	63	0	0
T7	2265	0	0	0
T21	1007	0	0	0
T22	1913	0	0	0
T23	2599	0	0	0
T24	680	0	0	0
T29	2172	0	0	0
T103	9042	0	0	0
T104	0	4284	0	0
T114	1884	0	0	0
T136	0	9296	0	0
T145	2638	0	0	0
T170	0	3927	0	0
T197	0	7504	0	0
T199	0	2800	0	0
T200	0	10740	0	0
T205	0	90	0	0
T206	0	43	0	0
T207	0	17	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	247953636	71201	0	0
T8	2130	0	0	0
T71	1866	0	0	0
T74	1105	0	0	0
T104	373496	3801	0	0
T105	2905	0	0	0
T117	1520	0	0	0
T128	1090	0	0	0
T131	2377	0	0	0
T136	0	8865	0	0
T160	2618	0	0	0
T161	2543	0	0	0
T170	0	3954	0	0
T197	0	7162	0	0
T199	0	2646	0	0
T200	0	10671	0	0
T201	0	1718	0	0
T202	0	3035	0	0
T203	0	3448	0	0
T204	0	1653	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	247953636	81133	0	0
T8	2130	0	0	0
T71	1866	0	0	0
T74	1105	0	0	0
T104	373496	4347	0	0
T105	2905	0	0	0
T117	1520	0	0	0
T128	1090	0	0	0
T131	2377	0	0	0
T136	0	10559	0	0
T160	2618	0	0	0
T161	2543	0	0	0
T170	0	4333	0	0
T197	0	8099	0	0
T199	0	3032	0	0
T200	0	12135	0	0
T201	0	2059	0	0
T202	0	3525	0	0
T203	0	4078	0	0
T204	0	1642	0	0