Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : edn
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.44 83.33 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut 94.44 83.33 100.00 100.00



Module Instance : tb.dut

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.44 83.33 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.76 98.24 93.80 97.02 83.14 96.62 99.77


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
tb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
edn_csr_assert 100.00 100.00
gen_alert_tx[0].u_prim_alert_sender 100.00 100.00
gen_alert_tx[1].u_prim_alert_sender 100.00 100.00
tlul_assert_device 100.00 100.00 100.00 100.00
u_edn_core 92.70 99.92 92.46 82.54 83.14 99.28 98.88
u_edn_cov_if 25.00 50.00 0.00
u_reg 96.95 95.02 97.57 100.00 92.16 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Cond Coverage for Module : edn
TotalCoveredPercent
Conditions6583.33
Logical6583.33
Non-Logical00
Event00

 LINE       98
 EXPRESSION (alert[0] || intg_err_alert[0])
             ----1---    --------2--------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT20,T25,T24

 LINE       98
 EXPRESSION (alert[1] || intg_err_alert[1])
             ----1---    --------2--------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT4,T13,T14
10CoveredT1,T4,T5

Toggle Coverage for Module : edn
TotalCoveredPercent
Totals 69 69 100.00
Total Bits 1172 1172 100.00
Total Bits 0->1 586 586 100.00
Total Bits 1->0 586 586 100.00

Ports 69 69 100.00
Port Bits 1172 1172 100.00
Port Bits 0->1 586 586 100.00
Port Bits 1->0 586 586 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T4,T5 Yes T1,T2,T3 INPUT
tl_i.d_ready Yes Yes T1,T3,T4 Yes T1,T2,T3 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T1,T3,T8 Yes T1,T3,T8 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[31:0] Yes Yes T1,T3,T8 Yes T1,T3,T8 INPUT
tl_i.a_source[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_error Yes Yes T102,T116,T117 Yes T102,T116,T117 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_user.rsp_intg[5:0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_o.d_user.rsp_intg[6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_sink Unreachable Unreachable Unreachable OUTPUT
tl_o.d_source[7:0] Yes Yes T2,T8,T4 Yes T2,T8,T4 OUTPUT
tl_o.d_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_i[0].edn_req Yes Yes T1,T2,T4 Yes T1,T2,T4 INPUT
edn_i[1].edn_req Yes Yes T2,T8,T18 Yes T2,T8,T18 INPUT
edn_i[2].edn_req Yes Yes T2,T18,T19 Yes T2,T18,T19 INPUT
edn_i[3].edn_req Yes Yes T2,T18,T15 Yes T2,T18,T15 INPUT
edn_i[4].edn_req Yes Yes T2,T18,T26 Yes T2,T18,T26 INPUT
edn_i[5].edn_req Yes Yes T2,T18,T15 Yes T2,T18,T15 INPUT
edn_i[6].edn_req Yes Yes T2,T3,T18 Yes T2,T3,T18 INPUT
edn_o[0].edn_bus[31:0] Yes Yes T1,T17,T18 Yes T1,T2,T17 OUTPUT
edn_o[0].edn_fips Yes Yes T1,T19,T102 Yes T1,T19,T102 OUTPUT
edn_o[0].edn_ack Yes Yes T1,T2,T17 Yes T1,T2,T17 OUTPUT
edn_o[1].edn_bus[31:0] Yes Yes T2,T8,T18 Yes T2,T8,T18 OUTPUT
edn_o[1].edn_fips Yes Yes T2,T18,T118 Yes T2,T18,T119 OUTPUT
edn_o[1].edn_ack Yes Yes T2,T8,T18 Yes T2,T8,T18 OUTPUT
edn_o[2].edn_bus[31:0] Yes Yes T2,T18,T16 Yes T2,T18,T19 OUTPUT
edn_o[2].edn_fips Yes Yes T16,T119,T120 Yes T19,T16,T119 OUTPUT
edn_o[2].edn_ack Yes Yes T2,T18,T19 Yes T2,T18,T19 OUTPUT
edn_o[3].edn_bus[31:0] Yes Yes T2,T18,T15 Yes T2,T18,T15 OUTPUT
edn_o[3].edn_fips Yes Yes T18,T15,T119 Yes T2,T18,T15 OUTPUT
edn_o[3].edn_ack Yes Yes T2,T18,T15 Yes T2,T18,T15 OUTPUT
edn_o[4].edn_bus[31:0] Yes Yes T2,T18,T26 Yes T2,T18,T26 OUTPUT
edn_o[4].edn_fips Yes Yes T2,T26,T120 Yes T2,T26,T120 OUTPUT
edn_o[4].edn_ack Yes Yes T2,T18,T26 Yes T2,T18,T26 OUTPUT
edn_o[5].edn_bus[31:0] Yes Yes T2,T18,T15 Yes T2,T18,T15 OUTPUT
edn_o[5].edn_fips Yes Yes T18,T15,T121 Yes T2,T18,T15 OUTPUT
edn_o[5].edn_ack Yes Yes T2,T18,T15 Yes T2,T18,T15 OUTPUT
edn_o[6].edn_bus[31:0] Yes Yes T2,T3,T18 Yes T2,T3,T18 OUTPUT
edn_o[6].edn_fips Yes Yes T2,T3,T18 Yes T2,T3,T18 OUTPUT
edn_o[6].edn_ack Yes Yes T2,T3,T18 Yes T2,T3,T18 OUTPUT
csrng_cmd_o.genbits_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
csrng_cmd_o.csrng_req_bus[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
csrng_cmd_o.csrng_req_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
csrng_cmd_i.genbits_bus[127:0] Yes Yes T2,T3,T8 Yes T2,T3,T18 INPUT
csrng_cmd_i.genbits_fips Yes Yes T2,T3,T18 Yes T2,T3,T18 INPUT
csrng_cmd_i.genbits_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
csrng_cmd_i.csrng_rsp_sts[2:0] Yes Yes T20,T25,T24 Yes T20,T25,T24 INPUT
csrng_cmd_i.csrng_rsp_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
csrng_cmd_i.csrng_req_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T20,T25,T24 Yes T20,T25,T24 INPUT
alert_rx_i[0].ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i[0].ping_p Unreachable Unreachable Unreachable INPUT
alert_rx_i[1].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[1].ack_p Yes Yes T1,T4,T5 Yes T1,T4,T5 INPUT
alert_rx_i[1].ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i[1].ping_p Unreachable Unreachable Unreachable INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T20,T25,T24 Yes T20,T25,T24 OUTPUT
alert_tx_o[1].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[1].alert_p Yes Yes T1,T4,T5 Yes T1,T4,T5 OUTPUT
intr_edn_cmd_req_done_o Yes Yes T102,T103,T116 Yes T102,T103,T116 OUTPUT
intr_edn_fatal_err_o Yes Yes T1,T102,T103 Yes T1,T102,T103 OUTPUT

*Tests covering at least one bit in the range

Assert Coverage for Module : edn
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 47 47 100.00 47 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 47 47 100.00 47 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AlertTxKnownO_A 176533014 176367716 0 0
CsrngAppIfOut_A 176533014 176367716 0 0
FpvSecCmCntAlertCheck_A 176533014 105 0 0
FpvSecCmGenCmdFifoRptrCheck_A 176533014 70 0 0
FpvSecCmGenCmdFifoWptrCheck_A 176533014 70 0 0
FpvSecCmMainFsmCheck_A 176533014 70 0 0
FpvSecCmRegWeOnehotCheck_A 176533014 70 0 0
FpvSecCmResCmdFifoRptrCheck_A 176533014 70 0 0
FpvSecCmResCmdFifoWptrCheck_A 176533014 70 0 0
IntrEdnCmdReqDoneKnownO_A 176533014 176367716 0 0
TlAReadyKnownO_A 176533014 176367716 0 0
TlDValidKnownO_A 176533014 176367716 0 0
gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A 176533014 70 0 0
gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A 176533014 70 0 0
gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A 176533014 70 0 0
gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A 176533014 70 0 0
gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A 176533014 70 0 0
gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A 176533014 70 0 0
gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A 176533014 70 0 0
gen_edn_if_asserts[0].EdnDataStableDisable_A 176533014 517959 0 314
gen_edn_if_asserts[0].EdnDataStable_A 176533014 27945 0 352
gen_edn_if_asserts[0].EdnEndPointOut_A 176533014 176367716 0 0
gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A 176533014 144132 0 0
gen_edn_if_asserts[1].EdnDataStableDisable_A 176533014 517959 0 314
gen_edn_if_asserts[1].EdnDataStable_A 176533014 3678 0 116
gen_edn_if_asserts[1].EdnEndPointOut_A 176533014 176367716 0 0
gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A 176533014 144132 0 0
gen_edn_if_asserts[2].EdnDataStableDisable_A 176533014 517959 0 314
gen_edn_if_asserts[2].EdnDataStable_A 176533014 53736 0 106
gen_edn_if_asserts[2].EdnEndPointOut_A 176533014 176367716 0 0
gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A 176533014 144132 0 0
gen_edn_if_asserts[3].EdnDataStableDisable_A 176533014 517959 0 314
gen_edn_if_asserts[3].EdnDataStable_A 176533014 3913 0 99
gen_edn_if_asserts[3].EdnEndPointOut_A 176533014 176367716 0 0
gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A 176533014 144132 0 0
gen_edn_if_asserts[4].EdnDataStableDisable_A 176533014 517959 0 314
gen_edn_if_asserts[4].EdnDataStable_A 176533014 2200 0 77
gen_edn_if_asserts[4].EdnEndPointOut_A 176533014 176367716 0 0
gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A 176533014 144132 0 0
gen_edn_if_asserts[5].EdnDataStableDisable_A 176533014 517959 0 314
gen_edn_if_asserts[5].EdnDataStable_A 176533014 3025 0 72
gen_edn_if_asserts[5].EdnEndPointOut_A 176533014 176367716 0 0
gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A 176533014 144132 0 0
gen_edn_if_asserts[6].EdnDataStableDisable_A 176533014 517959 0 314
gen_edn_if_asserts[6].EdnDataStable_A 176533014 3862 0 76
gen_edn_if_asserts[6].EdnEndPointOut_A 176533014 176367716 0 0
gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A 176533014 144132 0 0


AlertTxKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 176533014 176367716 0 0
T1 1341 1160 0 0
T2 6886 6834 0 0
T3 1707 1612 0 0
T4 50215 29274 0 0
T5 1250 1097 0 0
T8 2850 2783 0 0
T17 4312 4240 0 0
T18 2986 2892 0 0
T19 8033 7955 0 0
T20 1124 983 0 0

CsrngAppIfOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 176533014 176367716 0 0
T1 1341 1160 0 0
T2 6886 6834 0 0
T3 1707 1612 0 0
T4 50215 29274 0 0
T5 1250 1097 0 0
T8 2850 2783 0 0
T17 4312 4240 0 0
T18 2986 2892 0 0
T19 8033 7955 0 0
T20 1124 983 0 0

FpvSecCmCntAlertCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 176533014 105 0 0
T1 1341 1 0 0
T2 6886 0 0 0
T3 1707 0 0 0
T4 50215 20 0 0
T5 1250 0 0 0
T7 0 1 0 0
T8 2850 0 0 0
T12 0 1 0 0
T13 0 20 0 0
T17 4312 0 0 0
T18 2986 0 0 0
T19 8033 0 0 0
T20 1124 0 0 0
T82 0 1 0 0
T83 0 1 0 0
T90 0 1 0 0
T100 0 1 0 0
T105 0 1 0 0

FpvSecCmGenCmdFifoRptrCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 176533014 70 0 0
T4 50215 20 0 0
T5 1250 0 0 0
T13 0 20 0 0
T14 0 10 0 0
T15 4463 0 0 0
T16 6319 0 0 0
T17 4312 0 0 0
T18 2986 0 0 0
T19 8033 0 0 0
T20 1124 0 0 0
T102 242925 0 0 0
T106 1891 0 0 0
T122 0 10 0 0
T123 0 10 0 0

FpvSecCmGenCmdFifoWptrCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 176533014 70 0 0
T4 50215 20 0 0
T5 1250 0 0 0
T13 0 20 0 0
T14 0 10 0 0
T15 4463 0 0 0
T16 6319 0 0 0
T17 4312 0 0 0
T18 2986 0 0 0
T19 8033 0 0 0
T20 1124 0 0 0
T102 242925 0 0 0
T106 1891 0 0 0
T122 0 10 0 0
T123 0 10 0 0

FpvSecCmMainFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 176533014 70 0 0
T4 50215 20 0 0
T5 1250 0 0 0
T13 0 20 0 0
T14 0 10 0 0
T15 4463 0 0 0
T16 6319 0 0 0
T17 4312 0 0 0
T18 2986 0 0 0
T19 8033 0 0 0
T20 1124 0 0 0
T102 242925 0 0 0
T106 1891 0 0 0
T122 0 10 0 0
T123 0 10 0 0

FpvSecCmRegWeOnehotCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 176533014 70 0 0
T4 50215 20 0 0
T5 1250 0 0 0
T13 0 20 0 0
T14 0 10 0 0
T15 4463 0 0 0
T16 6319 0 0 0
T17 4312 0 0 0
T18 2986 0 0 0
T19 8033 0 0 0
T20 1124 0 0 0
T102 242925 0 0 0
T106 1891 0 0 0
T122 0 10 0 0
T123 0 10 0 0

FpvSecCmResCmdFifoRptrCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 176533014 70 0 0
T4 50215 20 0 0
T5 1250 0 0 0
T13 0 20 0 0
T14 0 10 0 0
T15 4463 0 0 0
T16 6319 0 0 0
T17 4312 0 0 0
T18 2986 0 0 0
T19 8033 0 0 0
T20 1124 0 0 0
T102 242925 0 0 0
T106 1891 0 0 0
T122 0 10 0 0
T123 0 10 0 0

FpvSecCmResCmdFifoWptrCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 176533014 70 0 0
T4 50215 20 0 0
T5 1250 0 0 0
T13 0 20 0 0
T14 0 10 0 0
T15 4463 0 0 0
T16 6319 0 0 0
T17 4312 0 0 0
T18 2986 0 0 0
T19 8033 0 0 0
T20 1124 0 0 0
T102 242925 0 0 0
T106 1891 0 0 0
T122 0 10 0 0
T123 0 10 0 0

IntrEdnCmdReqDoneKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 176533014 176367716 0 0
T1 1341 1160 0 0
T2 6886 6834 0 0
T3 1707 1612 0 0
T4 50215 29274 0 0
T5 1250 1097 0 0
T8 2850 2783 0 0
T17 4312 4240 0 0
T18 2986 2892 0 0
T19 8033 7955 0 0
T20 1124 983 0 0

TlAReadyKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 176533014 176367716 0 0
T1 1341 1160 0 0
T2 6886 6834 0 0
T3 1707 1612 0 0
T4 50215 29274 0 0
T5 1250 1097 0 0
T8 2850 2783 0 0
T17 4312 4240 0 0
T18 2986 2892 0 0
T19 8033 7955 0 0
T20 1124 983 0 0

TlDValidKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 176533014 176367716 0 0
T1 1341 1160 0 0
T2 6886 6834 0 0
T3 1707 1612 0 0
T4 50215 29274 0 0
T5 1250 1097 0 0
T8 2850 2783 0 0
T17 4312 4240 0 0
T18 2986 2892 0 0
T19 8033 7955 0 0
T20 1124 983 0 0

gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 176533014 70 0 0
T4 50215 20 0 0
T5 1250 0 0 0
T13 0 20 0 0
T14 0 10 0 0
T15 4463 0 0 0
T16 6319 0 0 0
T17 4312 0 0 0
T18 2986 0 0 0
T19 8033 0 0 0
T20 1124 0 0 0
T102 242925 0 0 0
T106 1891 0 0 0
T122 0 10 0 0
T123 0 10 0 0

gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 176533014 70 0 0
T4 50215 20 0 0
T5 1250 0 0 0
T13 0 20 0 0
T14 0 10 0 0
T15 4463 0 0 0
T16 6319 0 0 0
T17 4312 0 0 0
T18 2986 0 0 0
T19 8033 0 0 0
T20 1124 0 0 0
T102 242925 0 0 0
T106 1891 0 0 0
T122 0 10 0 0
T123 0 10 0 0

gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 176533014 70 0 0
T4 50215 20 0 0
T5 1250 0 0 0
T13 0 20 0 0
T14 0 10 0 0
T15 4463 0 0 0
T16 6319 0 0 0
T17 4312 0 0 0
T18 2986 0 0 0
T19 8033 0 0 0
T20 1124 0 0 0
T102 242925 0 0 0
T106 1891 0 0 0
T122 0 10 0 0
T123 0 10 0 0

gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 176533014 70 0 0
T4 50215 20 0 0
T5 1250 0 0 0
T13 0 20 0 0
T14 0 10 0 0
T15 4463 0 0 0
T16 6319 0 0 0
T17 4312 0 0 0
T18 2986 0 0 0
T19 8033 0 0 0
T20 1124 0 0 0
T102 242925 0 0 0
T106 1891 0 0 0
T122 0 10 0 0
T123 0 10 0 0

gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 176533014 70 0 0
T4 50215 20 0 0
T5 1250 0 0 0
T13 0 20 0 0
T14 0 10 0 0
T15 4463 0 0 0
T16 6319 0 0 0
T17 4312 0 0 0
T18 2986 0 0 0
T19 8033 0 0 0
T20 1124 0 0 0
T102 242925 0 0 0
T106 1891 0 0 0
T122 0 10 0 0
T123 0 10 0 0

gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 176533014 70 0 0
T4 50215 20 0 0
T5 1250 0 0 0
T13 0 20 0 0
T14 0 10 0 0
T15 4463 0 0 0
T16 6319 0 0 0
T17 4312 0 0 0
T18 2986 0 0 0
T19 8033 0 0 0
T20 1124 0 0 0
T102 242925 0 0 0
T106 1891 0 0 0
T122 0 10 0 0
T123 0 10 0 0

gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 176533014 70 0 0
T4 50215 20 0 0
T5 1250 0 0 0
T13 0 20 0 0
T14 0 10 0 0
T15 4463 0 0 0
T16 6319 0 0 0
T17 4312 0 0 0
T18 2986 0 0 0
T19 8033 0 0 0
T20 1124 0 0 0
T102 242925 0 0 0
T106 1891 0 0 0
T122 0 10 0 0
T123 0 10 0 0

gen_edn_if_asserts[0].EdnDataStableDisable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 176533014 517959 0 314
T1 1341 677 0 0
T2 6886 69 0 0
T3 1707 184 0 0
T4 50215 25903 0 2
T5 1250 650 0 0
T8 2850 1557 0 2
T17 4312 29 0 0
T18 2986 50 0 0
T19 8033 50 0 0
T20 1124 528 0 0
T31 0 0 0 2
T32 0 0 0 2
T102 0 0 0 2
T103 0 0 0 2
T116 0 0 0 2
T117 0 0 0 2
T124 0 0 0 2
T125 0 0 0 2

gen_edn_if_asserts[0].EdnDataStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 176533014 27945 0 352
T1 1341 1 0 0
T2 6886 3 0 1
T3 1707 0 0 0
T4 50215 0 0 0
T5 1250 0 0 0
T8 2850 0 0 0
T17 4312 3 0 1
T18 2986 3 0 1
T19 8033 1141 0 1
T20 1124 0 0 0
T24 0 0 0 1
T25 0 4 0 1
T102 0 9 0 0
T103 0 15 0 0
T106 0 3 0 1
T116 0 143 0 0
T118 0 0 0 1
T119 0 0 0 1
T126 0 0 0 1

gen_edn_if_asserts[0].EdnEndPointOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 176533014 176367716 0 0
T1 1341 1160 0 0
T2 6886 6834 0 0
T3 1707 1612 0 0
T4 50215 29274 0 0
T5 1250 1097 0 0
T8 2850 2783 0 0
T17 4312 4240 0 0
T18 2986 2892 0 0
T19 8033 7955 0 0
T20 1124 983 0 0

gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 176533014 144132 0 0
T1 1341 387 0 0
T2 6886 0 0 0
T3 1707 0 0 0
T4 50215 17377 0 0
T5 1250 602 0 0
T6 0 1112 0 0
T8 2850 0 0 0
T12 0 382 0 0
T17 4312 0 0 0
T18 2986 0 0 0
T19 8033 0 0 0
T20 1124 602 0 0
T22 0 1120 0 0
T23 0 1112 0 0
T109 0 7 0 0
T110 0 7 0 0

gen_edn_if_asserts[1].EdnDataStableDisable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 176533014 517959 0 314
T1 1341 677 0 0
T2 6886 69 0 0
T3 1707 184 0 0
T4 50215 25903 0 2
T5 1250 650 0 0
T8 2850 1557 0 2
T17 4312 29 0 0
T18 2986 50 0 0
T19 8033 50 0 0
T20 1124 528 0 0
T31 0 0 0 2
T32 0 0 0 2
T102 0 0 0 2
T103 0 0 0 2
T116 0 0 0 2
T117 0 0 0 2
T124 0 0 0 2
T125 0 0 0 2

gen_edn_if_asserts[1].EdnDataStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 176533014 3678 0 116
T2 6886 17 0 1
T3 1707 0 0 0
T4 50215 0 0 0
T5 1250 0 0 0
T8 2850 4 0 0
T17 4312 0 0 0
T18 2986 47 0 1
T19 8033 3 0 1
T20 1124 0 0 0
T21 0 3 0 1
T33 0 4 0 1
T102 242925 0 0 0
T109 0 1 0 0
T118 0 52 0 1
T119 0 3 0 1
T120 0 0 0 1
T127 0 51 0 1
T128 0 0 0 1

gen_edn_if_asserts[1].EdnEndPointOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 176533014 176367716 0 0
T1 1341 1160 0 0
T2 6886 6834 0 0
T3 1707 1612 0 0
T4 50215 29274 0 0
T5 1250 1097 0 0
T8 2850 2783 0 0
T17 4312 4240 0 0
T18 2986 2892 0 0
T19 8033 7955 0 0
T20 1124 983 0 0

gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 176533014 144132 0 0
T1 1341 387 0 0
T2 6886 0 0 0
T3 1707 0 0 0
T4 50215 17377 0 0
T5 1250 602 0 0
T6 0 1112 0 0
T8 2850 0 0 0
T12 0 382 0 0
T17 4312 0 0 0
T18 2986 0 0 0
T19 8033 0 0 0
T20 1124 602 0 0
T22 0 1120 0 0
T23 0 1112 0 0
T109 0 7 0 0
T110 0 7 0 0

gen_edn_if_asserts[2].EdnDataStableDisable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 176533014 517959 0 314
T1 1341 677 0 0
T2 6886 69 0 0
T3 1707 184 0 0
T4 50215 25903 0 2
T5 1250 650 0 0
T8 2850 1557 0 2
T17 4312 29 0 0
T18 2986 50 0 0
T19 8033 50 0 0
T20 1124 528 0 0
T31 0 0 0 2
T32 0 0 0 2
T102 0 0 0 2
T103 0 0 0 2
T116 0 0 0 2
T117 0 0 0 2
T124 0 0 0 2
T125 0 0 0 2

gen_edn_if_asserts[2].EdnDataStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 176533014 53736 0 106
T2 6886 3 0 1
T3 1707 0 0 0
T4 50215 0 0 0
T5 1250 0 0 0
T8 2850 0 0 0
T16 0 987 0 1
T17 4312 0 0 0
T18 2986 3 0 1
T19 8033 3 0 1
T20 1124 0 0 0
T26 0 3 0 1
T102 242925 0 0 0
T105 0 1 0 0
T118 0 3 0 1
T119 0 60 0 1
T120 0 36 0 1
T129 0 3 0 1
T130 0 0 0 1

gen_edn_if_asserts[2].EdnEndPointOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 176533014 176367716 0 0
T1 1341 1160 0 0
T2 6886 6834 0 0
T3 1707 1612 0 0
T4 50215 29274 0 0
T5 1250 1097 0 0
T8 2850 2783 0 0
T17 4312 4240 0 0
T18 2986 2892 0 0
T19 8033 7955 0 0
T20 1124 983 0 0

gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 176533014 144132 0 0
T1 1341 387 0 0
T2 6886 0 0 0
T3 1707 0 0 0
T4 50215 17377 0 0
T5 1250 602 0 0
T6 0 1112 0 0
T8 2850 0 0 0
T12 0 382 0 0
T17 4312 0 0 0
T18 2986 0 0 0
T19 8033 0 0 0
T20 1124 602 0 0
T22 0 1120 0 0
T23 0 1112 0 0
T109 0 7 0 0
T110 0 7 0 0

gen_edn_if_asserts[3].EdnDataStableDisable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 176533014 517959 0 314
T1 1341 677 0 0
T2 6886 69 0 0
T3 1707 184 0 0
T4 50215 25903 0 2
T5 1250 650 0 0
T8 2850 1557 0 2
T17 4312 29 0 0
T18 2986 50 0 0
T19 8033 50 0 0
T20 1124 528 0 0
T31 0 0 0 2
T32 0 0 0 2
T102 0 0 0 2
T103 0 0 0 2
T116 0 0 0 2
T117 0 0 0 2
T124 0 0 0 2
T125 0 0 0 2

gen_edn_if_asserts[3].EdnDataStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 176533014 3913 0 99
T2 6886 3 0 1
T3 1707 0 0 0
T4 50215 0 0 0
T5 1250 0 0 0
T8 2850 0 0 0
T15 0 531 0 1
T17 4312 0 0 0
T18 2986 23 0 1
T19 8033 0 0 0
T20 1124 0 0 0
T26 0 11 0 1
T28 0 0 0 1
T102 242925 0 0 0
T118 0 50 0 1
T119 0 30 0 1
T120 0 3 0 1
T131 0 4 0 0
T132 0 4 0 0
T133 0 15 0 1
T134 0 0 0 1

gen_edn_if_asserts[3].EdnEndPointOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 176533014 176367716 0 0
T1 1341 1160 0 0
T2 6886 6834 0 0
T3 1707 1612 0 0
T4 50215 29274 0 0
T5 1250 1097 0 0
T8 2850 2783 0 0
T17 4312 4240 0 0
T18 2986 2892 0 0
T19 8033 7955 0 0
T20 1124 983 0 0

gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 176533014 144132 0 0
T1 1341 387 0 0
T2 6886 0 0 0
T3 1707 0 0 0
T4 50215 17377 0 0
T5 1250 602 0 0
T6 0 1112 0 0
T8 2850 0 0 0
T12 0 382 0 0
T17 4312 0 0 0
T18 2986 0 0 0
T19 8033 0 0 0
T20 1124 602 0 0
T22 0 1120 0 0
T23 0 1112 0 0
T109 0 7 0 0
T110 0 7 0 0

gen_edn_if_asserts[4].EdnDataStableDisable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 176533014 517959 0 314
T1 1341 677 0 0
T2 6886 69 0 0
T3 1707 184 0 0
T4 50215 25903 0 2
T5 1250 650 0 0
T8 2850 1557 0 2
T17 4312 29 0 0
T18 2986 50 0 0
T19 8033 50 0 0
T20 1124 528 0 0
T31 0 0 0 2
T32 0 0 0 2
T102 0 0 0 2
T103 0 0 0 2
T116 0 0 0 2
T117 0 0 0 2
T124 0 0 0 2
T125 0 0 0 2

gen_edn_if_asserts[4].EdnDataStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 176533014 2200 0 77
T2 6886 55 0 1
T3 1707 0 0 0
T4 50215 0 0 0
T5 1250 0 0 0
T8 2850 0 0 0
T17 4312 0 0 0
T18 2986 3 0 1
T19 8033 0 0 0
T20 1124 0 0 0
T26 0 41 0 1
T102 242925 0 0 0
T120 0 46 0 1
T128 0 3 0 1
T129 0 3 0 1
T134 0 3 0 1
T135 0 18 0 1
T136 0 3 0 1
T137 0 9 0 1

gen_edn_if_asserts[4].EdnEndPointOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 176533014 176367716 0 0
T1 1341 1160 0 0
T2 6886 6834 0 0
T3 1707 1612 0 0
T4 50215 29274 0 0
T5 1250 1097 0 0
T8 2850 2783 0 0
T17 4312 4240 0 0
T18 2986 2892 0 0
T19 8033 7955 0 0
T20 1124 983 0 0

gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 176533014 144132 0 0
T1 1341 387 0 0
T2 6886 0 0 0
T3 1707 0 0 0
T4 50215 17377 0 0
T5 1250 602 0 0
T6 0 1112 0 0
T8 2850 0 0 0
T12 0 382 0 0
T17 4312 0 0 0
T18 2986 0 0 0
T19 8033 0 0 0
T20 1124 602 0 0
T22 0 1120 0 0
T23 0 1112 0 0
T109 0 7 0 0
T110 0 7 0 0

gen_edn_if_asserts[5].EdnDataStableDisable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 176533014 517959 0 314
T1 1341 677 0 0
T2 6886 69 0 0
T3 1707 184 0 0
T4 50215 25903 0 2
T5 1250 650 0 0
T8 2850 1557 0 2
T17 4312 29 0 0
T18 2986 50 0 0
T19 8033 50 0 0
T20 1124 528 0 0
T31 0 0 0 2
T32 0 0 0 2
T102 0 0 0 2
T103 0 0 0 2
T116 0 0 0 2
T117 0 0 0 2
T124 0 0 0 2
T125 0 0 0 2

gen_edn_if_asserts[5].EdnDataStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 176533014 3025 0 72
T2 6886 12 0 1
T3 1707 0 0 0
T4 50215 0 0 0
T5 1250 0 0 0
T8 2850 0 0 0
T15 0 12 0 1
T17 4312 0 0 0
T18 2986 22 0 1
T19 8033 0 0 0
T20 1124 0 0 0
T26 0 3 0 1
T32 0 4 0 0
T71 0 0 0 1
T102 242925 0 0 0
T120 0 3 0 1
T128 0 3 0 1
T129 0 8 0 1
T134 0 3 0 1
T138 0 8 0 0
T139 0 0 0 1

gen_edn_if_asserts[5].EdnEndPointOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 176533014 176367716 0 0
T1 1341 1160 0 0
T2 6886 6834 0 0
T3 1707 1612 0 0
T4 50215 29274 0 0
T5 1250 1097 0 0
T8 2850 2783 0 0
T17 4312 4240 0 0
T18 2986 2892 0 0
T19 8033 7955 0 0
T20 1124 983 0 0

gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 176533014 144132 0 0
T1 1341 387 0 0
T2 6886 0 0 0
T3 1707 0 0 0
T4 50215 17377 0 0
T5 1250 602 0 0
T6 0 1112 0 0
T8 2850 0 0 0
T12 0 382 0 0
T17 4312 0 0 0
T18 2986 0 0 0
T19 8033 0 0 0
T20 1124 602 0 0
T22 0 1120 0 0
T23 0 1112 0 0
T109 0 7 0 0
T110 0 7 0 0

gen_edn_if_asserts[6].EdnDataStableDisable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 176533014 517959 0 314
T1 1341 677 0 0
T2 6886 69 0 0
T3 1707 184 0 0
T4 50215 25903 0 2
T5 1250 650 0 0
T8 2850 1557 0 2
T17 4312 29 0 0
T18 2986 50 0 0
T19 8033 50 0 0
T20 1124 528 0 0
T31 0 0 0 2
T32 0 0 0 2
T102 0 0 0 2
T103 0 0 0 2
T116 0 0 0 2
T117 0 0 0 2
T124 0 0 0 2
T125 0 0 0 2

gen_edn_if_asserts[6].EdnDataStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 176533014 3862 0 76
T2 6886 711 0 1
T3 1707 52 0 1
T4 50215 0 0 0
T5 1250 0 0 0
T8 2850 0 0 0
T16 0 62 0 1
T17 4312 0 0 0
T18 2986 34 0 1
T19 8033 0 0 0
T20 1124 0 0 0
T102 242925 0 0 0
T120 0 3 0 1
T121 0 3 0 1
T129 0 3 0 1
T134 0 15 0 1
T136 0 3 0 1
T139 0 21 0 1

gen_edn_if_asserts[6].EdnEndPointOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 176533014 176367716 0 0
T1 1341 1160 0 0
T2 6886 6834 0 0
T3 1707 1612 0 0
T4 50215 29274 0 0
T5 1250 1097 0 0
T8 2850 2783 0 0
T17 4312 4240 0 0
T18 2986 2892 0 0
T19 8033 7955 0 0
T20 1124 983 0 0

gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 176533014 144132 0 0
T1 1341 387 0 0
T2 6886 0 0 0
T3 1707 0 0 0
T4 50215 17377 0 0
T5 1250 602 0 0
T6 0 1112 0 0
T8 2850 0 0 0
T12 0 382 0 0
T17 4312 0 0 0
T18 2986 0 0 0
T19 8033 0 0 0
T20 1124 602 0 0
T22 0 1120 0 0
T23 0 1112 0 0
T109 0 7 0 0
T110 0 7 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%