Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44		83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	177003347	8156987	0	0
boot_gen_cmd_rd_A	177003347	46686	0	0
boot_ins_cmd_rd_A	177003347	53201	0	0
ctrl_rd_A	177003347	46517	0	0
err_code_test_rd_A	177003347	53631	0	0
intr_enable_rd_A	177003347	51173	0	0
max_num_reqs_between_reseeds_rd_A	177003347	47299	0	0
regwen_rd_A	177003347	54460	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	177003347	8156987	0	0
T15	4463	0	0	0
T16	6319	0	0	0
T21	847	0	0	0
T24	2405	0	0	0
T25	1681	0	0	0
T102	242925	136552	0	0
T103	18946	0	0	0
T106	1891	0	0	0
T116	342800	199031	0	0
T117	0	298236	0	0
T119	4837	0	0	0
T124	0	57452	0	0
T125	0	59577	0	0
T188	0	12233	0	0
T189	0	245880	0	0
T190	0	106248	0	0
T191	0	210478	0	0
T192	0	322280	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	177003347	46686	0	0
T6	2109	0	0	0
T12	721	0	0	0
T23	1874	0	0	0
T26	3231	0	0	0
T27	3332	0	0	0
T105	2318	0	0	0
T109	1990	0	0	0
T110	1874	0	0	0
T117	852487	8804	0	0
T124	140783	0	0	0
T125	0	1591	0	0
T193	0	1469	0	0
T194	0	1070	0	0
T195	0	11811	0	0
T196	0	1379	0	0
T197	0	2339	0	0
T198	0	1015	0	0
T199	0	4216	0	0
T200	0	1785	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	177003347	53201	0	0
T6	2109	0	0	0
T12	721	0	0	0
T23	1874	0	0	0
T26	3231	0	0	0
T27	3332	0	0	0
T105	2318	0	0	0
T109	1990	0	0	0
T110	1874	0	0	0
T117	852487	10375	0	0
T124	140783	0	0	0
T125	0	1827	0	0
T193	0	1772	0	0
T194	0	1156	0	0
T195	0	13255	0	0
T196	0	1637	0	0
T197	0	2642	0	0
T198	0	1089	0	0
T199	0	4715	0	0
T200	0	2116	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	177003347	46517	0	0
T6	2109	0	0	0
T12	721	0	0	0
T23	1874	0	0	0
T26	3231	0	0	0
T27	3332	0	0	0
T74	0	1	0	0
T99	0	2	0	0
T105	2318	0	0	0
T109	1990	0	0	0
T110	1874	0	0	0
T117	852487	8750	0	0
T124	140783	0	0	0
T125	0	1650	0	0
T193	0	1389	0	0
T194	0	1038	0	0
T195	0	11595	0	0
T196	0	1397	0	0
T201	0	1	0	0
T202	0	1	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	177003347	53631	0	0
T6	2109	0	0	0
T12	721	0	0	0
T23	1874	0	0	0
T26	3231	0	0	0
T27	3332	0	0	0
T105	2318	0	0	0
T109	1990	0	0	0
T110	1874	0	0	0
T117	852487	9995	0	0
T124	140783	0	0	0
T125	0	2035	0	0
T193	0	1647	0	0
T194	0	1197	0	0
T195	0	13796	0	0
T196	0	1590	0	0
T197	0	2513	0	0
T198	0	1160	0	0
T199	0	4799	0	0
T200	0	2254	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	177003347	51173	0	0
T22	2186	0	0	0
T24	2405	0	0	0
T25	1681	0	0	0
T33	2322	0	0	0
T103	18946	116	0	0
T116	342800	0	0	0
T117	852487	9203	0	0
T118	7286	0	0	0
T119	4837	0	0	0
T125	0	1929	0	0
T126	6673	0	0	0
T193	0	1414	0	0
T194	0	1329	0	0
T195	0	12602	0	0
T201	0	47	0	0
T203	0	21	0	0
T204	0	21	0	0
T205	0	53	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	177003347	47299	0	0
T6	2109	0	0	0
T12	721	0	0	0
T23	1874	0	0	0
T26	3231	0	0	0
T27	3332	0	0	0
T105	2318	0	0	0
T109	1990	0	0	0
T110	1874	0	0	0
T117	852487	8727	0	0
T124	140783	0	0	0
T125	0	1732	0	0
T193	0	1503	0	0
T194	0	1020	0	0
T195	0	11652	0	0
T196	0	1556	0	0
T197	0	2144	0	0
T198	0	1067	0	0
T199	0	4142	0	0
T200	0	2031	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	177003347	54460	0	0
T6	2109	0	0	0
T12	721	0	0	0
T23	1874	0	0	0
T26	3231	0	0	0
T27	3332	0	0	0
T105	2318	0	0	0
T109	1990	0	0	0
T110	1874	0	0	0
T117	852487	10235	0	0
T124	140783	0	0	0
T125	0	1874	0	0
T193	0	1695	0	0
T194	0	1160	0	0
T195	0	13672	0	0
T196	0	1810	0	0
T197	0	2628	0	0
T198	0	1326	0	0
T199	0	4755	0	0
T200	0	2279	0	0