Unified Coverage Report :: Module :: edn

Module : edn

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	94.44		83.33	100.00			100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.25	98.24	93.72	97.02	92.44	96.33	99.77

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
edn_csr_assert	100.00						100.00
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_edn_core	94.16	99.92	92.36	82.54	92.44	98.81	98.88
u_edn_cov_if	25.00	50.00	0.00
u_reg	96.95	95.02	97.57	100.00		92.16	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Cond Coverage for Module : edn

	Total	Covered	Percent
Conditions	6	5	83.33
Logical	6	5	83.33
Non-Logical	0	0
Event	0	0

 LINE       98
 EXPRESSION (alert[0] || intg_err_alert[0])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T11,T31,T32

 LINE       98
 EXPRESSION (alert[1] || intg_err_alert[1])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T16,T19,T20
1	0	Covered	T16,T17,T36

---

Toggle Coverage for Module : edn

	Total	Covered	Percent
Totals	69	69	100.00
Total Bits	1172	1172	100.00
Total Bits 0->1	586	586	100.00
Total Bits 1->0	586	586	100.00

Ports	69	69	100.00
Port Bits	1172	1172	100.00
Port Bits 0->1	586	586	100.00
Port Bits 1->0	586	586	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T6	Yes	T1,T2,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T1,T42,T43	Yes	T1,T42,T43	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T3,T6	Yes	T1,T3,T6	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T3,*T6	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i[0].edn_req	Yes	Yes	T1,T6,T4	Yes	T1,T6,T4	INPUT
edn_i[1].edn_req	Yes	Yes	T3,T44,T12	Yes	T3,T44,T12	INPUT
edn_i[2].edn_req	Yes	Yes	T3,T10,T11	Yes	T3,T10,T11	INPUT
edn_i[3].edn_req	Yes	Yes	T10,T45,T36	Yes	T10,T45,T36	INPUT
edn_i[4].edn_req	Yes	Yes	T46,T45,T47	Yes	T46,T45,T47	INPUT
edn_i[5].edn_req	Yes	Yes	T46,T45,T47	Yes	T46,T45,T47	INPUT
edn_i[6].edn_req	Yes	Yes	T26,T46,T45	Yes	T26,T46,T45	INPUT
edn_o[0].edn_bus[31:0]	Yes	Yes	T1,T6,T4	Yes	T1,T6,T4	OUTPUT
edn_o[0].edn_fips	Yes	Yes	T1,T24,T27	Yes	T1,T23,T24	OUTPUT
edn_o[0].edn_ack	Yes	Yes	T1,T6,T4	Yes	T1,T6,T4	OUTPUT
edn_o[1].edn_bus[31:0]	Yes	Yes	T3,T12,T46	Yes	T3,T44,T12	OUTPUT
edn_o[1].edn_fips	Yes	Yes	T45,T48,T49	Yes	T44,T46,T45	OUTPUT
edn_o[1].edn_ack	Yes	Yes	T3,T44,T12	Yes	T3,T44,T12	OUTPUT
edn_o[2].edn_bus[31:0]	Yes	Yes	T10,T11,T46	Yes	T3,T10,T11	OUTPUT
edn_o[2].edn_fips	Yes	Yes	T10,T45,T50	Yes	T3,T10,T45	OUTPUT
edn_o[2].edn_ack	Yes	Yes	T3,T10,T11	Yes	T3,T10,T11	OUTPUT
edn_o[3].edn_bus[31:0]	Yes	Yes	T45,T47,T51	Yes	T10,T45,T47	OUTPUT
edn_o[3].edn_fips	Yes	Yes	T45,T51,T21	Yes	T10,T45,T51	OUTPUT
edn_o[3].edn_ack	Yes	Yes	T10,T45,T47	Yes	T10,T45,T47	OUTPUT
edn_o[4].edn_bus[31:0]	Yes	Yes	T45,T51,T21	Yes	T46,T45,T47	OUTPUT
edn_o[4].edn_fips	Yes	Yes	T45,T50,T48	Yes	T45,T21,T50	OUTPUT
edn_o[4].edn_ack	Yes	Yes	T46,T45,T47	Yes	T46,T45,T47	OUTPUT
edn_o[5].edn_bus[31:0]	Yes	Yes	T46,T45,T47	Yes	T46,T45,T47	OUTPUT
edn_o[5].edn_fips	Yes	Yes	T46,T45,T47	Yes	T46,T45,T47	OUTPUT
edn_o[5].edn_ack	Yes	Yes	T46,T45,T47	Yes	T46,T45,T47	OUTPUT
edn_o[6].edn_bus[31:0]	Yes	Yes	T26,T46,T45	Yes	T26,T46,T45	OUTPUT
edn_o[6].edn_fips	Yes	Yes	T45,T47,T52	Yes	T46,T45,T47	OUTPUT
edn_o[6].edn_ack	Yes	Yes	T26,T46,T45	Yes	T26,T46,T45	OUTPUT
csrng_cmd_o.genbits_ready	Yes	Yes	T1,T3,T6	Yes	T1,T3,T6	OUTPUT
csrng_cmd_o.csrng_req_bus[31:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T6	OUTPUT
csrng_cmd_o.csrng_req_valid	Yes	Yes	T1,T3,T6	Yes	T1,T3,T6	OUTPUT
csrng_cmd_i.genbits_bus[127:0]	Yes	Yes	T1,T3,T24	Yes	T1,T24,T26	INPUT
csrng_cmd_i.genbits_fips	Yes	Yes	T1,T24,T27	Yes	T1,T3,T24	INPUT
csrng_cmd_i.genbits_valid	Yes	Yes	T1,T3,T6	Yes	T1,T3,T6	INPUT
csrng_cmd_i.csrng_rsp_sts[2:0]	Yes	Yes	T31,T53,T54	Yes	T31,T53,T54	INPUT
csrng_cmd_i.csrng_rsp_ack	Yes	Yes	T1,T3,T6	Yes	T1,T3,T6	INPUT
csrng_cmd_i.csrng_req_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T2,T11,T31	Yes	T2,T11,T31	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T2,T16,T17	Yes	T2,T16,T17	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T2,T11,T31	Yes	T2,T11,T31	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T2,T16,T17	Yes	T2,T16,T17	OUTPUT
intr_edn_cmd_req_done_o	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
intr_edn_fatal_err_o	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT

*Tests covering at least one bit in the range

---

Assert Coverage for Module : edn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	47	47	100.00	47	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	47	47	100.00	47	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxKnownO_A	221079372	220911394	0	0
CsrngAppIfOut_A	221079372	220911394	0	0
FpvSecCmCntAlertCheck_A	221079372	114	0	0
FpvSecCmGenCmdFifoRptrCheck_A	221079372	70	0	0
FpvSecCmGenCmdFifoWptrCheck_A	221079372	70	0	0
FpvSecCmMainFsmCheck_A	221079372	70	0	0
FpvSecCmRegWeOnehotCheck_A	221079372	70	0	0
FpvSecCmResCmdFifoRptrCheck_A	221079372	70	0	0
FpvSecCmResCmdFifoWptrCheck_A	221079372	70	0	0
IntrEdnCmdReqDoneKnownO_A	221079372	220911394	0	0
TlAReadyKnownO_A	221079372	220911394	0	0
TlDValidKnownO_A	221079372	220911394	0	0
gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A	221079372	70	0	0
gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A	221079372	70	0	0
gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A	221079372	70	0	0
gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A	221079372	70	0	0
gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A	221079372	70	0	0
gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A	221079372	70	0	0
gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A	221079372	70	0	0
gen_edn_if_asserts[0].EdnDataStableDisable_A	221079372	559637	0	332
gen_edn_if_asserts[0].EdnDataStable_A	221079372	26226	0	337
gen_edn_if_asserts[0].EdnEndPointOut_A	221079372	220911394	0	0
gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A	221079372	156450	0	0
gen_edn_if_asserts[1].EdnDataStableDisable_A	221079372	559637	0	332
gen_edn_if_asserts[1].EdnDataStable_A	221079372	5584	0	132
gen_edn_if_asserts[1].EdnEndPointOut_A	221079372	220911394	0	0
gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A	221079372	156450	0	0
gen_edn_if_asserts[2].EdnDataStableDisable_A	221079372	559637	0	332
gen_edn_if_asserts[2].EdnDataStable_A	221079372	3343	0	134
gen_edn_if_asserts[2].EdnEndPointOut_A	221079372	220911394	0	0
gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A	221079372	156450	0	0
gen_edn_if_asserts[3].EdnDataStableDisable_A	221079372	559637	0	332
gen_edn_if_asserts[3].EdnDataStable_A	221079372	3236	0	119
gen_edn_if_asserts[3].EdnEndPointOut_A	221079372	220911394	0	0
gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A	221079372	156450	0	0
gen_edn_if_asserts[4].EdnDataStableDisable_A	221079372	559637	0	332
gen_edn_if_asserts[4].EdnDataStable_A	221079372	5062	0	105
gen_edn_if_asserts[4].EdnEndPointOut_A	221079372	220911394	0	0
gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A	221079372	156450	0	0
gen_edn_if_asserts[5].EdnDataStableDisable_A	221079372	559637	0	332
gen_edn_if_asserts[5].EdnDataStable_A	221079372	3543	0	105
gen_edn_if_asserts[5].EdnEndPointOut_A	221079372	220911394	0	0
gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A	221079372	156450	0	0
gen_edn_if_asserts[6].EdnDataStableDisable_A	221079372	559637	0	332
gen_edn_if_asserts[6].EdnDataStable_A	221079372	51332	0	84
gen_edn_if_asserts[6].EdnEndPointOut_A	221079372	220911394	0	0
gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A	221079372	156450	0	0

AlertTxKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221079372	220911394	0	0
T1	521601	521587	0	0
T2	1659	1591	0	0
T3	2209	2114	0	0
T4	5263	4993	0	0
T6	1273	1210	0	0
T23	3700	3616	0	0
T24	3737	3666	0	0
T25	891	830	0	0
T26	687	634	0	0
T27	3993	3911	0	0

CsrngAppIfOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221079372	220911394	0	0
T1	521601	521587	0	0
T2	1659	1591	0	0
T3	2209	2114	0	0
T4	5263	4993	0	0
T6	1273	1210	0	0
T23	3700	3616	0	0
T24	3737	3666	0	0
T25	891	830	0	0
T26	687	634	0	0
T27	3993	3911	0	0

FpvSecCmCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221079372	114	0	0
T16	46398	20	0	0
T17	1907	1	0	0
T18	0	1	0	0
T19	0	10	0	0
T21	4559	0	0	0
T36	1056	0	0	0
T42	196572	0	0	0
T45	4196	0	0	0
T47	2817	0	0	0
T51	2231	0	0	0
T53	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	1494	0	0	0
T61	13211	0	0	0

FpvSecCmGenCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221079372	70	0	0
T16	46398	20	0	0
T17	1907	0	0	0
T19	0	10	0	0
T20	0	20	0	0
T21	4559	0	0	0
T36	1056	0	0	0
T42	196572	0	0	0
T45	4196	0	0	0
T47	2817	0	0	0
T51	2231	0	0	0
T60	1494	0	0	0
T61	13211	0	0	0
T62	0	10	0	0
T63	0	10	0	0

FpvSecCmGenCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221079372	70	0	0
T16	46398	20	0	0
T17	1907	0	0	0
T19	0	10	0	0
T20	0	20	0	0
T21	4559	0	0	0
T36	1056	0	0	0
T42	196572	0	0	0
T45	4196	0	0	0
T47	2817	0	0	0
T51	2231	0	0	0
T60	1494	0	0	0
T61	13211	0	0	0
T62	0	10	0	0
T63	0	10	0	0

FpvSecCmMainFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221079372	70	0	0
T16	46398	20	0	0
T17	1907	0	0	0
T19	0	10	0	0
T20	0	20	0	0
T21	4559	0	0	0
T36	1056	0	0	0
T42	196572	0	0	0
T45	4196	0	0	0
T47	2817	0	0	0
T51	2231	0	0	0
T60	1494	0	0	0
T61	13211	0	0	0
T62	0	10	0	0
T63	0	10	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221079372	70	0	0
T16	46398	20	0	0
T17	1907	0	0	0
T19	0	10	0	0
T20	0	20	0	0
T21	4559	0	0	0
T36	1056	0	0	0
T42	196572	0	0	0
T45	4196	0	0	0
T47	2817	0	0	0
T51	2231	0	0	0
T60	1494	0	0	0
T61	13211	0	0	0
T62	0	10	0	0
T63	0	10	0	0

FpvSecCmResCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221079372	70	0	0
T16	46398	20	0	0
T17	1907	0	0	0
T19	0	10	0	0
T20	0	20	0	0
T21	4559	0	0	0
T36	1056	0	0	0
T42	196572	0	0	0
T45	4196	0	0	0
T47	2817	0	0	0
T51	2231	0	0	0
T60	1494	0	0	0
T61	13211	0	0	0
T62	0	10	0	0
T63	0	10	0	0

FpvSecCmResCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221079372	70	0	0
T16	46398	20	0	0
T17	1907	0	0	0
T19	0	10	0	0
T20	0	20	0	0
T21	4559	0	0	0
T36	1056	0	0	0
T42	196572	0	0	0
T45	4196	0	0	0
T47	2817	0	0	0
T51	2231	0	0	0
T60	1494	0	0	0
T61	13211	0	0	0
T62	0	10	0	0
T63	0	10	0	0

IntrEdnCmdReqDoneKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221079372	220911394	0	0
T1	521601	521587	0	0
T2	1659	1591	0	0
T3	2209	2114	0	0
T4	5263	4993	0	0
T6	1273	1210	0	0
T23	3700	3616	0	0
T24	3737	3666	0	0
T25	891	830	0	0
T26	687	634	0	0
T27	3993	3911	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221079372	220911394	0	0
T1	521601	521587	0	0
T2	1659	1591	0	0
T3	2209	2114	0	0
T4	5263	4993	0	0
T6	1273	1210	0	0
T23	3700	3616	0	0
T24	3737	3666	0	0
T25	891	830	0	0
T26	687	634	0	0
T27	3993	3911	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221079372	220911394	0	0
T1	521601	521587	0	0
T2	1659	1591	0	0
T3	2209	2114	0	0
T4	5263	4993	0	0
T6	1273	1210	0	0
T23	3700	3616	0	0
T24	3737	3666	0	0
T25	891	830	0	0
T26	687	634	0	0
T27	3993	3911	0	0

gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221079372	70	0	0
T16	46398	20	0	0
T17	1907	0	0	0
T19	0	10	0	0
T20	0	20	0	0
T21	4559	0	0	0
T36	1056	0	0	0
T42	196572	0	0	0
T45	4196	0	0	0
T47	2817	0	0	0
T51	2231	0	0	0
T60	1494	0	0	0
T61	13211	0	0	0
T62	0	10	0	0
T63	0	10	0	0

gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221079372	70	0	0
T16	46398	20	0	0
T17	1907	0	0	0
T19	0	10	0	0
T20	0	20	0	0
T21	4559	0	0	0
T36	1056	0	0	0
T42	196572	0	0	0
T45	4196	0	0	0
T47	2817	0	0	0
T51	2231	0	0	0
T60	1494	0	0	0
T61	13211	0	0	0
T62	0	10	0	0
T63	0	10	0	0

gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221079372	70	0	0
T16	46398	20	0	0
T17	1907	0	0	0
T19	0	10	0	0
T20	0	20	0	0
T21	4559	0	0	0
T36	1056	0	0	0
T42	196572	0	0	0
T45	4196	0	0	0
T47	2817	0	0	0
T51	2231	0	0	0
T60	1494	0	0	0
T61	13211	0	0	0
T62	0	10	0	0
T63	0	10	0	0

gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221079372	70	0	0
T16	46398	20	0	0
T17	1907	0	0	0
T19	0	10	0	0
T20	0	20	0	0
T21	4559	0	0	0
T36	1056	0	0	0
T42	196572	0	0	0
T45	4196	0	0	0
T47	2817	0	0	0
T51	2231	0	0	0
T60	1494	0	0	0
T61	13211	0	0	0
T62	0	10	0	0
T63	0	10	0	0

gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221079372	70	0	0
T16	46398	20	0	0
T17	1907	0	0	0
T19	0	10	0	0
T20	0	20	0	0
T21	4559	0	0	0
T36	1056	0	0	0
T42	196572	0	0	0
T45	4196	0	0	0
T47	2817	0	0	0
T51	2231	0	0	0
T60	1494	0	0	0
T61	13211	0	0	0
T62	0	10	0	0
T63	0	10	0	0

gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221079372	70	0	0
T16	46398	20	0	0
T17	1907	0	0	0
T19	0	10	0	0
T20	0	20	0	0
T21	4559	0	0	0
T36	1056	0	0	0
T42	196572	0	0	0
T45	4196	0	0	0
T47	2817	0	0	0
T51	2231	0	0	0
T60	1494	0	0	0
T61	13211	0	0	0
T62	0	10	0	0
T63	0	10	0	0

gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221079372	70	0	0
T16	46398	20	0	0
T17	1907	0	0	0
T19	0	10	0	0
T20	0	20	0	0
T21	4559	0	0	0
T36	1056	0	0	0
T42	196572	0	0	0
T45	4196	0	0	0
T47	2817	0	0	0
T51	2231	0	0	0
T60	1494	0	0	0
T61	13211	0	0	0
T62	0	10	0	0
T63	0	10	0	0

gen_edn_if_asserts[0].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221079372	559637	0	332
T1	521601	1656	0	2
T2	1659	1589	0	2
T3	2209	14	0	0
T4	5263	1346	0	0
T6	1273	93	0	0
T12	0	0	0	2
T16	0	0	0	2
T23	3700	23	0	0
T24	3737	27	0	0
T25	891	41	0	0
T26	687	90	0	0
T27	3993	163	0	0
T42	0	0	0	2
T43	0	0	0	2
T64	0	0	0	2
T65	0	0	0	2
T66	0	0	0	2
T67	0	0	0	2

gen_edn_if_asserts[0].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221079372	26226	0	337
T1	521601	65	0	0
T2	1659	0	0	0
T3	2209	0	0	0
T4	5263	3	0	1
T5	0	12	0	1
T6	1273	3	0	1
T10	0	0	0	1
T23	3700	11	0	1
T24	3737	66	0	1
T25	891	3	0	1
T26	687	0	0	0
T27	3993	7	0	1
T44	0	15	0	1
T68	0	19	0	1

gen_edn_if_asserts[0].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221079372	220911394	0	0
T1	521601	521587	0	0
T2	1659	1591	0	0
T3	2209	2114	0	0
T4	5263	4993	0	0
T6	1273	1210	0	0
T23	3700	3616	0	0
T24	3737	3666	0	0
T25	891	830	0	0
T26	687	634	0	0
T27	3993	3911	0	0

gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221079372	156450	0	0
T7	0	1112	0	0
T8	0	196	0	0
T9	0	664	0	0
T16	46398	18672	0	0
T17	1907	1104	0	0
T18	0	663	0	0
T21	4559	0	0	0
T33	0	7	0	0
T34	0	7	0	0
T36	1056	602	0	0
T42	196572	0	0	0
T45	4196	0	0	0
T47	2817	0	0	0
T51	2231	0	0	0
T55	0	354	0	0
T60	1494	0	0	0
T61	13211	0	0	0

gen_edn_if_asserts[1].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221079372	559637	0	332
T1	521601	1656	0	2
T2	1659	1589	0	2
T3	2209	14	0	0
T4	5263	1346	0	0
T6	1273	93	0	0
T12	0	0	0	2
T16	0	0	0	2
T23	3700	23	0	0
T24	3737	27	0	0
T25	891	41	0	0
T26	687	90	0	0
T27	3993	163	0	0
T42	0	0	0	2
T43	0	0	0	2
T64	0	0	0	2
T65	0	0	0	2
T66	0	0	0	2
T67	0	0	0	2

gen_edn_if_asserts[1].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221079372	5584	0	132
T3	2209	3	0	1
T4	5263	0	0	0
T6	1273	0	0	0
T12	0	4	0	0
T23	3700	0	0	0
T24	3737	0	0	0
T25	891	0	0	0
T26	687	0	0	0
T27	3993	0	0	0
T44	2862	3	0	1
T45	0	21	0	1
T46	0	3	0	1
T47	0	3	0	1
T48	0	23	0	1
T49	0	46	0	1
T50	0	3	0	1
T51	0	3	0	1
T52	0	0	0	1
T68	3920	0	0	0

gen_edn_if_asserts[1].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221079372	220911394	0	0
T1	521601	521587	0	0
T2	1659	1591	0	0
T3	2209	2114	0	0
T4	5263	4993	0	0
T6	1273	1210	0	0
T23	3700	3616	0	0
T24	3737	3666	0	0
T25	891	830	0	0
T26	687	634	0	0
T27	3993	3911	0	0

gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221079372	156450	0	0
T7	0	1112	0	0
T8	0	196	0	0
T9	0	664	0	0
T16	46398	18672	0	0
T17	1907	1104	0	0
T18	0	663	0	0
T21	4559	0	0	0
T33	0	7	0	0
T34	0	7	0	0
T36	1056	602	0	0
T42	196572	0	0	0
T45	4196	0	0	0
T47	2817	0	0	0
T51	2231	0	0	0
T55	0	354	0	0
T60	1494	0	0	0
T61	13211	0	0	0

gen_edn_if_asserts[2].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221079372	559637	0	332
T1	521601	1656	0	2
T2	1659	1589	0	2
T3	2209	14	0	0
T4	5263	1346	0	0
T6	1273	93	0	0
T12	0	0	0	2
T16	0	0	0	2
T23	3700	23	0	0
T24	3737	27	0	0
T25	891	41	0	0
T26	687	90	0	0
T27	3993	163	0	0
T42	0	0	0	2
T43	0	0	0	2
T64	0	0	0	2
T65	0	0	0	2
T66	0	0	0	2
T67	0	0	0	2

gen_edn_if_asserts[2].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221079372	3343	0	134
T3	2209	3	0	1
T4	5263	0	0	0
T6	1273	0	0	0
T10	0	57	0	1
T11	0	8	0	1
T23	3700	0	0	0
T24	3737	0	0	0
T25	891	0	0	0
T26	687	0	0	0
T27	3993	0	0	0
T33	0	1	0	0
T44	2862	0	0	0
T45	0	35	0	1
T46	0	3	0	1
T47	0	5	0	1
T48	0	57	0	1
T49	0	0	0	1
T50	0	21	0	1
T51	0	3	0	1
T68	3920	0	0	0

gen_edn_if_asserts[2].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221079372	220911394	0	0
T1	521601	521587	0	0
T2	1659	1591	0	0
T3	2209	2114	0	0
T4	5263	4993	0	0
T6	1273	1210	0	0
T23	3700	3616	0	0
T24	3737	3666	0	0
T25	891	830	0	0
T26	687	634	0	0
T27	3993	3911	0	0

gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221079372	156450	0	0
T7	0	1112	0	0
T8	0	196	0	0
T9	0	664	0	0
T16	46398	18672	0	0
T17	1907	1104	0	0
T18	0	663	0	0
T21	4559	0	0	0
T33	0	7	0	0
T34	0	7	0	0
T36	1056	602	0	0
T42	196572	0	0	0
T45	4196	0	0	0
T47	2817	0	0	0
T51	2231	0	0	0
T55	0	354	0	0
T60	1494	0	0	0
T61	13211	0	0	0

gen_edn_if_asserts[3].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221079372	559637	0	332
T1	521601	1656	0	2
T2	1659	1589	0	2
T3	2209	14	0	0
T4	5263	1346	0	0
T6	1273	93	0	0
T12	0	0	0	2
T16	0	0	0	2
T23	3700	23	0	0
T24	3737	27	0	0
T25	891	41	0	0
T26	687	90	0	0
T27	3993	163	0	0
T42	0	0	0	2
T43	0	0	0	2
T64	0	0	0	2
T65	0	0	0	2
T66	0	0	0	2
T67	0	0	0	2

gen_edn_if_asserts[3].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221079372	3236	0	119
T10	4882	3	0	1
T11	2443	0	0	0
T12	3119	0	0	0
T16	46398	0	0	0
T17	1907	0	0	0
T21	0	53	0	1
T36	1056	0	0	0
T45	4196	38	0	1
T46	2290	0	0	0
T47	0	3	0	1
T48	0	39	0	1
T49	0	3	0	1
T51	0	36	0	1
T52	0	3	0	1
T60	1494	0	0	0
T64	21042	0	0	0
T69	0	18	0	1
T70	0	15	0	1

gen_edn_if_asserts[3].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221079372	220911394	0	0
T1	521601	521587	0	0
T2	1659	1591	0	0
T3	2209	2114	0	0
T4	5263	4993	0	0
T6	1273	1210	0	0
T23	3700	3616	0	0
T24	3737	3666	0	0
T25	891	830	0	0
T26	687	634	0	0
T27	3993	3911	0	0

gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221079372	156450	0	0
T7	0	1112	0	0
T8	0	196	0	0
T9	0	664	0	0
T16	46398	18672	0	0
T17	1907	1104	0	0
T18	0	663	0	0
T21	4559	0	0	0
T33	0	7	0	0
T34	0	7	0	0
T36	1056	602	0	0
T42	196572	0	0	0
T45	4196	0	0	0
T47	2817	0	0	0
T51	2231	0	0	0
T55	0	354	0	0
T60	1494	0	0	0
T61	13211	0	0	0

gen_edn_if_asserts[4].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221079372	559637	0	332
T1	521601	1656	0	2
T2	1659	1589	0	2
T3	2209	14	0	0
T4	5263	1346	0	0
T6	1273	93	0	0
T12	0	0	0	2
T16	0	0	0	2
T23	3700	23	0	0
T24	3737	27	0	0
T25	891	41	0	0
T26	687	90	0	0
T27	3993	163	0	0
T42	0	0	0	2
T43	0	0	0	2
T64	0	0	0	2
T65	0	0	0	2
T66	0	0	0	2
T67	0	0	0	2

gen_edn_if_asserts[4].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221079372	5062	0	105
T16	46398	0	0	0
T17	1907	0	0	0
T21	0	3	0	1
T36	1056	0	0	0
T42	196572	0	0	0
T45	4196	19	0	1
T46	2290	3	0	1
T47	2817	3	0	1
T48	0	15	0	1
T49	0	3	0	1
T50	0	14	0	1
T51	0	3	0	1
T52	0	3	0	1
T60	1494	0	0	0
T61	13211	0	0	0
T64	21042	0	0	0
T71	0	15	0	1

gen_edn_if_asserts[4].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221079372	220911394	0	0
T1	521601	521587	0	0
T2	1659	1591	0	0
T3	2209	2114	0	0
T4	5263	4993	0	0
T6	1273	1210	0	0
T23	3700	3616	0	0
T24	3737	3666	0	0
T25	891	830	0	0
T26	687	634	0	0
T27	3993	3911	0	0

gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221079372	156450	0	0
T7	0	1112	0	0
T8	0	196	0	0
T9	0	664	0	0
T16	46398	18672	0	0
T17	1907	1104	0	0
T18	0	663	0	0
T21	4559	0	0	0
T33	0	7	0	0
T34	0	7	0	0
T36	1056	602	0	0
T42	196572	0	0	0
T45	4196	0	0	0
T47	2817	0	0	0
T51	2231	0	0	0
T55	0	354	0	0
T60	1494	0	0	0
T61	13211	0	0	0

gen_edn_if_asserts[5].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221079372	559637	0	332
T1	521601	1656	0	2
T2	1659	1589	0	2
T3	2209	14	0	0
T4	5263	1346	0	0
T6	1273	93	0	0
T12	0	0	0	2
T16	0	0	0	2
T23	3700	23	0	0
T24	3737	27	0	0
T25	891	41	0	0
T26	687	90	0	0
T27	3993	163	0	0
T42	0	0	0	2
T43	0	0	0	2
T64	0	0	0	2
T65	0	0	0	2
T66	0	0	0	2
T67	0	0	0	2

gen_edn_if_asserts[5].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221079372	3543	0	105
T16	46398	0	0	0
T17	1907	0	0	0
T21	0	28	0	1
T36	1056	0	0	0
T42	196572	0	0	0
T45	4196	33	0	1
T46	2290	38	0	1
T47	2817	43	0	1
T50	0	34	0	1
T51	0	47	0	1
T52	0	37	0	1
T60	1494	0	0	0
T61	13211	0	0	0
T64	21042	0	0	0
T69	0	11	0	1
T70	0	3	0	1
T72	0	47	0	1

gen_edn_if_asserts[5].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221079372	220911394	0	0
T1	521601	521587	0	0
T2	1659	1591	0	0
T3	2209	2114	0	0
T4	5263	4993	0	0
T6	1273	1210	0	0
T23	3700	3616	0	0
T24	3737	3666	0	0
T25	891	830	0	0
T26	687	634	0	0
T27	3993	3911	0	0

gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221079372	156450	0	0
T7	0	1112	0	0
T8	0	196	0	0
T9	0	664	0	0
T16	46398	18672	0	0
T17	1907	1104	0	0
T18	0	663	0	0
T21	4559	0	0	0
T33	0	7	0	0
T34	0	7	0	0
T36	1056	602	0	0
T42	196572	0	0	0
T45	4196	0	0	0
T47	2817	0	0	0
T51	2231	0	0	0
T55	0	354	0	0
T60	1494	0	0	0
T61	13211	0	0	0

gen_edn_if_asserts[6].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221079372	559637	0	332
T1	521601	1656	0	2
T2	1659	1589	0	2
T3	2209	14	0	0
T4	5263	1346	0	0
T6	1273	93	0	0
T12	0	0	0	2
T16	0	0	0	2
T23	3700	23	0	0
T24	3737	27	0	0
T25	891	41	0	0
T26	687	90	0	0
T27	3993	163	0	0
T42	0	0	0	2
T43	0	0	0	2
T64	0	0	0	2
T65	0	0	0	2
T66	0	0	0	2
T67	0	0	0	2

gen_edn_if_asserts[6].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221079372	51332	0	84
T5	22590	0	0	0
T10	4882	0	0	0
T11	2443	0	0	0
T12	3119	0	0	0
T21	0	3	0	1
T26	687	4	0	0
T27	3993	0	0	0
T44	2862	0	0	0
T45	0	29	0	1
T46	2290	19	0	1
T47	0	15	0	1
T50	0	3	0	1
T51	0	3	0	1
T52	0	28	0	1
T64	21042	0	0	0
T68	3920	0	0	0
T70	0	579	0	1
T72	0	0	0	1
T73	0	4	0	0
T74	0	0	0	1

gen_edn_if_asserts[6].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221079372	220911394	0	0
T1	521601	521587	0	0
T2	1659	1591	0	0
T3	2209	2114	0	0
T4	5263	4993	0	0
T6	1273	1210	0	0
T23	3700	3616	0	0
T24	3737	3666	0	0
T25	891	830	0	0
T26	687	634	0	0
T27	3993	3911	0	0

gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221079372	156450	0	0
T7	0	1112	0	0
T8	0	196	0	0
T9	0	664	0	0
T16	46398	18672	0	0
T17	1907	1104	0	0
T18	0	663	0	0
T21	4559	0	0	0
T33	0	7	0	0
T34	0	7	0	0
T36	1056	602	0	0
T42	196572	0	0	0
T45	4196	0	0	0
T47	2817	0	0	0
T51	2231	0	0	0
T55	0	354	0	0
T60	1494	0	0	0
T61	13211	0	0	0