Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44		83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	221598521	10050457	0	0
boot_gen_cmd_rd_A	221598521	43957	0	0
boot_ins_cmd_rd_A	221598521	49730	0	0
ctrl_rd_A	221598521	43184	0	0
err_code_test_rd_A	221598521	48719	0	0
intr_enable_rd_A	221598521	49747	0	0
max_num_reqs_between_reseeds_rd_A	221598521	43896	0	0
regwen_rd_A	221598521	50736	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221598521	10050457	0	0
T1	521601	298387	0	0
T2	1659	0	0	0
T3	2209	0	0	0
T4	5263	0	0	0
T6	1273	0	0	0
T23	3700	0	0	0
T24	3737	0	0	0
T25	891	0	0	0
T26	687	0	0	0
T27	3993	0	0	0
T42	0	113252	0	0
T43	0	458004	0	0
T65	0	130727	0	0
T66	0	324418	0	0
T67	0	60140	0	0
T81	0	96811	0	0
T178	0	114098	0	0
T202	0	326079	0	0
T203	0	138713	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221598521	43957	0	0
T28	1564	0	0	0
T32	2089	0	0	0
T52	2272	0	0	0
T67	160194	756	0	0
T71	2524	0	0	0
T81	244965	0	0	0
T90	2027	0	0	0
T149	823	0	0	0
T178	0	3534	0	0
T203	0	4320	0	0
T204	0	5586	0	0
T205	0	1855	0	0
T206	0	2880	0	0
T207	0	3693	0	0
T208	0	4487	0	0
T209	0	6205	0	0
T210	0	582	0	0
T211	873	0	0	0
T212	1659	0	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221598521	49730	0	0
T28	1564	0	0	0
T32	2089	0	0	0
T52	2272	0	0	0
T67	160194	1042	0	0
T71	2524	0	0	0
T81	244965	0	0	0
T90	2027	0	0	0
T149	823	0	0	0
T178	0	3803	0	0
T203	0	4491	0	0
T204	0	6912	0	0
T205	0	2236	0	0
T206	0	3274	0	0
T207	0	4283	0	0
T208	0	4700	0	0
T209	0	7053	0	0
T210	0	658	0	0
T211	873	0	0	0
T212	1659	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221598521	43184	0	0
T28	1564	0	0	0
T32	2089	0	0	0
T52	2272	0	0	0
T67	160194	911	0	0
T71	2524	0	0	0
T76	0	3	0	0
T81	244965	0	0	0
T90	2027	0	0	0
T149	823	0	0	0
T178	0	3466	0	0
T203	0	3834	0	0
T204	0	5965	0	0
T205	0	2075	0	0
T206	0	2772	0	0
T207	0	3639	0	0
T208	0	4194	0	0
T211	873	0	0	0
T212	1659	0	0	0
T213	0	8	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221598521	48719	0	0
T28	1564	0	0	0
T32	2089	0	0	0
T52	2272	0	0	0
T67	160194	974	0	0
T71	2524	0	0	0
T81	244965	0	0	0
T90	2027	0	0	0
T149	823	0	0	0
T178	0	3644	0	0
T203	0	4689	0	0
T204	0	6337	0	0
T205	0	2220	0	0
T206	0	3227	0	0
T207	0	4215	0	0
T208	0	4789	0	0
T209	0	7073	0	0
T210	0	716	0	0
T211	873	0	0	0
T212	1659	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221598521	49747	0	0
T18	1142	0	0	0
T48	3905	0	0	0
T49	1525	0	0	0
T52	2272	0	0	0
T66	588416	0	0	0
T67	160194	1195	0	0
T80	41509	71	0	0
T81	244965	0	0	0
T178	0	3674	0	0
T203	0	4577	0	0
T204	0	6018	0	0
T205	0	2157	0	0
T206	0	3046	0	0
T211	873	0	0	0
T212	1659	17	0	0
T214	0	11	0	0
T215	0	63	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221598521	43896	0	0
T28	1564	0	0	0
T32	2089	0	0	0
T52	2272	0	0	0
T67	160194	846	0	0
T71	2524	0	0	0
T81	244965	0	0	0
T90	2027	0	0	0
T149	823	0	0	0
T178	0	3275	0	0
T203	0	4045	0	0
T204	0	5617	0	0
T205	0	1964	0	0
T206	0	2844	0	0
T207	0	3779	0	0
T208	0	3992	0	0
T209	0	6231	0	0
T210	0	609	0	0
T211	873	0	0	0
T212	1659	0	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221598521	50736	0	0
T28	1564	0	0	0
T32	2089	0	0	0
T52	2272	0	0	0
T67	160194	1023	0	0
T71	2524	0	0	0
T81	244965	0	0	0
T90	2027	0	0	0
T149	823	0	0	0
T178	0	3688	0	0
T203	0	4812	0	0
T204	0	6765	0	0
T205	0	2193	0	0
T206	0	3249	0	0
T207	0	4006	0	0
T208	0	5055	0	0
T209	0	7042	0	0
T210	0	629	0	0
T211	873	0	0	0
T212	1659	0	0	0