Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	567552	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4452737

1

T1

64

T2

5

T3

257

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1336928	1			T1	444		T2	2		T3	581
values[0x0]	1704844	1			T1	30		T2	3		T3	41
values[0x1]	1978517	1			T1	33		T2	2		T3	28

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	284906	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

4735383

1

T1

205

T2

6

T3

358

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	19666	1			T1	4		T17	1		T54	1
valid_sources[0x01]	18837	1			T20	1		T54	1		T55	9
valid_sources[0x02]	21699	1			T1	2		T55	1		T56	4
valid_sources[0x03]	18027	1			T1	1		T9	1		T20	1
valid_sources[0x04]	20274	1			T1	3		T9	1		T63	1
valid_sources[0x05]	18806	1			T1	5		T55	4		T56	5
valid_sources[0x06]	19861	1			T1	2		T9	1		T55	8
valid_sources[0x07]	19620	1			T1	4		T20	1		T55	2
valid_sources[0x08]	19343	1			T1	1		T54	1		T35	265
valid_sources[0x09]	19392	1			T1	2		T55	3		T35	267
valid_sources[0x0a]	18636	1			T9	1		T20	1		T55	2
valid_sources[0x0b]	18430	1			T1	2		T17	1		T63	1
valid_sources[0x0c]	19340	1			T1	1		T20	2		T55	2
valid_sources[0x0d]	21528	1			T1	3		T17	1		T55	1
valid_sources[0x0e]	22996	1			T1	1		T9	1		T55	1
valid_sources[0x0f]	20175	1			T1	2		T56	4		T35	265
valid_sources[0x10]	19029	1			T9	1		T63	1		T54	2
valid_sources[0x11]	20361	1			T1	2		T9	1		T56	10
valid_sources[0x12]	19043	1			T1	3		T20	1		T54	2
valid_sources[0x13]	20010	1			T1	1		T55	4		T35	258
valid_sources[0x14]	23016	1			T1	1		T17	1		T20	1
valid_sources[0x15]	19058	1			T1	3		T9	1		T55	2
valid_sources[0x16]	20211	1			T1	4		T17	1		T20	1
valid_sources[0x17]	21402	1			T20	1		T55	1		T35	312
valid_sources[0x18]	19940	1			T17	1		T20	1		T5	1
valid_sources[0x19]	21345	1			T1	6		T9	1		T55	7
valid_sources[0x1a]	20571	1			T1	1		T17	1		T70	6
valid_sources[0x1b]	19753	1			T1	4		T17	1		T55	2
valid_sources[0x1c]	19843	1			T1	1		T9	2		T54	1
valid_sources[0x1d]	21583	1			T1	2		T54	2		T55	1
valid_sources[0x1e]	21154	1			T1	1		T17	1		T63	1
valid_sources[0x1f]	21040	1			T1	1		T9	1		T17	1
valid_sources[0x20]	17974	1			T1	2		T55	4		T56	7
valid_sources[0x21]	19671	1			T63	1		T54	3		T73	1
valid_sources[0x22]	19511	1			T1	1		T18	5		T54	4
valid_sources[0x23]	18968	1			T55	1		T73	2		T35	269
valid_sources[0x24]	20140	1			T1	1		T9	1		T55	7
valid_sources[0x25]	20271	1			T1	2		T9	2		T54	1
valid_sources[0x26]	20645	1			T1	5		T54	2		T55	4
valid_sources[0x27]	20964	1			T1	1		T9	1		T17	2
valid_sources[0x28]	20382	1			T1	2		T17	1		T54	1
valid_sources[0x29]	20001	1			T1	3		T55	3		T56	5
valid_sources[0x2a]	18677	1			T1	7		T9	1		T17	1
valid_sources[0x2b]	20093	1			T1	1		T9	1		T55	4
valid_sources[0x2c]	19062	1			T1	4		T54	1		T55	3
valid_sources[0x2d]	18396	1			T1	2		T17	1		T55	6
valid_sources[0x2e]	19320	1			T1	1		T17	1		T55	1
valid_sources[0x2f]	20254	1			T1	4		T9	1		T17	1
valid_sources[0x30]	20157	1			T1	2		T17	3		T54	1
valid_sources[0x31]	18791	1			T9	5		T55	2		T56	12
valid_sources[0x32]	17594	1			T1	3		T9	1		T17	1
valid_sources[0x33]	20219	1			T1	1		T73	1		T56	3
valid_sources[0x34]	21609	1			T55	7		T56	15		T35	236
valid_sources[0x35]	18429	1			T1	1		T17	3		T20	1
valid_sources[0x36]	19797	1			T17	3		T55	2		T56	2
valid_sources[0x37]	18669	1			T1	1		T20	1		T54	1
valid_sources[0x38]	19672	1			T1	1		T9	2		T20	1
valid_sources[0x39]	19044	1			T1	3		T63	1		T73	1
valid_sources[0x3a]	18796	1			T1	1		T9	3		T54	1
valid_sources[0x3b]	17522	1			T9	1		T55	10		T73	1
valid_sources[0x3c]	19460	1			T1	2		T17	1		T54	3
valid_sources[0x3d]	18774	1			T73	1		T35	289		T27	1
valid_sources[0x3e]	18742	1			T1	1		T54	2		T55	3
valid_sources[0x3f]	20760	1			T1	2		T9	1		T17	1
valid_sources[0x40]	18637	1			T1	3		T20	4		T54	1
valid_sources[0x41]	20637	1			T1	1		T4	7		T55	3
valid_sources[0x42]	20419	1			T1	5		T10	90		T55	4
valid_sources[0x43]	18048	1			T1	4		T9	1		T38	3
valid_sources[0x44]	18769	1			T1	3		T9	1		T17	1
valid_sources[0x45]	19537	1			T1	1		T17	1		T55	4
valid_sources[0x46]	20006	1			T1	1		T55	2		T35	256
valid_sources[0x47]	19675	1			T1	3		T54	5		T55	8
valid_sources[0x48]	20603	1			T1	1		T2	7		T17	1
valid_sources[0x49]	19289	1			T1	2		T9	2		T42	5
valid_sources[0x4a]	18360	1			T55	4		T35	310		T27	1
valid_sources[0x4b]	19421	1			T1	4		T9	1		T54	1
valid_sources[0x4c]	19079	1			T1	2		T9	1		T17	1
valid_sources[0x4d]	18007	1			T1	3		T9	1		T17	1
valid_sources[0x4e]	20106	1			T1	3		T73	1		T56	3
valid_sources[0x4f]	18500	1			T1	1		T54	1		T55	2
valid_sources[0x50]	19931	1			T1	2		T9	1		T17	2
valid_sources[0x51]	19105	1			T17	1		T54	1		T35	309
valid_sources[0x52]	19931	1			T1	2		T9	1		T19	22
valid_sources[0x53]	22026	1			T1	3		T17	2		T55	4
valid_sources[0x54]	18499	1			T1	4		T54	1		T73	1
valid_sources[0x55]	19512	1			T1	3		T63	1		T54	1
valid_sources[0x56]	19212	1			T54	1		T73	1		T35	285
valid_sources[0x57]	18985	1			T1	1		T17	1		T20	1
valid_sources[0x58]	19185	1			T1	4		T9	1		T35	266
valid_sources[0x59]	19340	1			T1	4		T9	2		T17	1
valid_sources[0x5a]	18954	1			T1	2		T17	1		T55	4
valid_sources[0x5b]	21218	1			T1	3		T9	1		T5	1
valid_sources[0x5c]	19648	1			T55	16		T56	6		T35	313
valid_sources[0x5d]	18234	1			T1	6		T9	4		T17	1
valid_sources[0x5e]	19333	1			T1	2		T9	2		T19	7
valid_sources[0x5f]	18861	1			T1	1		T9	1		T55	1
valid_sources[0x60]	18426	1			T1	4		T4	1		T9	3
valid_sources[0x61]	19249	1			T1	2		T63	3		T35	292
valid_sources[0x62]	19199	1			T1	1		T4	1		T9	1
valid_sources[0x63]	19924	1			T1	4		T4	4		T63	1
valid_sources[0x64]	20143	1			T1	1		T9	1		T63	2
valid_sources[0x65]	18654	1			T19	1		T54	2		T55	9
valid_sources[0x66]	20955	1			T1	3		T20	1		T39	323
valid_sources[0x67]	19415	1			T1	2		T9	2		T17	2
valid_sources[0x68]	19817	1			T1	1		T17	1		T55	1
valid_sources[0x69]	21766	1			T1	2		T9	1		T20	1
valid_sources[0x6a]	20564	1			T73	1		T35	280		T12	1
valid_sources[0x6b]	18205	1			T9	3		T20	1		T63	1
valid_sources[0x6c]	18825	1			T1	4		T9	3		T54	3
valid_sources[0x6d]	19316	1			T1	3		T56	4		T35	320
valid_sources[0x6e]	19084	1			T1	4		T17	2		T20	1
valid_sources[0x6f]	20052	1			T1	3		T9	4		T35	266
valid_sources[0x70]	19324	1			T1	3		T54	1		T55	2
valid_sources[0x71]	20204	1			T1	1		T19	1		T20	2
valid_sources[0x72]	20286	1			T19	4		T17	1		T54	1
valid_sources[0x73]	21221	1			T17	2		T54	1		T55	3
valid_sources[0x74]	17960	1			T1	2		T9	1		T17	1
valid_sources[0x75]	18555	1			T1	2		T20	1		T55	1
valid_sources[0x76]	20274	1			T1	4		T9	1		T17	1
valid_sources[0x77]	19230	1			T9	1		T17	1		T54	4
valid_sources[0x78]	20819	1			T1	7		T5	1		T55	6
valid_sources[0x79]	18943	1			T1	1		T9	1		T17	1
valid_sources[0x7a]	19546	1			T1	1		T9	1		T63	2
valid_sources[0x7b]	19596	1			T1	4		T54	2		T55	1
valid_sources[0x7c]	19061	1			T26	1		T54	1		T35	265
valid_sources[0x7d]	19115	1			T9	1		T5	1		T22	1
valid_sources[0x7e]	20376	1			T1	1		T54	2		T35	268
valid_sources[0x7f]	18473	1			T1	1		T9	1		T55	3
valid_sources[0x80]	19348	1			T1	2		T17	1		T20	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1122011

1

T1

5

T2

1

T3

225

values[0x0]

all_enables

biggest_size

1667849

1

T1

29

T2

2

T3

21

values[0x1]

all_enables

biggest_size

1662877

1

T1

30

T2

2

T3

11