Unified Coverage Report :: Group :: csrng_agent_pkg::device_cmd_cg

Group : csrng_agent_pkg::device_cmd_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
60.94	60.94	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg	60.94	1	100	1	64	64

---

Group Instance : csrng_agent_pkg.csrng_device_cmd_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
60.94	1	100	1	64	64

---

Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	52	25	27	51.92

Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_clen_cp	3	0	3	100.00	100	1	1	0
csrng_cmd_cp	5	0	5	100.00	100	1	1	0
csrng_flag_cp	2	0	2	100.00	100	1	1	0
csrng_sts	2	0	2	100.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_cmd_cross	52	25	27	51.92	100	1	1	0

Summary for Variable csrng_clen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csrng_clen_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
non_zero_bins[0]	2627	1			T1	4		T9	5		T10	3
non_zero_bins[1]	1831	1			T1	3		T9	2		T10	4
zero	8221	1			T1	1		T2	4		T4	2

---

Summary for Variable csrng_cmd_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	521	1			T19	1		T54	1		T55	1
uni	3521	1			T1	1		T9	1		T10	1
gen	3878	1			T1	4		T2	2		T4	1
res	812	1			T1	2		T9	2		T10	2
ins	3947	1			T1	1		T2	2		T4	1

---

Summary for Variable csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_flag_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

mubi_false

8500

1

T1

6

T4

2

T9

5

mubi_true

4179

1

T1

2

T2

4

T9

3

---

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_sts

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fail

5

1

T50

1

T51

1

T115

1

pass

12674

1

T1

8

T2

4

T4

2

---

Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	52	25	27	51.92	25
Automatically Generated Cross Bins	52	25	27	51.92	25
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for csrng_cmd_cross

Element holes

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[upd]	*	[fail]	*	--	--	6
[uni]	[zero]	[fail]	*	--	--	2
[gen]	[non_zero_bins[0] , non_zero_bins[1]]	[fail]	*	--	--	4
[res , ins]	*	[fail]	*	--	--	12

Uncovered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[gen]	[zero]	[fail]	[mubi_true]	0	1	1

Covered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	non_zero_bins[0]	pass	mubi_false	113	1			T54	1		T35	1		T265	1
upd	non_zero_bins[0]	pass	mubi_true	126	1			T36	3		T37	2		T92	2
upd	non_zero_bins[1]	pass	mubi_false	86	1			T36	3		T68	2		T37	1
upd	non_zero_bins[1]	pass	mubi_true	92	1			T19	1		T55	1		T37	2
upd	zero	pass	mubi_false	54	1			T35	1		T44	1		T92	1
upd	zero	pass	mubi_true	50	1			T40	1		T35	1		T37	2
uni	zero	pass	mubi_false	2625	1			T1	1		T9	1		T10	1
uni	zero	pass	mubi_true	896	1			T39	1		T54	1		T55	3
gen	non_zero_bins[0]	pass	mubi_false	452	1			T1	3		T10	1		T56	2
gen	non_zero_bins[0]	pass	mubi_true	572	1			T1	1		T9	3		T17	3
gen	non_zero_bins[1]	pass	mubi_false	307	1			T9	1		T17	1		T40	1
gen	non_zero_bins[1]	pass	mubi_true	365	1			T10	3		T19	1		T39	1
gen	zero	fail	mubi_false	5	1			T50	1		T51	1		T115	1
gen	zero	pass	mubi_false	1761	1			T4	1		T19	1		T21	2
gen	zero	pass	mubi_true	416	1			T2	2		T18	1		T5	2
res	non_zero_bins[0]	pass	mubi_false	188	1			T9	2		T56	1		T35	2
res	non_zero_bins[0]	pass	mubi_true	164	1			T10	2		T73	2		T49	2
res	non_zero_bins[1]	pass	mubi_false	139	1			T1	2		T17	2		T20	2
res	non_zero_bins[1]	pass	mubi_true	138	1			T35	1		T36	1		T37	2
res	zero	pass	mubi_false	80	1			T36	1		T69	1		T217	1
res	zero	pass	mubi_true	103	1			T63	1		T56	1		T35	1
ins	non_zero_bins[0]	pass	mubi_false	516	1			T19	1		T63	1		T39	1
ins	non_zero_bins[0]	pass	mubi_true	496	1			T39	1		T73	1		T56	1
ins	non_zero_bins[1]	pass	mubi_false	348	1			T9	1		T10	1		T56	2
ins	non_zero_bins[1]	pass	mubi_true	356	1			T1	1		T54	1		T55	1
ins	zero	pass	mubi_false	1826	1			T4	1		T5	3		T38	2
ins	zero	pass	mubi_true	405	1			T2	2		T18	1		T19	1

User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
uni_clen	0	Excluded