Unified Coverage Report :: Module :: edn_main_sm

Module : edn_main_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.60	100.00	94.44		95.95	97.62	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_edn_main_sm	97.60	100.00	94.44		95.95	97.62	100.00

---

Module Instance : tb.dut.u_edn_core.u_edn_main_sm

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.60	100.00	94.44		95.95	97.62	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.62	100.00	94.44		95.95	97.73	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.12	100.00	90.40			98.10	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
TOTAL		108	108	100.00
ALWAYS	42	3	3	100.00
CONT_ASSIGN	44	1	1	100.00
ALWAYS	47	104	104	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	3	3
44	1	1
47	1	1
48	1	1
49	1	1
50	1	1
51	1	1
52	1	1
53	1	1
54	1	1
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
61	1	1
62	1	1
64	1	1
65	1	1
66	1	1
67	1	1
68	1	1
69	1	1
70	1	1
71	1	1
72	1	1
73	1	1
74	1	1
			MISSING_ELSE
78	1	1
79	1	1
80	1	1
83	1	1
84	1	1
85	1	1
			MISSING_ELSE
89	1	1
90	1	1
93	1	1
94	1	1
			MISSING_ELSE
98	1	1
101	1	1
102	1	1
			MISSING_ELSE
106	1	1
107	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
117	1	1
118	1	1
119	1	1
			MISSING_ELSE
123	1	1
124	1	1
125	1	1
			MISSING_ELSE
129	1	1
130	1	1
131	1	1
			MISSING_ELSE
135	1	1
136	1	1
137	1	1
138	1	1
140	1	1
141	1	1
143	1	1
148	1	1
149	1	1
150	1	1
153	1	1
154	1	1
155	1	1
156	1	1
			MISSING_ELSE
160	1	1
161	1	1
162	1	1
165	1	1
166	1	1
167	1	1
168	1	1
			MISSING_ELSE
172	1	1
175	1	1
178	1	1
186	1	1
188	1	1
192	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
201	1	1
211	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_main_sm

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (boot_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T2,T18,T5
1	1	Covered	T2,T18,T19

 LINE       66
 EXPRESSION (auto_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T49,T6,T7
1	1	Covered	T1,T9,T10

 LINE       186
 EXPRESSION (local_escalate_i || csrng_ack_err_i)
             --------1-------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T26,T27,T28
1	0	Covered	T3,T5,T22

 LINE       188
 EXPRESSION (local_escalate_i ? Error : ((state_q == Error) ? Error : RejectCsrngEntropy))
             --------1-------

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T3,T5,T22

 LINE       188
 SUB-EXPRESSION ((state_q == Error) ? Error : RejectCsrngEntropy)
                 ---------1--------

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Not Covered

 LINE       188
 SUB-EXPRESSION (state_q == Error)
                ---------1--------

-1-	Status	Tests
0	Covered	T3,T5,T22
1	Covered	T3,T5,T22

 LINE       201
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_i)) && 
      2  (state_q inside {BootLoadIns, BootInsAckWait, BootLoadGen, BootGenAckWait, BootLoadUni, BootUniAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode, RejectCsrngEntropy}))

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T18

---

FSM Coverage for Module : edn_main_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	20	20	100.00	(Not included in score)
Transitions	74	71	95.95
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AutoAckWait	156	Covered	T1,T9,T10
AutoCaptGenCnt	143	Covered	T1,T9,T10
AutoCaptReseedCnt	141	Covered	T1,T9,T10
AutoDispatch	125	Covered	T1,T9,T10
AutoFirstAckWait	119	Covered	T1,T9,T10
AutoLoadIns	69	Covered	T1,T9,T10
AutoSendGenCmd	150	Covered	T1,T9,T10
AutoSendReseedCmd	162	Covered	T1,T9,T10
BootDone	98	Covered	T2,T18,T19
BootGenAckWait	90	Covered	T2,T18,T19
BootInsAckWait	80	Covered	T2,T18,T19
BootLoadGen	85	Covered	T2,T18,T19
BootLoadIns	65	Covered	T2,T18,T19
BootLoadUni	102	Covered	T19,T39,T26
BootPulse	94	Covered	T2,T18,T19
BootUniAckWait	107	Covered	T19,T39,T26
Error	188	Covered	T3,T5,T22
Idle	112	Covered	T1,T2,T3
RejectCsrngEntropy	188	Covered	T26,T27,T28
SWPortMode	74	Covered	T1,T3,T4

transitions	Line No.	Covered	Tests
AutoAckWait->AutoDispatch	131	Covered	T1,T9,T10
AutoAckWait->Error	188	Covered	T113,T114
AutoAckWait->Idle	211	Covered	T49,T69,T93
AutoAckWait->RejectCsrngEntropy	188	Covered	T115,T116,T117
AutoCaptGenCnt->AutoSendGenCmd	150	Covered	T1,T9,T10
AutoCaptGenCnt->Error	188	Covered	T6,T118
AutoCaptGenCnt->Idle	211	Covered	T49,T119,T120
AutoCaptGenCnt->RejectCsrngEntropy	188	Covered	T103,T121,T122
AutoCaptReseedCnt->AutoSendReseedCmd	162	Covered	T1,T9,T10
AutoCaptReseedCnt->Error	188	Covered	T123,T124,T125
AutoCaptReseedCnt->Idle	211	Covered	T69,T93,T78
AutoCaptReseedCnt->RejectCsrngEntropy	188	Covered	T74,T106,T105
AutoDispatch->AutoCaptGenCnt	143	Covered	T1,T9,T10
AutoDispatch->AutoCaptReseedCnt	141	Covered	T1,T9,T10
AutoDispatch->Error	188	Covered	T126,T127
AutoDispatch->Idle	138	Covered	T1,T9,T10
AutoDispatch->RejectCsrngEntropy	188	Covered	T52,T128
AutoFirstAckWait->AutoDispatch	125	Covered	T1,T9,T10
AutoFirstAckWait->Error	188	Covered	T129,T130,T131
AutoFirstAckWait->Idle	211	Covered	T82,T99,T132
AutoFirstAckWait->RejectCsrngEntropy	188	Covered	T109
AutoLoadIns->AutoFirstAckWait	119	Covered	T1,T9,T10
AutoLoadIns->Error	188	Covered	T8,T58,T133
AutoLoadIns->Idle	211	Covered	T27,T6,T28
AutoLoadIns->RejectCsrngEntropy	188	Covered	T134
AutoSendGenCmd->AutoAckWait	156	Covered	T1,T9,T10
AutoSendGenCmd->Error	188	Covered	T135,T136,T137
AutoSendGenCmd->Idle	211	Covered	T138,T139,T140
AutoSendGenCmd->RejectCsrngEntropy	188	Covered	T27,T50,T51
AutoSendReseedCmd->AutoAckWait	168	Covered	T1,T9,T10
AutoSendReseedCmd->Error	188	Covered	T7,T141,T142
AutoSendReseedCmd->Idle	211	Covered	T143,T144,T145
AutoSendReseedCmd->RejectCsrngEntropy	188	Not Covered
BootDone->BootLoadUni	102	Covered	T19,T39,T26
BootDone->Error	188	Covered	T15,T59,T146
BootDone->Idle	211	Covered	T147,T148,T149
BootDone->RejectCsrngEntropy	188	Covered	T150,T151,T152
BootGenAckWait->BootPulse	94	Covered	T2,T18,T19
BootGenAckWait->Error	188	Covered	T153,T154,T155
BootGenAckWait->Idle	211	Covered	T5,T38,T45
BootGenAckWait->RejectCsrngEntropy	188	Covered	T101,T156,T157
BootInsAckWait->BootLoadGen	85	Covered	T2,T18,T19
BootInsAckWait->Error	188	Covered	T158,T62,T159
BootInsAckWait->Idle	211	Covered	T76,T59,T160
BootInsAckWait->RejectCsrngEntropy	188	Covered	T107,T110,T161
BootLoadGen->BootGenAckWait	90	Covered	T2,T18,T19
BootLoadGen->Error	188	Covered	T162
BootLoadGen->Idle	211	Covered	T163,T164,T165
BootLoadGen->RejectCsrngEntropy	188	Covered	T166,T102,T167
BootLoadIns->BootInsAckWait	80	Covered	T2,T18,T19
BootLoadIns->Error	188	Covered	T168,T169,T170
BootLoadIns->Idle	211	Covered	T18,T70,T171
BootLoadIns->RejectCsrngEntropy	188	Covered	T108,T172,T173
BootLoadUni->BootUniAckWait	107	Covered	T19,T39,T26
BootLoadUni->Error	188	Covered	T165,T174,T175
BootLoadUni->Idle	211	Not Covered
BootLoadUni->RejectCsrngEntropy	188	Covered	T26,T176,T177
BootPulse->BootDone	98	Covered	T2,T18,T19
BootPulse->Error	188	Not Covered
BootPulse->Idle	211	Covered	T2,T21,T42
BootPulse->RejectCsrngEntropy	188	Covered	T28
BootUniAckWait->Error	188	Covered	T178,T179
BootUniAckWait->Idle	112	Covered	T19,T39,T26
BootUniAckWait->RejectCsrngEntropy	188	Covered	T180
Idle->AutoLoadIns	69	Covered	T1,T9,T10
Idle->BootLoadIns	65	Covered	T2,T18,T19
Idle->Error	188	Covered	T3,T14,T16
Idle->RejectCsrngEntropy	188	Covered	T26,T28,T74
Idle->SWPortMode	74	Covered	T1,T3,T4
RejectCsrngEntropy->Error	188	Covered	T112,T181,T182
RejectCsrngEntropy->Idle	211	Covered	T26,T27,T28
SWPortMode->Error	188	Covered	T3,T22,T14
SWPortMode->Idle	211	Covered	T3,T4,T54
SWPortMode->RejectCsrngEntropy	188	Covered	T27,T50,T51

---

Branch Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
Branches		42	41	97.62
IF	42	2	2	100.00
CASE	62	35	35	100.00
IF	186	5	4	80.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	42	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	62	case (state_q)
-2-:	64	if ((boot_req_mode_i && edn_enable_i))
-3-:	66	if ((auto_req_mode_i && edn_enable_i))
-4-:	70	if (edn_enable_i)
-5-:	84	if (csrng_cmd_ack_i)
-6-:	93	if (csrng_cmd_ack_i)
-7-:	101	if ((!boot_req_mode_i))
-8-:	110	if (csrng_cmd_ack_i)
-9-:	118	if (sw_cmd_req_load_i)
-10-:	124	if (csrng_cmd_ack_i)
-11-:	130	if (csrng_cmd_ack_i)
-12-:	136	if ((!auto_req_mode_i))
-13-:	140	if (max_reqs_cnt_zero_i)
-14-:	155	if (cmd_sent_i)
-15-:	167	if (cmd_sent_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	Status	Tests
Idle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T18,T19
Idle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T9,T10
Idle	0	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
Idle	0	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
BootLoadIns	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T18,T19
BootInsAckWait	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T2,T18,T19
BootInsAckWait	-	-	-	0	-	-	-	-	-	-	-	-	-	-	Covered	T2,T18,T19
BootLoadGen	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T18,T19
BootGenAckWait	-	-	-	-	1	-	-	-	-	-	-	-	-	-	Covered	T2,T18,T19
BootGenAckWait	-	-	-	-	0	-	-	-	-	-	-	-	-	-	Covered	T2,T18,T19
BootPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T18,T19
BootDone	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T19,T39,T26
BootDone	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T2,T18,T5
BootLoadUni	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T19,T39,T26
BootUniAckWait	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T19,T39,T41
BootUniAckWait	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T19,T39,T26
AutoLoadIns	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T1,T9,T10
AutoLoadIns	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T1,T9,T10
AutoFirstAckWait	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T1,T9,T10
AutoFirstAckWait	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T9,T10
AutoAckWait	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T1,T9,T10
AutoAckWait	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T1,T9,T10
AutoDispatch	-	-	-	-	-	-	-	-	-	-	1	-	-	-	Covered	T1,T9,T10
AutoDispatch	-	-	-	-	-	-	-	-	-	-	0	1	-	-	Covered	T1,T9,T10
AutoDispatch	-	-	-	-	-	-	-	-	-	-	0	0	-	-	Covered	T1,T9,T10
AutoCaptGenCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T9,T10
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T1,T9,T10
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T1,T9,T10
AutoCaptReseedCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T9,T10
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T9,T10
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T9,T10
SWPortMode	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
RejectCsrngEntropy	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T26,T27,T28
Error	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T5,T22
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T5,T71

	LineNo.	Expression
-1-:	186	if ((local_escalate_i || csrng_ack_err_i))
-2-:	188	(local_escalate_i) ? 
-3-:	188	((state_q == Error)) ? 
-4-:	201	if (((!edn_enable_i) && (state_q inside {BootLoadIns, BootInsAckWait, BootLoadGen, BootGenAckWait, BootLoadUni, BootUniAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode, RejectCsrngEntropy})))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	1	-	-	Covered	T3,T5,T22
1	0	1	-	Not Covered
1	0	0	-	Covered	T26,T27,T28
0	-	-	1	Covered	T2,T4,T18
0	-	-	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_main_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ErrorStStable_A	187404959	145805	0	0
FpvSecCmErrorStEscalate_A	187404959	146969	0	0
u_state_regs_A	187366544	187187511	0	0

ErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187404959	145805	0	0
T3	46351	17806	0	0
T4	1307	0	0	0
T5	1418	738	0	0
T6	0	1080	0	0
T7	0	1099	0	0
T9	5598	0	0	0
T10	2689	0	0	0
T14	0	8811	0	0
T15	0	1171	0	0
T17	3002	0	0	0
T18	798	0	0	0
T19	1841	0	0	0
T20	4534	0	0	0
T22	0	466	0	0
T57	0	1041	0	0
T63	2294	0	0	0
T71	0	378	0	0
T72	0	310	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187404959	146969	0	0
T3	46351	18066	0	0
T4	1307	0	0	0
T5	1418	739	0	0
T6	0	1081	0	0
T7	0	1100	0	0
T9	5598	0	0	0
T10	2689	0	0	0
T14	0	8941	0	0
T15	0	1172	0	0
T17	3002	0	0	0
T18	798	0	0	0
T19	1841	0	0	0
T20	4534	0	0	0
T22	0	467	0	0
T57	0	1042	0	0
T63	2294	0	0	0
T71	0	379	0	0
T72	0	311	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187366544	187187511	0	0
T1	3553	3492	0	0
T2	1533	1461	0	0
T3	46351	25226	0	0
T4	1247	1096	0	0
T9	5598	5540	0	0
T10	2689	2600	0	0
T17	3002	2914	0	0
T18	798	736	0	0
T19	1841	1787	0	0
T20	4534	4452	0	0