Unified Coverage Report :: Module :: edn_ack_sm

Module : edn_ack_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.12	100.00	90.40			98.10	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.12	100.00	90.40			98.10	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.12	100.00	90.40			98.10	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.12	100.00	90.40			98.10	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.12	100.00	90.40			98.10	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.12	100.00	90.40			98.10	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.12	100.00	90.40			98.10	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_ack_sm

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T18

---

FSM Coverage for Module : edn_ack_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T1,T4,T9
DataWait	75	Covered	T1,T4,T9
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T3,T5,T22
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T2,T21,T183
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T1,T4,T9
DataWait->AckPls	80	Covered	T1,T4,T9
DataWait->Disabled	107	Covered	T38,T49,T76
DataWait->Error	99	Covered	T5,T15,T112
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T3,T14,T16
EndPointClear->Disabled	107	Covered	T18,T70,T56
EndPointClear->Error	99	Covered	T3,T14,T184
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T1,T4,T9
Idle->Disabled	107	Covered	T2,T3,T4
Idle->Error	99	Covered	T5,T22,T71

---

Branch Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T1,T4,T9
Idle	-	1	0	-	Covered	T1,T4,T9
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T1,T4,T9
DataWait	-	-	-	0	Covered	T1,T9,T10
AckPls	-	-	-	-	Covered	T1,T4,T9
Error	-	-	-	-	Covered	T3,T5,T22
default	-	-	-	-	Covered	T3,T22,T14

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T5,T22
0	1	Covered	T2,T4,T18
0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_ack_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	1311834713	1032835	0	0
FpvSecCmErrorStEscalate_A	1311834713	1040983	0	0
u_state_regs_A	1311796298	1310543067	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1311834713	1032835	0	0
T3	324457	124642	0	0
T4	9149	0	0	0
T5	9926	5516	0	0
T6	0	7510	0	0
T7	0	7643	0	0
T9	39186	0	0	0
T10	18823	0	0	0
T14	0	61677	0	0
T15	0	8197	0	0
T17	21014	0	0	0
T18	5586	0	0	0
T19	12887	0	0	0
T20	31738	0	0	0
T22	0	3212	0	0
T57	0	7287	0	0
T63	16058	0	0	0
T71	0	2996	0	0
T72	0	2520	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1311834713	1040983	0	0
T3	324457	126462	0	0
T4	9149	0	0	0
T5	9926	5523	0	0
T6	0	7517	0	0
T7	0	7650	0	0
T9	39186	0	0	0
T10	18823	0	0	0
T14	0	62587	0	0
T15	0	8204	0	0
T17	21014	0	0	0
T18	5586	0	0	0
T19	12887	0	0	0
T20	31738	0	0	0
T22	0	3219	0	0
T57	0	7294	0	0
T63	16058	0	0	0
T71	0	3003	0	0
T72	0	2527	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1311796298	1310543067	0	0
T1	24871	24444	0	0
T2	10731	10227	0	0
T3	324457	176582	0	0
T4	9089	8032	0	0
T9	39186	38780	0	0
T10	18823	18200	0	0
T17	21014	20398	0	0
T18	5586	5152	0	0
T19	12887	12509	0	0
T20	31738	31164	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T18

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T1,T9,T19
DataWait	75	Covered	T1,T9,T19
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T3,T5,T22
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T1,T9,T19
DataWait->AckPls	80	Covered	T1,T9,T19
DataWait->Disabled	107	Covered	T163,T185
DataWait->Error	99	Covered	T5,T112,T62
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T3,T14,T16
EndPointClear->Disabled	107	Covered	T18,T70,T56
EndPointClear->Error	99	Covered	T3,T14,T184
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T1,T9,T19
Idle->Disabled	107	Covered	T2,T3,T4
Idle->Error	99	Covered	T22,T71,T14

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T1,T9,T19
Idle	-	1	0	-	Covered	T1,T9,T19
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T1,T9,T19
DataWait	-	-	-	0	Covered	T1,T9,T19
AckPls	-	-	-	-	Covered	T1,T9,T19
Error	-	-	-	-	Covered	T3,T5,T22
default	-	-	-	-	Covered	T3,T14,T16

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T5,T22
0	1	Covered	T2,T4,T18
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	187404959	147805	0	0
FpvSecCmErrorStEscalate_A	187404959	148969	0	0
u_state_regs_A	187404959	187225926	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187404959	147805	0	0
T3	46351	17806	0	0
T4	1307	0	0	0
T5	1418	788	0	0
T6	0	1080	0	0
T7	0	1099	0	0
T9	5598	0	0	0
T10	2689	0	0	0
T14	0	8811	0	0
T15	0	1171	0	0
T17	3002	0	0	0
T18	798	0	0	0
T19	1841	0	0	0
T20	4534	0	0	0
T22	0	466	0	0
T57	0	1041	0	0
T63	2294	0	0	0
T71	0	428	0	0
T72	0	360	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187404959	148969	0	0
T3	46351	18066	0	0
T4	1307	0	0	0
T5	1418	789	0	0
T6	0	1081	0	0
T7	0	1100	0	0
T9	5598	0	0	0
T10	2689	0	0	0
T14	0	8941	0	0
T15	0	1172	0	0
T17	3002	0	0	0
T18	798	0	0	0
T19	1841	0	0	0
T20	4534	0	0	0
T22	0	467	0	0
T57	0	1042	0	0
T63	2294	0	0	0
T71	0	429	0	0
T72	0	361	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187404959	187225926	0	0
T1	3553	3492	0	0
T2	1533	1461	0	0
T3	46351	25226	0	0
T4	1307	1156	0	0
T9	5598	5540	0	0
T10	2689	2600	0	0
T17	3002	2914	0	0
T18	798	736	0	0
T19	1841	1787	0	0
T20	4534	4452	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T18

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T1,T18,T38
DataWait	75	Covered	T1,T18,T38
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T3,T5,T22
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T1,T18,T38
DataWait->AckPls	80	Covered	T1,T18,T38
DataWait->Disabled	107	Covered	T38,T76,T186
DataWait->Error	99	Covered	T59,T61,T136
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T3,T14,T16
EndPointClear->Disabled	107	Covered	T18,T70,T56
EndPointClear->Error	99	Covered	T3,T14,T184
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T1,T18,T38
Idle->Disabled	107	Covered	T2,T3,T4
Idle->Error	99	Covered	T5,T22,T71

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T1,T18,T38
Idle	-	1	0	-	Covered	T1,T18,T38
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T1,T18,T38
DataWait	-	-	-	0	Covered	T1,T18,T38
AckPls	-	-	-	-	Covered	T1,T18,T38
Error	-	-	-	-	Covered	T3,T5,T22
default	-	-	-	-	Covered	T3,T14,T16

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T5,T22
0	1	Covered	T2,T4,T18
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	187404959	147805	0	0
FpvSecCmErrorStEscalate_A	187404959	148969	0	0
u_state_regs_A	187404959	187225926	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187404959	147805	0	0
T3	46351	17806	0	0
T4	1307	0	0	0
T5	1418	788	0	0
T6	0	1080	0	0
T7	0	1099	0	0
T9	5598	0	0	0
T10	2689	0	0	0
T14	0	8811	0	0
T15	0	1171	0	0
T17	3002	0	0	0
T18	798	0	0	0
T19	1841	0	0	0
T20	4534	0	0	0
T22	0	466	0	0
T57	0	1041	0	0
T63	2294	0	0	0
T71	0	428	0	0
T72	0	360	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187404959	148969	0	0
T3	46351	18066	0	0
T4	1307	0	0	0
T5	1418	789	0	0
T6	0	1081	0	0
T7	0	1100	0	0
T9	5598	0	0	0
T10	2689	0	0	0
T14	0	8941	0	0
T15	0	1172	0	0
T17	3002	0	0	0
T18	798	0	0	0
T19	1841	0	0	0
T20	4534	0	0	0
T22	0	467	0	0
T57	0	1042	0	0
T63	2294	0	0	0
T71	0	429	0	0
T72	0	361	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187404959	187225926	0	0
T1	3553	3492	0	0
T2	1533	1461	0	0
T3	46351	25226	0	0
T4	1307	1156	0	0
T9	5598	5540	0	0
T10	2689	2600	0	0
T17	3002	2914	0	0
T18	798	736	0	0
T19	1841	1787	0	0
T20	4534	4452	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T18

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T1,T39,T40
DataWait	75	Covered	T1,T39,T40
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T3,T5,T22
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T1,T39,T40
DataWait->AckPls	80	Covered	T1,T39,T40
DataWait->Disabled	107	Covered	T187,T188
DataWait->Error	99	Covered	T6,T189
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T3,T14,T16
EndPointClear->Disabled	107	Covered	T18,T70,T56
EndPointClear->Error	99	Covered	T3,T14,T184
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T1,T39,T40
Idle->Disabled	107	Covered	T2,T3,T4
Idle->Error	99	Covered	T5,T22,T71

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T1,T39,T40
Idle	-	1	0	-	Covered	T1,T39,T40
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T1,T39,T40
DataWait	-	-	-	0	Covered	T1,T39,T40
AckPls	-	-	-	-	Covered	T1,T39,T40
Error	-	-	-	-	Covered	T3,T5,T22
default	-	-	-	-	Covered	T3,T14,T16

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T5,T22
0	1	Covered	T2,T4,T18
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	187404959	147805	0	0
FpvSecCmErrorStEscalate_A	187404959	148969	0	0
u_state_regs_A	187404959	187225926	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187404959	147805	0	0
T3	46351	17806	0	0
T4	1307	0	0	0
T5	1418	788	0	0
T6	0	1080	0	0
T7	0	1099	0	0
T9	5598	0	0	0
T10	2689	0	0	0
T14	0	8811	0	0
T15	0	1171	0	0
T17	3002	0	0	0
T18	798	0	0	0
T19	1841	0	0	0
T20	4534	0	0	0
T22	0	466	0	0
T57	0	1041	0	0
T63	2294	0	0	0
T71	0	428	0	0
T72	0	360	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187404959	148969	0	0
T3	46351	18066	0	0
T4	1307	0	0	0
T5	1418	789	0	0
T6	0	1081	0	0
T7	0	1100	0	0
T9	5598	0	0	0
T10	2689	0	0	0
T14	0	8941	0	0
T15	0	1172	0	0
T17	3002	0	0	0
T18	798	0	0	0
T19	1841	0	0	0
T20	4534	0	0	0
T22	0	467	0	0
T57	0	1042	0	0
T63	2294	0	0	0
T71	0	429	0	0
T72	0	361	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187404959	187225926	0	0
T1	3553	3492	0	0
T2	1533	1461	0	0
T3	46351	25226	0	0
T4	1307	1156	0	0
T9	5598	5540	0	0
T10	2689	2600	0	0
T17	3002	2914	0	0
T18	798	736	0	0
T19	1841	1787	0	0
T20	4534	4452	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T18

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T39,T40,T41
DataWait	75	Covered	T39,T40,T41
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T3,T5,T22
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T39,T40,T41
DataWait->AckPls	80	Covered	T39,T40,T41
DataWait->Disabled	107	Covered	T49,T140,T190
DataWait->Error	99	Covered	T72,T57,T58
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T3,T14,T16
EndPointClear->Disabled	107	Covered	T18,T70,T56
EndPointClear->Error	99	Covered	T3,T14,T184
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T39,T40,T41
Idle->Disabled	107	Covered	T2,T3,T4
Idle->Error	99	Covered	T5,T22,T71

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T39,T40,T41
Idle	-	1	0	-	Covered	T39,T40,T41
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T39,T40,T41
DataWait	-	-	-	0	Covered	T39,T40,T41
AckPls	-	-	-	-	Covered	T39,T40,T41
Error	-	-	-	-	Covered	T3,T5,T22
default	-	-	-	-	Covered	T3,T14,T16

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T5,T22
0	1	Covered	T2,T4,T18
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	187404959	147805	0	0
FpvSecCmErrorStEscalate_A	187404959	148969	0	0
u_state_regs_A	187404959	187225926	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187404959	147805	0	0
T3	46351	17806	0	0
T4	1307	0	0	0
T5	1418	788	0	0
T6	0	1080	0	0
T7	0	1099	0	0
T9	5598	0	0	0
T10	2689	0	0	0
T14	0	8811	0	0
T15	0	1171	0	0
T17	3002	0	0	0
T18	798	0	0	0
T19	1841	0	0	0
T20	4534	0	0	0
T22	0	466	0	0
T57	0	1041	0	0
T63	2294	0	0	0
T71	0	428	0	0
T72	0	360	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187404959	148969	0	0
T3	46351	18066	0	0
T4	1307	0	0	0
T5	1418	789	0	0
T6	0	1081	0	0
T7	0	1100	0	0
T9	5598	0	0	0
T10	2689	0	0	0
T14	0	8941	0	0
T15	0	1172	0	0
T17	3002	0	0	0
T18	798	0	0	0
T19	1841	0	0	0
T20	4534	0	0	0
T22	0	467	0	0
T57	0	1042	0	0
T63	2294	0	0	0
T71	0	429	0	0
T72	0	361	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187404959	187225926	0	0
T1	3553	3492	0	0
T2	1533	1461	0	0
T3	46351	25226	0	0
T4	1307	1156	0	0
T9	5598	5540	0	0
T10	2689	2600	0	0
T17	3002	2914	0	0
T18	798	736	0	0
T19	1841	1787	0	0
T20	4534	4452	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T18

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T1,T4,T9
DataWait	75	Covered	T1,T4,T9
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T3,T5,T22
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T183
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T1,T4,T9
DataWait->AckPls	80	Covered	T1,T4,T9
DataWait->Disabled	107	Covered	T138,T164,T139
DataWait->Error	99	Covered	T15,T191,T192
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T3,T14,T16
EndPointClear->Disabled	107	Covered	T18,T70,T56
EndPointClear->Error	99	Covered	T3,T184,T60
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T1,T4,T9
Idle->Disabled	107	Covered	T2,T3,T4
Idle->Error	99	Covered	T5,T71,T14

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T1,T4,T9
Idle	-	1	0	-	Covered	T1,T4,T9
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T1,T4,T9
DataWait	-	-	-	0	Covered	T1,T9,T10
AckPls	-	-	-	-	Covered	T1,T4,T9
Error	-	-	-	-	Covered	T3,T5,T22
default	-	-	-	-	Covered	T3,T22,T14

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T5,T22
0	1	Covered	T2,T4,T18
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	187404959	146005	0	0
FpvSecCmErrorStEscalate_A	187404959	147169	0	0
u_state_regs_A	187366544	187187511	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187404959	146005	0	0
T3	46351	17806	0	0
T4	1307	0	0	0
T5	1418	788	0	0
T6	0	1030	0	0
T7	0	1049	0	0
T9	5598	0	0	0
T10	2689	0	0	0
T14	0	8811	0	0
T15	0	1171	0	0
T17	3002	0	0	0
T18	798	0	0	0
T19	1841	0	0	0
T20	4534	0	0	0
T22	0	416	0	0
T57	0	1041	0	0
T63	2294	0	0	0
T71	0	428	0	0
T72	0	360	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187404959	147169	0	0
T3	46351	18066	0	0
T4	1307	0	0	0
T5	1418	789	0	0
T6	0	1031	0	0
T7	0	1050	0	0
T9	5598	0	0	0
T10	2689	0	0	0
T14	0	8941	0	0
T15	0	1172	0	0
T17	3002	0	0	0
T18	798	0	0	0
T19	1841	0	0	0
T20	4534	0	0	0
T22	0	417	0	0
T57	0	1042	0	0
T63	2294	0	0	0
T71	0	429	0	0
T72	0	361	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187366544	187187511	0	0
T1	3553	3492	0	0
T2	1533	1461	0	0
T3	46351	25226	0	0
T4	1247	1096	0	0
T9	5598	5540	0	0
T10	2689	2600	0	0
T17	3002	2914	0	0
T18	798	736	0	0
T19	1841	1787	0	0
T20	4534	4452	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T18

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T1,T19,T21
DataWait	75	Covered	T1,T19,T21
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T3,T5,T22
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T21
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T1,T19,T21
DataWait->AckPls	80	Covered	T1,T19,T21
DataWait->Disabled	107	Covered	T193
DataWait->Error	99	Covered	T194,T130,T195
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T3,T14,T16
EndPointClear->Disabled	107	Covered	T18,T70,T56
EndPointClear->Error	99	Covered	T3,T14,T184
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T1,T19,T21
Idle->Disabled	107	Covered	T2,T3,T4
Idle->Error	99	Covered	T5,T22,T71

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T1,T19,T21
Idle	-	1	0	-	Covered	T1,T19,T21
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T1,T19,T21
DataWait	-	-	-	0	Covered	T1,T19,T21
AckPls	-	-	-	-	Covered	T1,T19,T21
Error	-	-	-	-	Covered	T3,T5,T22
default	-	-	-	-	Covered	T3,T14,T16

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T5,T22
0	1	Covered	T2,T4,T18
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	187404959	147805	0	0
FpvSecCmErrorStEscalate_A	187404959	148969	0	0
u_state_regs_A	187404959	187225926	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187404959	147805	0	0
T3	46351	17806	0	0
T4	1307	0	0	0
T5	1418	788	0	0
T6	0	1080	0	0
T7	0	1099	0	0
T9	5598	0	0	0
T10	2689	0	0	0
T14	0	8811	0	0
T15	0	1171	0	0
T17	3002	0	0	0
T18	798	0	0	0
T19	1841	0	0	0
T20	4534	0	0	0
T22	0	466	0	0
T57	0	1041	0	0
T63	2294	0	0	0
T71	0	428	0	0
T72	0	360	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187404959	148969	0	0
T3	46351	18066	0	0
T4	1307	0	0	0
T5	1418	789	0	0
T6	0	1081	0	0
T7	0	1100	0	0
T9	5598	0	0	0
T10	2689	0	0	0
T14	0	8941	0	0
T15	0	1172	0	0
T17	3002	0	0	0
T18	798	0	0	0
T19	1841	0	0	0
T20	4534	0	0	0
T22	0	467	0	0
T57	0	1042	0	0
T63	2294	0	0	0
T71	0	429	0	0
T72	0	361	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187404959	187225926	0	0
T1	3553	3492	0	0
T2	1533	1461	0	0
T3	46351	25226	0	0
T4	1307	1156	0	0
T9	5598	5540	0	0
T10	2689	2600	0	0
T17	3002	2914	0	0
T18	798	736	0	0
T19	1841	1787	0	0
T20	4534	4452	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T18

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T2,T39,T42
DataWait	75	Covered	T2,T39,T42
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T3,T5,T22
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T2
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T2,T39,T42
DataWait->AckPls	80	Covered	T2,T39,T42
DataWait->Disabled	107	Covered	T196
DataWait->Error	99	Covered	T181,T118,T126
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T3,T14,T16
EndPointClear->Disabled	107	Covered	T18,T70,T56
EndPointClear->Error	99	Covered	T3,T14,T184
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T2,T39,T42
Idle->Disabled	107	Covered	T3,T4,T5
Idle->Error	99	Covered	T5,T22,T71

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T2,T39,T42
Idle	-	1	0	-	Covered	T2,T39,T42
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T2,T39,T42
DataWait	-	-	-	0	Covered	T2,T39,T42
AckPls	-	-	-	-	Covered	T2,T39,T42
Error	-	-	-	-	Covered	T3,T5,T22
default	-	-	-	-	Covered	T3,T14,T16

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T5,T22
0	1	Covered	T2,T4,T18
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	187404959	147805	0	0
FpvSecCmErrorStEscalate_A	187404959	148969	0	0
u_state_regs_A	187404959	187225926	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187404959	147805	0	0
T3	46351	17806	0	0
T4	1307	0	0	0
T5	1418	788	0	0
T6	0	1080	0	0
T7	0	1099	0	0
T9	5598	0	0	0
T10	2689	0	0	0
T14	0	8811	0	0
T15	0	1171	0	0
T17	3002	0	0	0
T18	798	0	0	0
T19	1841	0	0	0
T20	4534	0	0	0
T22	0	466	0	0
T57	0	1041	0	0
T63	2294	0	0	0
T71	0	428	0	0
T72	0	360	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187404959	148969	0	0
T3	46351	18066	0	0
T4	1307	0	0	0
T5	1418	789	0	0
T6	0	1081	0	0
T7	0	1100	0	0
T9	5598	0	0	0
T10	2689	0	0	0
T14	0	8941	0	0
T15	0	1172	0	0
T17	3002	0	0	0
T18	798	0	0	0
T19	1841	0	0	0
T20	4534	0	0	0
T22	0	467	0	0
T57	0	1042	0	0
T63	2294	0	0	0
T71	0	429	0	0
T72	0	361	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187404959	187225926	0	0
T1	3553	3492	0	0
T2	1533	1461	0	0
T3	46351	25226	0	0
T4	1307	1156	0	0
T9	5598	5540	0	0
T10	2689	2600	0	0
T17	3002	2914	0	0
T18	798	736	0	0
T19	1841	1787	0	0
T20	4534	4452	0	0