Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_prim_fifo_sync_rescmd	94.64	100.00	78.57			100.00	100.00
tb.dut.u_edn_core.u_prim_fifo_sync_gencmd	94.64	100.00	78.57			100.00	100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.38	100.00	91.89	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.12	100.00	90.40			98.10	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.38	100.00	91.89	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.12	100.00	90.40			98.10	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Module : prim_fifo_sync

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T9,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T9,T10

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T30,T31,T84
1	1	0	Not Covered
1	1	1	Covered	T1,T9,T10

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T32,T33,T34
1	0	1	Covered	T1,T9,T10
1	1	0	Not Covered
1	1	1	Covered	T1,T9,T10

---

Branch Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T9,T10
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	374045950	1453020	0	0
DepthKnown_A	374809918	374451852	0	0
RvalidKnown_A	374809918	374451852	0	0
WreadyKnown_A	374809918	374451852	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	374408642	1550357	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	374045950	1453020	0	0
T1	7106	3109	0	0
T2	3066	0	0	0
T3	2128	0	0	0
T4	824	0	0	0
T9	11196	5517	0	0
T10	5378	2639	0	0
T11	0	737	0	0
T12	0	2342	0	0
T17	6004	663	0	0
T18	1596	0	0	0
T19	3682	0	0	0
T20	9068	6766	0	0
T27	0	924	0	0
T73	0	8080	0	0
T85	0	10123	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	374809918	374451852	0	0
T1	7106	6984	0	0
T2	3066	2922	0	0
T3	92702	50452	0	0
T4	2614	2312	0	0
T9	11196	11080	0	0
T10	5378	5200	0	0
T17	6004	5828	0	0
T18	1596	1472	0	0
T19	3682	3574	0	0
T20	9068	8904	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	374809918	374451852	0	0
T1	7106	6984	0	0
T2	3066	2922	0	0
T3	92702	50452	0	0
T4	2614	2312	0	0
T9	11196	11080	0	0
T10	5378	5200	0	0
T17	6004	5828	0	0
T18	1596	1472	0	0
T19	3682	3574	0	0
T20	9068	8904	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	374809918	374451852	0	0
T1	7106	6984	0	0
T2	3066	2922	0	0
T3	92702	50452	0	0
T4	2614	2312	0	0
T9	11196	11080	0	0
T10	5378	5200	0	0
T17	6004	5828	0	0
T18	1596	1472	0	0
T19	3682	3574	0	0
T20	9068	8904	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	374408642	1550357	0	0
T1	7106	3109	0	0
T2	3066	0	0	0
T3	2128	0	0	0
T4	2614	0	0	0
T5	0	363	0	0
T9	11196	5517	0	0
T10	5378	2639	0	0
T11	0	737	0	0
T17	6004	663	0	0
T18	1596	0	0	0
T19	3682	0	0	0
T20	9068	6766	0	0
T22	0	270	0	0
T27	0	924	0	0
T73	0	8080	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T85,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T9,T10

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T31,T84
1	1	0	Not Covered
1	1	1	Covered	T1,T9,T10

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T32,T33,T86
1	0	1	Covered	T1,T9,T10
1	1	0	Not Covered
1	1	1	Covered	T1,T9,T10

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T9,T10
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	187022975	721183	0	0
DepthKnown_A	187404959	187225926	0	0
RvalidKnown_A	187404959	187225926	0	0
WreadyKnown_A	187404959	187225926	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	187204321	769526	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187022975	721183	0	0
T1	3553	1554	0	0
T2	1533	0	0	0
T3	1064	0	0	0
T4	412	0	0	0
T9	5598	2735	0	0
T10	2689	1300	0	0
T11	0	364	0	0
T12	0	1124	0	0
T17	3002	327	0	0
T18	798	0	0	0
T19	1841	0	0	0
T20	4534	3379	0	0
T27	0	523	0	0
T73	0	3979	0	0
T85	0	5067	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187404959	187225926	0	0
T1	3553	3492	0	0
T2	1533	1461	0	0
T3	46351	25226	0	0
T4	1307	1156	0	0
T9	5598	5540	0	0
T10	2689	2600	0	0
T17	3002	2914	0	0
T18	798	736	0	0
T19	1841	1787	0	0
T20	4534	4452	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187404959	187225926	0	0
T1	3553	3492	0	0
T2	1533	1461	0	0
T3	46351	25226	0	0
T4	1307	1156	0	0
T9	5598	5540	0	0
T10	2689	2600	0	0
T17	3002	2914	0	0
T18	798	736	0	0
T19	1841	1787	0	0
T20	4534	4452	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187404959	187225926	0	0
T1	3553	3492	0	0
T2	1533	1461	0	0
T3	46351	25226	0	0
T4	1307	1156	0	0
T9	5598	5540	0	0
T10	2689	2600	0	0
T17	3002	2914	0	0
T18	798	736	0	0
T19	1841	1787	0	0
T20	4534	4452	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	187204321	769526	0	0
T1	3553	1554	0	0
T2	1533	0	0	0
T3	1064	0	0	0
T4	1307	0	0	0
T5	0	184	0	0
T9	5598	2735	0	0
T10	2689	1300	0	0
T11	0	364	0	0
T17	3002	327	0	0
T18	798	0	0	0
T19	1841	0	0	0
T20	4534	3379	0	0
T22	0	136	0	0
T27	0	523	0	0
T73	0	3979	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T9,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T9,T10

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T30
1	1	0	Not Covered
1	1	1	Covered	T1,T9,T10

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T34,T87,T88
1	0	1	Covered	T1,T9,T10
1	1	0	Not Covered
1	1	1	Covered	T1,T9,T10

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T9,T10
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	187022975	731837	0	0
DepthKnown_A	187404959	187225926	0	0
RvalidKnown_A	187404959	187225926	0	0
WreadyKnown_A	187404959	187225926	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	187204321	780831	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187022975	731837	0	0
T1	3553	1555	0	0
T2	1533	0	0	0
T3	1064	0	0	0
T4	412	0	0	0
T9	5598	2782	0	0
T10	2689	1339	0	0
T11	0	373	0	0
T12	0	1218	0	0
T17	3002	336	0	0
T18	798	0	0	0
T19	1841	0	0	0
T20	4534	3387	0	0
T27	0	401	0	0
T73	0	4101	0	0
T85	0	5056	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187404959	187225926	0	0
T1	3553	3492	0	0
T2	1533	1461	0	0
T3	46351	25226	0	0
T4	1307	1156	0	0
T9	5598	5540	0	0
T10	2689	2600	0	0
T17	3002	2914	0	0
T18	798	736	0	0
T19	1841	1787	0	0
T20	4534	4452	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187404959	187225926	0	0
T1	3553	3492	0	0
T2	1533	1461	0	0
T3	46351	25226	0	0
T4	1307	1156	0	0
T9	5598	5540	0	0
T10	2689	2600	0	0
T17	3002	2914	0	0
T18	798	736	0	0
T19	1841	1787	0	0
T20	4534	4452	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	187404959	187225926	0	0
T1	3553	3492	0	0
T2	1533	1461	0	0
T3	46351	25226	0	0
T4	1307	1156	0	0
T9	5598	5540	0	0
T10	2689	2600	0	0
T17	3002	2914	0	0
T18	798	736	0	0
T19	1841	1787	0	0
T20	4534	4452	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	187204321	780831	0	0
T1	3553	1555	0	0
T2	1533	0	0	0
T3	1064	0	0	0
T4	1307	0	0	0
T5	0	179	0	0
T9	5598	2782	0	0
T10	2689	1339	0	0
T11	0	373	0	0
T17	3002	336	0	0
T18	798	0	0	0
T19	1841	0	0	0
T20	4534	3387	0	0
T22	0	134	0	0
T27	0	401	0	0
T73	0	4101	0	0