Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44		83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	200716986	8548297	0	0
boot_gen_cmd_rd_A	200716986	48581	0	0
boot_ins_cmd_rd_A	200716986	57191	0	0
ctrl_rd_A	200716986	49896	0	0
err_code_test_rd_A	200716986	56804	0	0
intr_enable_rd_A	200716986	56573	0	0
max_num_reqs_between_reseeds_rd_A	200716986	51009	0	0
regwen_rd_A	200716986	58505	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200716986	8548297	0	0
T4	328025	186004	0	0
T5	1167	0	0	0
T8	3497	0	0	0
T13	23016	0	0	0
T19	10671	0	0	0
T20	194272	68757	0	0
T21	1183	0	0	0
T22	1315	0	0	0
T23	24414	0	0	0
T37	0	144669	0	0
T42	748	0	0	0
T62	0	90626	0	0
T89	0	143816	0	0
T91	0	127399	0	0
T197	0	217853	0	0
T198	0	119997	0	0
T199	0	226900	0	0
T200	0	142921	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200716986	48581	0	0
T5	1167	0	0	0
T8	3497	0	0	0
T13	23016	0	0	0
T18	2284	0	0	0
T20	194272	1214	0	0
T21	1183	0	0	0
T22	1315	0	0	0
T23	24414	0	0	0
T27	843	0	0	0
T37	0	4259	0	0
T42	748	0	0	0
T62	0	2588	0	0
T198	0	3233	0	0
T201	0	3199	0	0
T202	0	4539	0	0
T203	0	4224	0	0
T204	0	4038	0	0
T205	0	3182	0	0
T206	0	1864	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200716986	57191	0	0
T5	1167	0	0	0
T8	3497	0	0	0
T13	23016	0	0	0
T18	2284	0	0	0
T20	194272	1302	0	0
T21	1183	0	0	0
T22	1315	0	0	0
T23	24414	0	0	0
T27	843	0	0	0
T37	0	4654	0	0
T42	748	0	0	0
T62	0	2973	0	0
T198	0	4029	0	0
T201	0	3941	0	0
T202	0	5614	0	0
T203	0	5275	0	0
T204	0	4903	0	0
T205	0	3640	0	0
T206	0	2116	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200716986	49896	0	0
T5	1167	0	0	0
T8	3497	0	0	0
T13	23016	0	0	0
T18	2284	0	0	0
T20	194272	1308	0	0
T21	1183	0	0	0
T22	1315	0	0	0
T23	24414	0	0	0
T27	843	0	0	0
T37	0	4287	0	0
T42	748	0	0	0
T62	0	2696	0	0
T90	0	6	0	0
T198	0	3789	0	0
T201	0	3354	0	0
T202	0	4965	0	0
T203	0	4277	0	0
T207	0	7	0	0
T208	0	1	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200716986	56804	0	0
T5	1167	0	0	0
T8	3497	0	0	0
T13	23016	0	0	0
T18	2284	0	0	0
T20	194272	1381	0	0
T21	1183	0	0	0
T22	1315	0	0	0
T23	24414	0	0	0
T27	843	0	0	0
T37	0	4891	0	0
T42	748	0	0	0
T62	0	3167	0	0
T198	0	3914	0	0
T201	0	3850	0	0
T202	0	5598	0	0
T203	0	5296	0	0
T204	0	4735	0	0
T205	0	3456	0	0
T206	0	2088	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200716986	56573	0	0
T5	1167	0	0	0
T8	3497	0	0	0
T13	23016	0	0	0
T18	2284	0	0	0
T20	194272	1324	0	0
T21	1183	0	0	0
T22	1315	0	0	0
T23	24414	108	0	0
T27	843	0	0	0
T37	0	4825	0	0
T42	748	0	0	0
T62	0	2832	0	0
T81	0	32	0	0
T90	0	63	0	0
T198	0	3765	0	0
T201	0	3491	0	0
T202	0	4791	0	0
T209	0	94	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200716986	51009	0	0
T5	1167	0	0	0
T8	3497	0	0	0
T13	23016	0	0	0
T18	2284	0	0	0
T20	194272	1239	0	0
T21	1183	0	0	0
T22	1315	0	0	0
T23	24414	0	0	0
T27	843	0	0	0
T37	0	4345	0	0
T42	748	0	0	0
T62	0	2714	0	0
T198	0	3363	0	0
T201	0	3389	0	0
T202	0	4607	0	0
T203	0	4384	0	0
T204	0	4159	0	0
T205	0	3302	0	0
T206	0	1817	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200716986	58505	0	0
T5	1167	0	0	0
T8	3497	0	0	0
T13	23016	0	0	0
T18	2284	0	0	0
T20	194272	1446	0	0
T21	1183	0	0	0
T22	1315	0	0	0
T23	24414	0	0	0
T27	843	0	0	0
T37	0	5059	0	0
T42	748	0	0	0
T62	0	2996	0	0
T198	0	4081	0	0
T201	0	3861	0	0
T202	0	5418	0	0
T203	0	4803	0	0
T204	0	4596	0	0
T205	0	3701	0	0
T206	0	2108	0	0