Unified Coverage Report :: Module :: edn

Module : edn

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	94.44		83.33	100.00			100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.17	98.24	93.78	97.02	91.86	96.33	99.77

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
edn_csr_assert	100.00						100.00
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_edn_core	94.07	99.92	92.44	82.54	91.86	98.81	98.88
u_edn_cov_if	25.00	50.00	0.00
u_reg	96.95	95.02	97.57	100.00		92.16	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Cond Coverage for Module : edn

	Total	Covered	Percent
Conditions	6	5	83.33
Logical	6	5	83.33
Non-Logical	0	0
Event	0	0

 LINE       98
 EXPRESSION (alert[0] || intg_err_alert[0])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T18,T29,T30

 LINE       98
 EXPRESSION (alert[1] || intg_err_alert[1])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T13,T14
1	0	Covered	T2,T3,T21

---

Toggle Coverage for Module : edn

	Total	Covered	Percent
Totals	69	69	100.00
Total Bits	1172	1172	100.00
Total Bits 0->1	586	586	100.00
Total Bits 1->0	586	586	100.00

Ports	69	69	100.00
Port Bits	1172	1172	100.00
Port Bits 0->1	586	586	100.00
Port Bits 1->0	586	586	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T3,T4,T20	Yes	T3,T4,T20	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T4,T20,T37	Yes	T4,T20,T37	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i[0].edn_req	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
edn_i[1].edn_req	Yes	Yes	T1,T17,T38	Yes	T1,T17,T38	INPUT
edn_i[2].edn_req	Yes	Yes	T1,T8,T12	Yes	T1,T8,T12	INPUT
edn_i[3].edn_req	Yes	Yes	T39,T17,T40	Yes	T39,T17,T40	INPUT
edn_i[4].edn_req	Yes	Yes	T1,T41,T38	Yes	T1,T41,T38	INPUT
edn_i[5].edn_req	Yes	Yes	T42,T27,T17	Yes	T42,T27,T17	INPUT
edn_i[6].edn_req	Yes	Yes	T5,T43,T38	Yes	T5,T43,T38	INPUT
edn_o[0].edn_bus[31:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
edn_o[0].edn_fips	Yes	Yes	T1,T4,T19	Yes	T1,T4,T19	OUTPUT
edn_o[0].edn_ack	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
edn_o[1].edn_bus[31:0]	Yes	Yes	T1,T17,T38	Yes	T1,T17,T38	OUTPUT
edn_o[1].edn_fips	Yes	Yes	T1,T38,T44	Yes	T1,T38,T44	OUTPUT
edn_o[1].edn_ack	Yes	Yes	T1,T17,T38	Yes	T1,T17,T38	OUTPUT
edn_o[2].edn_bus[31:0]	Yes	Yes	T1,T8,T12	Yes	T1,T8,T12	OUTPUT
edn_o[2].edn_fips	Yes	Yes	T1,T8,T12	Yes	T1,T8,T12	OUTPUT
edn_o[2].edn_ack	Yes	Yes	T1,T8,T12	Yes	T1,T8,T12	OUTPUT
edn_o[3].edn_bus[31:0]	Yes	Yes	T39,T17,T40	Yes	T39,T17,T40	OUTPUT
edn_o[3].edn_fips	Yes	Yes	T17,T38,T45	Yes	T17,T40,T38	OUTPUT
edn_o[3].edn_ack	Yes	Yes	T39,T17,T40	Yes	T39,T17,T40	OUTPUT
edn_o[4].edn_bus[31:0]	Yes	Yes	T1,T38,T45	Yes	T1,T38,T45	OUTPUT
edn_o[4].edn_fips	Yes	Yes	T1,T38,T46	Yes	T1,T38,T45	OUTPUT
edn_o[4].edn_ack	Yes	Yes	T1,T38,T45	Yes	T1,T38,T45	OUTPUT
edn_o[5].edn_bus[31:0]	Yes	Yes	T27,T17,T38	Yes	T27,T17,T38	OUTPUT
edn_o[5].edn_fips	Yes	Yes	T45,T30,T47	Yes	T27,T17,T45	OUTPUT
edn_o[5].edn_ack	Yes	Yes	T42,T27,T17	Yes	T42,T27,T17	OUTPUT
edn_o[6].edn_bus[31:0]	Yes	Yes	T43,T38,T48	Yes	T43,T38,T48	OUTPUT
edn_o[6].edn_fips	Yes	Yes	T48,T49,T50	Yes	T38,T48,T49	OUTPUT
edn_o[6].edn_ack	Yes	Yes	T43,T38,T48	Yes	T43,T38,T48	OUTPUT
csrng_cmd_o.genbits_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_bus[31:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
csrng_cmd_o.csrng_req_valid	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
csrng_cmd_i.genbits_bus[127:0]	Yes	Yes	T1,T4,T20	Yes	T1,T4,T20	INPUT
csrng_cmd_i.genbits_fips	Yes	Yes	T1,T4,T20	Yes	T1,T4,T20	INPUT
csrng_cmd_i.genbits_valid	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
csrng_cmd_i.csrng_rsp_sts[2:0]	Yes	Yes	T30,T51,T52	Yes	T30,T51,T52	INPUT
csrng_cmd_i.csrng_rsp_ack	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
csrng_cmd_i.csrng_req_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T18,T53,T54	Yes	T18,T53,T54	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T2,T3,T21	Yes	T2,T3,T21	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T18,T53,T54	Yes	T18,T53,T54	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T2,T3,T21	Yes	T2,T3,T21	OUTPUT
intr_edn_cmd_req_done_o	Yes	Yes	T4,T20,T23	Yes	T4,T20,T23	OUTPUT
intr_edn_fatal_err_o	Yes	Yes	T2,T4,T19	Yes	T2,T4,T19	OUTPUT

*Tests covering at least one bit in the range

---

Assert Coverage for Module : edn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	47	47	100.00	47	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	47	47	100.00	47	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxKnownO_A	200199254	200031836	0	0
CsrngAppIfOut_A	200199254	200031836	0	0
FpvSecCmCntAlertCheck_A	200199254	112	0	0
FpvSecCmGenCmdFifoRptrCheck_A	200199254	70	0	0
FpvSecCmGenCmdFifoWptrCheck_A	200199254	70	0	0
FpvSecCmMainFsmCheck_A	200199254	70	0	0
FpvSecCmRegWeOnehotCheck_A	200199254	70	0	0
FpvSecCmResCmdFifoRptrCheck_A	200199254	70	0	0
FpvSecCmResCmdFifoWptrCheck_A	200199254	70	0	0
IntrEdnCmdReqDoneKnownO_A	200199254	200031836	0	0
TlAReadyKnownO_A	200199254	200031836	0	0
TlDValidKnownO_A	200199254	200031836	0	0
gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A	200199254	70	0	0
gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A	200199254	70	0	0
gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A	200199254	70	0	0
gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A	200199254	70	0	0
gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A	200199254	70	0	0
gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A	200199254	70	0	0
gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A	200199254	70	0	0
gen_edn_if_asserts[0].EdnDataStableDisable_A	200199254	548480	0	326
gen_edn_if_asserts[0].EdnDataStable_A	200199254	69963	0	349
gen_edn_if_asserts[0].EdnEndPointOut_A	200199254	200031836	0	0
gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A	200199254	146589	0	0
gen_edn_if_asserts[1].EdnDataStableDisable_A	200199254	548480	0	326
gen_edn_if_asserts[1].EdnDataStable_A	200199254	53702	0	119
gen_edn_if_asserts[1].EdnEndPointOut_A	200199254	200031836	0	0
gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A	200199254	146589	0	0
gen_edn_if_asserts[2].EdnDataStableDisable_A	200199254	548480	0	326
gen_edn_if_asserts[2].EdnDataStable_A	200199254	4969	0	119
gen_edn_if_asserts[2].EdnEndPointOut_A	200199254	200031836	0	0
gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A	200199254	146589	0	0
gen_edn_if_asserts[3].EdnDataStableDisable_A	200199254	548480	0	326
gen_edn_if_asserts[3].EdnDataStable_A	200199254	4226	0	116
gen_edn_if_asserts[3].EdnEndPointOut_A	200199254	200031836	0	0
gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A	200199254	146589	0	0
gen_edn_if_asserts[4].EdnDataStableDisable_A	200199254	548480	0	326
gen_edn_if_asserts[4].EdnDataStable_A	200199254	1574	0	96
gen_edn_if_asserts[4].EdnEndPointOut_A	200199254	200031836	0	0
gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A	200199254	146589	0	0
gen_edn_if_asserts[5].EdnDataStableDisable_A	200199254	548480	0	326
gen_edn_if_asserts[5].EdnDataStable_A	200199254	3725	0	86
gen_edn_if_asserts[5].EdnEndPointOut_A	200199254	200031836	0	0
gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A	200199254	146589	0	0
gen_edn_if_asserts[6].EdnDataStableDisable_A	200199254	548480	0	326
gen_edn_if_asserts[6].EdnDataStable_A	200199254	3885	0	84
gen_edn_if_asserts[6].EdnEndPointOut_A	200199254	200031836	0	0
gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A	200199254	146589	0	0

AlertTxKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200199254	200031836	0	0
T1	2402	2349	0	0
T2	2035	1841	0	0
T3	25258	14552	0	0
T4	328025	328010	0	0
T8	3497	3407	0	0
T19	10671	10340	0	0
T20	194272	194260	0	0
T21	1183	1044	0	0
T22	1315	1230	0	0
T23	24414	23655	0	0

CsrngAppIfOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200199254	200031836	0	0
T1	2402	2349	0	0
T2	2035	1841	0	0
T3	25258	14552	0	0
T4	328025	328010	0	0
T8	3497	3407	0	0
T19	10671	10340	0	0
T20	194272	194260	0	0
T21	1183	1044	0	0
T22	1315	1230	0	0
T23	24414	23655	0	0

FpvSecCmCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200199254	112	0	0
T3	25258	10	0	0
T4	328025	0	0	0
T5	1167	1	0	0
T6	0	1	0	0
T8	3497	0	0	0
T13	23016	10	0	0
T14	0	10	0	0
T19	10671	0	0	0
T20	194272	0	0	0
T21	1183	0	0	0
T22	1315	0	0	0
T23	24414	0	0	0
T42	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0

FpvSecCmGenCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200199254	70	0	0
T3	25258	10	0	0
T4	328025	0	0	0
T5	1167	0	0	0
T8	3497	0	0	0
T13	23016	10	0	0
T14	0	10	0	0
T19	10671	0	0	0
T20	194272	0	0	0
T21	1183	0	0	0
T22	1315	0	0	0
T23	24414	0	0	0
T59	0	20	0	0
T60	0	20	0	0

FpvSecCmGenCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200199254	70	0	0
T3	25258	10	0	0
T4	328025	0	0	0
T5	1167	0	0	0
T8	3497	0	0	0
T13	23016	10	0	0
T14	0	10	0	0
T19	10671	0	0	0
T20	194272	0	0	0
T21	1183	0	0	0
T22	1315	0	0	0
T23	24414	0	0	0
T59	0	20	0	0
T60	0	20	0	0

FpvSecCmMainFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200199254	70	0	0
T3	25258	10	0	0
T4	328025	0	0	0
T5	1167	0	0	0
T8	3497	0	0	0
T13	23016	10	0	0
T14	0	10	0	0
T19	10671	0	0	0
T20	194272	0	0	0
T21	1183	0	0	0
T22	1315	0	0	0
T23	24414	0	0	0
T59	0	20	0	0
T60	0	20	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200199254	70	0	0
T3	25258	10	0	0
T4	328025	0	0	0
T5	1167	0	0	0
T8	3497	0	0	0
T13	23016	10	0	0
T14	0	10	0	0
T19	10671	0	0	0
T20	194272	0	0	0
T21	1183	0	0	0
T22	1315	0	0	0
T23	24414	0	0	0
T59	0	20	0	0
T60	0	20	0	0

FpvSecCmResCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200199254	70	0	0
T3	25258	10	0	0
T4	328025	0	0	0
T5	1167	0	0	0
T8	3497	0	0	0
T13	23016	10	0	0
T14	0	10	0	0
T19	10671	0	0	0
T20	194272	0	0	0
T21	1183	0	0	0
T22	1315	0	0	0
T23	24414	0	0	0
T59	0	20	0	0
T60	0	20	0	0

FpvSecCmResCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200199254	70	0	0
T3	25258	10	0	0
T4	328025	0	0	0
T5	1167	0	0	0
T8	3497	0	0	0
T13	23016	10	0	0
T14	0	10	0	0
T19	10671	0	0	0
T20	194272	0	0	0
T21	1183	0	0	0
T22	1315	0	0	0
T23	24414	0	0	0
T59	0	20	0	0
T60	0	20	0	0

IntrEdnCmdReqDoneKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200199254	200031836	0	0
T1	2402	2349	0	0
T2	2035	1841	0	0
T3	25258	14552	0	0
T4	328025	328010	0	0
T8	3497	3407	0	0
T19	10671	10340	0	0
T20	194272	194260	0	0
T21	1183	1044	0	0
T22	1315	1230	0	0
T23	24414	23655	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200199254	200031836	0	0
T1	2402	2349	0	0
T2	2035	1841	0	0
T3	25258	14552	0	0
T4	328025	328010	0	0
T8	3497	3407	0	0
T19	10671	10340	0	0
T20	194272	194260	0	0
T21	1183	1044	0	0
T22	1315	1230	0	0
T23	24414	23655	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200199254	200031836	0	0
T1	2402	2349	0	0
T2	2035	1841	0	0
T3	25258	14552	0	0
T4	328025	328010	0	0
T8	3497	3407	0	0
T19	10671	10340	0	0
T20	194272	194260	0	0
T21	1183	1044	0	0
T22	1315	1230	0	0
T23	24414	23655	0	0

gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200199254	70	0	0
T3	25258	10	0	0
T4	328025	0	0	0
T5	1167	0	0	0
T8	3497	0	0	0
T13	23016	10	0	0
T14	0	10	0	0
T19	10671	0	0	0
T20	194272	0	0	0
T21	1183	0	0	0
T22	1315	0	0	0
T23	24414	0	0	0
T59	0	20	0	0
T60	0	20	0	0

gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200199254	70	0	0
T3	25258	10	0	0
T4	328025	0	0	0
T5	1167	0	0	0
T8	3497	0	0	0
T13	23016	10	0	0
T14	0	10	0	0
T19	10671	0	0	0
T20	194272	0	0	0
T21	1183	0	0	0
T22	1315	0	0	0
T23	24414	0	0	0
T59	0	20	0	0
T60	0	20	0	0

gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200199254	70	0	0
T3	25258	10	0	0
T4	328025	0	0	0
T5	1167	0	0	0
T8	3497	0	0	0
T13	23016	10	0	0
T14	0	10	0	0
T19	10671	0	0	0
T20	194272	0	0	0
T21	1183	0	0	0
T22	1315	0	0	0
T23	24414	0	0	0
T59	0	20	0	0
T60	0	20	0	0

gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200199254	70	0	0
T3	25258	10	0	0
T4	328025	0	0	0
T5	1167	0	0	0
T8	3497	0	0	0
T13	23016	10	0	0
T14	0	10	0	0
T19	10671	0	0	0
T20	194272	0	0	0
T21	1183	0	0	0
T22	1315	0	0	0
T23	24414	0	0	0
T59	0	20	0	0
T60	0	20	0	0

gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200199254	70	0	0
T3	25258	10	0	0
T4	328025	0	0	0
T5	1167	0	0	0
T8	3497	0	0	0
T13	23016	10	0	0
T14	0	10	0	0
T19	10671	0	0	0
T20	194272	0	0	0
T21	1183	0	0	0
T22	1315	0	0	0
T23	24414	0	0	0
T59	0	20	0	0
T60	0	20	0	0

gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200199254	70	0	0
T3	25258	10	0	0
T4	328025	0	0	0
T5	1167	0	0	0
T8	3497	0	0	0
T13	23016	10	0	0
T14	0	10	0	0
T19	10671	0	0	0
T20	194272	0	0	0
T21	1183	0	0	0
T22	1315	0	0	0
T23	24414	0	0	0
T59	0	20	0	0
T60	0	20	0	0

gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200199254	70	0	0
T3	25258	10	0	0
T4	328025	0	0	0
T5	1167	0	0	0
T8	3497	0	0	0
T13	23016	10	0	0
T14	0	10	0	0
T19	10671	0	0	0
T20	194272	0	0	0
T21	1183	0	0	0
T22	1315	0	0	0
T23	24414	0	0	0
T59	0	20	0	0
T60	0	20	0	0

gen_edn_if_asserts[0].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200199254	548480	0	326
T1	2402	68	0	0
T2	2035	1023	0	0
T3	25258	12183	0	2
T4	328025	1046	0	2
T8	3497	345	0	0
T13	0	0	0	2
T19	10671	558	0	0
T20	194272	2773	0	2
T21	1183	394	0	0
T22	1315	72	0	0
T23	24414	5248	0	0
T37	0	0	0	2
T40	0	0	0	2
T53	0	0	0	2
T54	0	0	0	2
T61	0	0	0	2
T62	0	0	0	2

gen_edn_if_asserts[0].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200199254	69963	0	349
T1	2402	37	0	1
T2	2035	1	0	0
T3	25258	0	0	0
T4	328025	94	0	0
T8	3497	0	0	0
T17	0	10	0	1
T18	0	4	0	1
T19	10671	3	0	0
T20	194272	87	0	0
T21	1183	1	0	0
T22	1315	3	0	1
T23	24414	23	0	1
T38	0	0	0	1
T48	0	0	0	1
T63	0	0	0	1
T64	0	0	0	1
T65	0	0	0	1

gen_edn_if_asserts[0].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200199254	200031836	0	0
T1	2402	2349	0	0
T2	2035	1841	0	0
T3	25258	14552	0	0
T4	328025	328010	0	0
T8	3497	3407	0	0
T19	10671	10340	0	0
T20	194272	194260	0	0
T21	1183	1044	0	0
T22	1315	1230	0	0
T23	24414	23655	0	0

gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200199254	146589	0	0
T2	2035	24	0	0
T3	25258	7384	0	0
T4	328025	0	0	0
T5	1167	604	0	0
T8	3497	0	0	0
T13	0	8768	0	0
T19	10671	0	0	0
T20	194272	0	0	0
T21	1183	491	0	0
T22	1315	0	0	0
T23	24414	0	0	0
T31	0	32	0	0
T41	0	1147	0	0
T42	0	262	0	0
T43	0	644	0	0
T66	0	360	0	0

gen_edn_if_asserts[1].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200199254	548480	0	326
T1	2402	68	0	0
T2	2035	1023	0	0
T3	25258	12183	0	2
T4	328025	1046	0	2
T8	3497	345	0	0
T13	0	0	0	2
T19	10671	558	0	0
T20	194272	2773	0	2
T21	1183	394	0	0
T22	1315	72	0	0
T23	24414	5248	0	0
T37	0	0	0	2
T40	0	0	0	2
T53	0	0	0	2
T54	0	0	0	2
T61	0	0	0	2
T62	0	0	0	2

gen_edn_if_asserts[1].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200199254	53702	0	119
T1	2402	62	0	1
T2	2035	0	0	0
T3	25258	0	0	0
T4	328025	0	0	0
T8	3497	0	0	0
T17	0	3	0	1
T19	10671	0	0	0
T20	194272	0	0	0
T21	1183	0	0	0
T22	1315	0	0	0
T23	24414	0	0	0
T38	0	34	0	1
T44	0	1	0	0
T45	0	3	0	1
T47	0	3	0	1
T67	0	19	0	1
T68	0	36	0	1
T69	0	3	0	1
T70	0	44	0	1
T71	0	0	0	1

gen_edn_if_asserts[1].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200199254	200031836	0	0
T1	2402	2349	0	0
T2	2035	1841	0	0
T3	25258	14552	0	0
T4	328025	328010	0	0
T8	3497	3407	0	0
T19	10671	10340	0	0
T20	194272	194260	0	0
T21	1183	1044	0	0
T22	1315	1230	0	0
T23	24414	23655	0	0

gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200199254	146589	0	0
T2	2035	24	0	0
T3	25258	7384	0	0
T4	328025	0	0	0
T5	1167	604	0	0
T8	3497	0	0	0
T13	0	8768	0	0
T19	10671	0	0	0
T20	194272	0	0	0
T21	1183	491	0	0
T22	1315	0	0	0
T23	24414	0	0	0
T31	0	32	0	0
T41	0	1147	0	0
T42	0	262	0	0
T43	0	644	0	0
T66	0	360	0	0

gen_edn_if_asserts[2].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200199254	548480	0	326
T1	2402	68	0	0
T2	2035	1023	0	0
T3	25258	12183	0	2
T4	328025	1046	0	2
T8	3497	345	0	0
T13	0	0	0	2
T19	10671	558	0	0
T20	194272	2773	0	2
T21	1183	394	0	0
T22	1315	72	0	0
T23	24414	5248	0	0
T37	0	0	0	2
T40	0	0	0	2
T53	0	0	0	2
T54	0	0	0	2
T61	0	0	0	2
T62	0	0	0	2

gen_edn_if_asserts[2].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200199254	4969	0	119
T1	2402	17	0	1
T2	2035	0	0	0
T3	25258	0	0	0
T4	328025	0	0	0
T8	3497	378	0	1
T12	0	946	0	1
T17	0	3	0	1
T19	10671	0	0	0
T20	194272	0	0	0
T21	1183	0	0	0
T22	1315	0	0	0
T23	24414	0	0	0
T28	0	3	0	1
T29	0	4	0	1
T31	0	1	0	0
T45	0	28	0	1
T46	0	3	0	1
T67	0	0	0	1
T72	0	3	0	1

gen_edn_if_asserts[2].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200199254	200031836	0	0
T1	2402	2349	0	0
T2	2035	1841	0	0
T3	25258	14552	0	0
T4	328025	328010	0	0
T8	3497	3407	0	0
T19	10671	10340	0	0
T20	194272	194260	0	0
T21	1183	1044	0	0
T22	1315	1230	0	0
T23	24414	23655	0	0

gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200199254	146589	0	0
T2	2035	24	0	0
T3	25258	7384	0	0
T4	328025	0	0	0
T5	1167	604	0	0
T8	3497	0	0	0
T13	0	8768	0	0
T19	10671	0	0	0
T20	194272	0	0	0
T21	1183	491	0	0
T22	1315	0	0	0
T23	24414	0	0	0
T31	0	32	0	0
T41	0	1147	0	0
T42	0	262	0	0
T43	0	644	0	0
T66	0	360	0	0

gen_edn_if_asserts[3].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200199254	548480	0	326
T1	2402	68	0	0
T2	2035	1023	0	0
T3	25258	12183	0	2
T4	328025	1046	0	2
T8	3497	345	0	0
T13	0	0	0	2
T19	10671	558	0	0
T20	194272	2773	0	2
T21	1183	394	0	0
T22	1315	72	0	0
T23	24414	5248	0	0
T37	0	0	0	2
T40	0	0	0	2
T53	0	0	0	2
T54	0	0	0	2
T61	0	0	0	2
T62	0	0	0	2

gen_edn_if_asserts[3].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200199254	4226	0	116
T12	5380	0	0	0
T15	0	1	0	0
T17	3387	71	0	1
T28	1280	0	0	0
T29	2239	0	0	0
T30	0	4	0	1
T31	827	0	0	0
T38	0	53	0	1
T39	1587	3	0	1
T40	0	4	0	0
T43	1319	0	0	0
T45	0	17	0	1
T46	0	0	0	1
T48	0	11	0	1
T53	1512	0	0	0
T54	1655	0	0	0
T63	6659	0	0	0
T72	0	15	0	1
T73	0	3	0	1
T74	0	0	0	1

gen_edn_if_asserts[3].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200199254	200031836	0	0
T1	2402	2349	0	0
T2	2035	1841	0	0
T3	25258	14552	0	0
T4	328025	328010	0	0
T8	3497	3407	0	0
T19	10671	10340	0	0
T20	194272	194260	0	0
T21	1183	1044	0	0
T22	1315	1230	0	0
T23	24414	23655	0	0

gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200199254	146589	0	0
T2	2035	24	0	0
T3	25258	7384	0	0
T4	328025	0	0	0
T5	1167	604	0	0
T8	3497	0	0	0
T13	0	8768	0	0
T19	10671	0	0	0
T20	194272	0	0	0
T21	1183	491	0	0
T22	1315	0	0	0
T23	24414	0	0	0
T31	0	32	0	0
T41	0	1147	0	0
T42	0	262	0	0
T43	0	644	0	0
T66	0	360	0	0

gen_edn_if_asserts[4].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200199254	548480	0	326
T1	2402	68	0	0
T2	2035	1023	0	0
T3	25258	12183	0	2
T4	328025	1046	0	2
T8	3497	345	0	0
T13	0	0	0	2
T19	10671	558	0	0
T20	194272	2773	0	2
T21	1183	394	0	0
T22	1315	72	0	0
T23	24414	5248	0	0
T37	0	0	0	2
T40	0	0	0	2
T53	0	0	0	2
T54	0	0	0	2
T61	0	0	0	2
T62	0	0	0	2

gen_edn_if_asserts[4].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200199254	1574	0	96
T1	2402	47	0	1
T2	2035	0	0	0
T3	25258	0	0	0
T4	328025	0	0	0
T8	3497	0	0	0
T19	10671	0	0	0
T20	194272	0	0	0
T21	1183	0	0	0
T22	1315	0	0	0
T23	24414	0	0	0
T38	0	23	0	1
T45	0	11	0	1
T46	0	13	0	1
T47	0	3	0	1
T50	0	58	0	1
T68	0	58	0	1
T70	0	3	0	1
T75	0	3	0	1
T76	0	19	0	1

gen_edn_if_asserts[4].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200199254	200031836	0	0
T1	2402	2349	0	0
T2	2035	1841	0	0
T3	25258	14552	0	0
T4	328025	328010	0	0
T8	3497	3407	0	0
T19	10671	10340	0	0
T20	194272	194260	0	0
T21	1183	1044	0	0
T22	1315	1230	0	0
T23	24414	23655	0	0

gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200199254	146589	0	0
T2	2035	24	0	0
T3	25258	7384	0	0
T4	328025	0	0	0
T5	1167	604	0	0
T8	3497	0	0	0
T13	0	8768	0	0
T19	10671	0	0	0
T20	194272	0	0	0
T21	1183	491	0	0
T22	1315	0	0	0
T23	24414	0	0	0
T31	0	32	0	0
T41	0	1147	0	0
T42	0	262	0	0
T43	0	644	0	0
T66	0	360	0	0

gen_edn_if_asserts[5].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200199254	548480	0	326
T1	2402	68	0	0
T2	2035	1023	0	0
T3	25258	12183	0	2
T4	328025	1046	0	2
T8	3497	345	0	0
T13	0	0	0	2
T19	10671	558	0	0
T20	194272	2773	0	2
T21	1183	394	0	0
T22	1315	72	0	0
T23	24414	5248	0	0
T37	0	0	0	2
T40	0	0	0	2
T53	0	0	0	2
T54	0	0	0	2
T61	0	0	0	2
T62	0	0	0	2

gen_edn_if_asserts[5].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200199254	3725	0	86
T12	5380	0	0	0
T15	0	4	0	0
T17	3387	3	0	1
T18	2284	0	0	0
T27	843	3	0	1
T28	1280	0	0	0
T30	0	4	0	0
T31	827	0	0	0
T38	0	3	0	1
T39	1587	0	0	0
T42	748	1	0	0
T45	0	31	0	1
T47	0	71	0	1
T50	0	0	0	1
T53	1512	0	0	0
T54	1655	0	0	0
T68	0	0	0	1
T72	0	3	0	1
T75	0	0	0	1
T77	0	3	0	1

gen_edn_if_asserts[5].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200199254	200031836	0	0
T1	2402	2349	0	0
T2	2035	1841	0	0
T3	25258	14552	0	0
T4	328025	328010	0	0
T8	3497	3407	0	0
T19	10671	10340	0	0
T20	194272	194260	0	0
T21	1183	1044	0	0
T22	1315	1230	0	0
T23	24414	23655	0	0

gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200199254	146589	0	0
T2	2035	24	0	0
T3	25258	7384	0	0
T4	328025	0	0	0
T5	1167	604	0	0
T8	3497	0	0	0
T13	0	8768	0	0
T19	10671	0	0	0
T20	194272	0	0	0
T21	1183	491	0	0
T22	1315	0	0	0
T23	24414	0	0	0
T31	0	32	0	0
T41	0	1147	0	0
T42	0	262	0	0
T43	0	644	0	0
T66	0	360	0	0

gen_edn_if_asserts[6].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200199254	548480	0	326
T1	2402	68	0	0
T2	2035	1023	0	0
T3	25258	12183	0	2
T4	328025	1046	0	2
T8	3497	345	0	0
T13	0	0	0	2
T19	10671	558	0	0
T20	194272	2773	0	2
T21	1183	394	0	0
T22	1315	72	0	0
T23	24414	5248	0	0
T37	0	0	0	2
T40	0	0	0	2
T53	0	0	0	2
T54	0	0	0	2
T61	0	0	0	2
T62	0	0	0	2

gen_edn_if_asserts[6].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200199254	3885	0	84
T38	6136	3	0	1
T40	3103	0	0	0
T41	1903	0	0	0
T43	1319	1	0	0
T45	0	3	0	1
T47	0	0	0	1
T48	0	27	0	1
T49	0	53	0	1
T50	0	0	0	1
T55	1192	0	0	0
T61	1577	0	0	0
T64	799	0	0	0
T65	839	0	0	0
T66	847	0	0	0
T67	0	3	0	1
T68	0	0	0	1
T74	0	3	0	1
T78	0	1	0	0
T79	0	3	0	1
T80	0	4	0	0
T81	14009	0	0	0

gen_edn_if_asserts[6].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200199254	200031836	0	0
T1	2402	2349	0	0
T2	2035	1841	0	0
T3	25258	14552	0	0
T4	328025	328010	0	0
T8	3497	3407	0	0
T19	10671	10340	0	0
T20	194272	194260	0	0
T21	1183	1044	0	0
T22	1315	1230	0	0
T23	24414	23655	0	0

gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200199254	146589	0	0
T2	2035	24	0	0
T3	25258	7384	0	0
T4	328025	0	0	0
T5	1167	604	0	0
T8	3497	0	0	0
T13	0	8768	0	0
T19	10671	0	0	0
T20	194272	0	0	0
T21	1183	491	0	0
T22	1315	0	0	0
T23	24414	0	0	0
T31	0	32	0	0
T41	0	1147	0	0
T42	0	262	0	0
T43	0	644	0	0
T66	0	360	0	0