Unified Coverage Report :: Module :: edn_main_sm

Module : edn_main_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.33	100.00	94.44		94.59	97.62	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_edn_main_sm	97.33	100.00	94.44		94.59	97.62	100.00

---

Module Instance : tb.dut.u_edn_core.u_edn_main_sm

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.33	100.00	94.44		94.59	97.62	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.35	100.00	94.44		94.59	97.73	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.12	100.00	90.40			98.10	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
TOTAL		108	108	100.00
ALWAYS	42	3	3	100.00
CONT_ASSIGN	44	1	1	100.00
ALWAYS	47	104	104	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	3	3
44	1	1
47	1	1
48	1	1
49	1	1
50	1	1
51	1	1
52	1	1
53	1	1
54	1	1
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
61	1	1
62	1	1
64	1	1
65	1	1
66	1	1
67	1	1
68	1	1
69	1	1
70	1	1
71	1	1
72	1	1
73	1	1
74	1	1
			MISSING_ELSE
78	1	1
79	1	1
80	1	1
83	1	1
84	1	1
85	1	1
			MISSING_ELSE
89	1	1
90	1	1
93	1	1
94	1	1
			MISSING_ELSE
98	1	1
101	1	1
102	1	1
			MISSING_ELSE
106	1	1
107	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
117	1	1
118	1	1
119	1	1
			MISSING_ELSE
123	1	1
124	1	1
125	1	1
			MISSING_ELSE
129	1	1
130	1	1
131	1	1
			MISSING_ELSE
135	1	1
136	1	1
137	1	1
138	1	1
140	1	1
141	1	1
143	1	1
148	1	1
149	1	1
150	1	1
153	1	1
154	1	1
155	1	1
156	1	1
			MISSING_ELSE
160	1	1
161	1	1
162	1	1
165	1	1
166	1	1
167	1	1
168	1	1
			MISSING_ELSE
172	1	1
175	1	1
178	1	1
186	1	1
188	1	1
192	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
201	1	1
211	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_main_sm

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (boot_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T27,T28
1	1	Covered	T22,T27,T28

 LINE       66
 EXPRESSION (auto_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T40,T15
1	1	Covered	T1,T8,T5

 LINE       186
 EXPRESSION (local_escalate_i || csrng_ack_err_i)
             --------1-------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T18,T29,T30
1	0	Covered	T3,T21,T5

 LINE       188
 EXPRESSION (local_escalate_i ? Error : ((state_q == Error) ? Error : RejectCsrngEntropy))
             --------1-------

-1-	Status	Tests
0	Covered	T18,T29,T30
1	Covered	T3,T21,T5

 LINE       188
 SUB-EXPRESSION ((state_q == Error) ? Error : RejectCsrngEntropy)
                 ---------1--------

-1-	Status	Tests
0	Covered	T18,T29,T30
1	Not Covered

 LINE       188
 SUB-EXPRESSION (state_q == Error)
                ---------1--------

-1-	Status	Tests
0	Covered	T3,T21,T5
1	Covered	T3,T21,T5

 LINE       201
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_i)) && 
      2  (state_q inside {BootLoadIns, BootInsAckWait, BootLoadGen, BootGenAckWait, BootLoadUni, BootUniAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode, RejectCsrngEntropy}))

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T22,T5

---

FSM Coverage for Module : edn_main_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	20	20	100.00	(Not included in score)
Transitions	74	70	94.59
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AutoAckWait	156	Covered	T1,T8,T12
AutoCaptGenCnt	143	Covered	T1,T8,T18
AutoCaptReseedCnt	141	Covered	T1,T8,T12
AutoDispatch	125	Covered	T1,T8,T18
AutoFirstAckWait	119	Covered	T1,T8,T18
AutoLoadIns	69	Covered	T1,T8,T5
AutoSendGenCmd	150	Covered	T1,T8,T18
AutoSendReseedCmd	162	Covered	T1,T8,T12
BootDone	98	Covered	T22,T27,T28
BootGenAckWait	90	Covered	T22,T27,T28
BootInsAckWait	80	Covered	T22,T27,T28
BootLoadGen	85	Covered	T22,T27,T28
BootLoadIns	65	Covered	T22,T27,T28
BootLoadUni	102	Covered	T29,T48,T49
BootPulse	94	Covered	T22,T27,T28
BootUniAckWait	107	Covered	T29,T48,T49
Error	188	Covered	T3,T21,T5
Idle	112	Covered	T1,T2,T3
RejectCsrngEntropy	188	Covered	T18,T29,T30
SWPortMode	74	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AutoAckWait->AutoDispatch	131	Covered	T1,T8,T12
AutoAckWait->Error	188	Not Covered
AutoAckWait->Idle	211	Covered	T40,T15,T16
AutoAckWait->RejectCsrngEntropy	188	Covered	T102,T103,T104
AutoCaptGenCnt->AutoSendGenCmd	150	Covered	T1,T8,T18
AutoCaptGenCnt->Error	188	Covered	T105,T106
AutoCaptGenCnt->Idle	211	Covered	T15,T107,T108
AutoCaptGenCnt->RejectCsrngEntropy	188	Covered	T99,T109
AutoCaptReseedCnt->AutoSendReseedCmd	162	Covered	T1,T8,T12
AutoCaptReseedCnt->Error	188	Covered	T110
AutoCaptReseedCnt->Idle	211	Covered	T111,T112,T113
AutoCaptReseedCnt->RejectCsrngEntropy	188	Covered	T114,T115
AutoDispatch->AutoCaptGenCnt	143	Covered	T1,T8,T18
AutoDispatch->AutoCaptReseedCnt	141	Covered	T1,T8,T12
AutoDispatch->Error	188	Not Covered
AutoDispatch->Idle	138	Covered	T1,T8,T12
AutoDispatch->RejectCsrngEntropy	188	Covered	T29,T116
AutoFirstAckWait->AutoDispatch	125	Covered	T1,T8,T18
AutoFirstAckWait->Error	188	Covered	T117,T118
AutoFirstAckWait->Idle	211	Covered	T119,T120,T121
AutoFirstAckWait->RejectCsrngEntropy	188	Covered	T96,T122
AutoLoadIns->AutoFirstAckWait	119	Covered	T1,T8,T18
AutoLoadIns->Error	188	Covered	T5,T7,T123
AutoLoadIns->Idle	211	Covered	T5,T18,T6
AutoLoadIns->RejectCsrngEntropy	188	Covered	T97,T94,T124
AutoSendGenCmd->AutoAckWait	156	Covered	T1,T8,T12
AutoSendGenCmd->Error	188	Covered	T125,T126
AutoSendGenCmd->Idle	211	Covered	T127
AutoSendGenCmd->RejectCsrngEntropy	188	Covered	T18,T128
AutoSendReseedCmd->AutoAckWait	168	Covered	T1,T8,T12
AutoSendReseedCmd->Error	188	Covered	T6,T129,T130
AutoSendReseedCmd->Idle	211	Covered	T16,T131,T80
AutoSendReseedCmd->RejectCsrngEntropy	188	Covered	T132,T133
BootDone->BootLoadUni	102	Covered	T29,T48,T49
BootDone->Error	188	Covered	T134,T135,T136
BootDone->Idle	211	Covered	T137,T138,T139
BootDone->RejectCsrngEntropy	188	Covered	T92,T140,T141
BootGenAckWait->BootPulse	94	Covered	T22,T27,T28
BootGenAckWait->Error	188	Covered	T55,T142,T143
BootGenAckWait->Idle	211	Covered	T28,T41,T77
BootGenAckWait->RejectCsrngEntropy	188	Covered	T51,T144,T145
BootInsAckWait->BootLoadGen	85	Covered	T22,T27,T28
BootInsAckWait->Error	188	Covered	T146,T138,T147
BootInsAckWait->Idle	211	Covered	T27,T55,T65
BootInsAckWait->RejectCsrngEntropy	188	Covered	T93,T148,T149
BootLoadGen->BootGenAckWait	90	Covered	T22,T27,T28
BootLoadGen->Error	188	Covered	T150,T151
BootLoadGen->Idle	211	Covered	T152,T153,T154
BootLoadGen->RejectCsrngEntropy	188	Covered	T98,T155,T156
BootLoadIns->BootInsAckWait	80	Covered	T22,T27,T28
BootLoadIns->Error	188	Covered	T157,T158,T159
BootLoadIns->Idle	211	Covered	T79,T160,T161
BootLoadIns->RejectCsrngEntropy	188	Covered	T101
BootLoadUni->BootUniAckWait	107	Covered	T29,T48,T49
BootLoadUni->Error	188	Covered	T162,T163,T164
BootLoadUni->Idle	211	Not Covered
BootLoadUni->RejectCsrngEntropy	188	Not Covered
BootPulse->BootDone	98	Covered	T22,T27,T28
BootPulse->Error	188	Covered	T165
BootPulse->Idle	211	Covered	T22,T166,T163
BootPulse->RejectCsrngEntropy	188	Covered	T167,T168
BootUniAckWait->Error	188	Covered	T58,T169,T170
BootUniAckWait->Idle	112	Covered	T29,T48,T49
BootUniAckWait->RejectCsrngEntropy	188	Covered	T30,T95,T171
Idle->AutoLoadIns	69	Covered	T1,T8,T5
Idle->BootLoadIns	65	Covered	T22,T27,T28
Idle->Error	188	Covered	T3,T13,T14
Idle->RejectCsrngEntropy	188	Covered	T92,T51,T93
Idle->SWPortMode	74	Covered	T1,T2,T3
RejectCsrngEntropy->Error	188	Covered	T52,T172,T173
RejectCsrngEntropy->Idle	211	Covered	T18,T29,T30
SWPortMode->Error	188	Covered	T3,T21,T13
SWPortMode->Idle	211	Covered	T2,T3,T4
SWPortMode->RejectCsrngEntropy	188	Covered	T18,T29,T30

---

Branch Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
Branches		42	41	97.62
IF	42	2	2	100.00
CASE	62	35	35	100.00
IF	186	5	4	80.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	42	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	62	case (state_q)
-2-:	64	if ((boot_req_mode_i && edn_enable_i))
-3-:	66	if ((auto_req_mode_i && edn_enable_i))
-4-:	70	if (edn_enable_i)
-5-:	84	if (csrng_cmd_ack_i)
-6-:	93	if (csrng_cmd_ack_i)
-7-:	101	if ((!boot_req_mode_i))
-8-:	110	if (csrng_cmd_ack_i)
-9-:	118	if (sw_cmd_req_load_i)
-10-:	124	if (csrng_cmd_ack_i)
-11-:	130	if (csrng_cmd_ack_i)
-12-:	136	if ((!auto_req_mode_i))
-13-:	140	if (max_reqs_cnt_zero_i)
-14-:	155	if (cmd_sent_i)
-15-:	167	if (cmd_sent_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	Status	Tests
Idle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T22,T27,T28
Idle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T8,T5
Idle	0	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
Idle	0	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
BootLoadIns	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T22,T27,T28
BootInsAckWait	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T22,T27,T28
BootInsAckWait	-	-	-	0	-	-	-	-	-	-	-	-	-	-	Covered	T22,T27,T28
BootLoadGen	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T22,T27,T28
BootGenAckWait	-	-	-	-	1	-	-	-	-	-	-	-	-	-	Covered	T22,T27,T28
BootGenAckWait	-	-	-	-	0	-	-	-	-	-	-	-	-	-	Covered	T22,T27,T28
BootPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T22,T27,T28
BootDone	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T29,T48,T49
BootDone	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T22,T27,T28
BootLoadUni	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T29,T48,T49
BootUniAckWait	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T48,T49,T45
BootUniAckWait	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T29,T48,T49
AutoLoadIns	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T1,T8,T18
AutoLoadIns	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T1,T8,T5
AutoFirstAckWait	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T1,T8,T18
AutoFirstAckWait	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T8,T18
AutoAckWait	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T1,T8,T12
AutoAckWait	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T1,T8,T12
AutoDispatch	-	-	-	-	-	-	-	-	-	-	1	-	-	-	Covered	T1,T8,T12
AutoDispatch	-	-	-	-	-	-	-	-	-	-	0	1	-	-	Covered	T1,T8,T12
AutoDispatch	-	-	-	-	-	-	-	-	-	-	0	0	-	-	Covered	T1,T8,T18
AutoCaptGenCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T8,T18
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T1,T8,T18
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T1,T8,T18
AutoCaptReseedCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T8,T12
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T8,T12
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T8,T12
SWPortMode	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
RejectCsrngEntropy	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T18,T29,T30
Error	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T21,T5
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T13,T66

	LineNo.	Expression
-1-:	186	if ((local_escalate_i || csrng_ack_err_i))
-2-:	188	(local_escalate_i) ? 
-3-:	188	((state_q == Error)) ? 
-4-:	201	if (((!edn_enable_i) && (state_q inside {BootLoadIns, BootInsAckWait, BootLoadGen, BootGenAckWait, BootLoadUni, BootUniAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode, RejectCsrngEntropy})))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	1	-	-	Covered	T3,T21,T5
1	0	1	-	Not Covered
1	0	0	-	Covered	T18,T29,T30
0	-	-	1	Covered	T2,T22,T5
0	-	-	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_main_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ErrorStStable_A	200199254	141620	0	0
FpvSecCmErrorStEscalate_A	200199254	142662	0	0
u_state_regs_A	200160419	199993001	0	0

ErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200199254	141620	0	0
T3	25258	7124	0	0
T4	328025	0	0	0
T5	1167	602	0	0
T8	3497	0	0	0
T13	23016	8508	0	0
T19	10671	0	0	0
T20	194272	0	0	0
T21	1183	489	0	0
T22	1315	0	0	0
T23	24414	0	0	0
T41	0	1095	0	0
T42	0	260	0	0
T43	0	642	0	0
T55	0	663	0	0
T66	0	308	0	0
T146	0	969	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200199254	142662	0	0
T3	25258	7254	0	0
T4	328025	0	0	0
T5	1167	603	0	0
T8	3497	0	0	0
T13	23016	8638	0	0
T19	10671	0	0	0
T20	194272	0	0	0
T21	1183	490	0	0
T22	1315	0	0	0
T23	24414	0	0	0
T41	0	1096	0	0
T42	0	261	0	0
T43	0	643	0	0
T55	0	664	0	0
T66	0	309	0	0
T146	0	970	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200160419	199993001	0	0
T1	2402	2349	0	0
T2	2000	1806	0	0
T3	25258	14552	0	0
T4	328025	328010	0	0
T8	3497	3407	0	0
T19	10671	10340	0	0
T20	194272	194260	0	0
T21	1010	871	0	0
T22	1315	1230	0	0
T23	24414	23655	0	0