Unified Coverage Report :: Module :: edn_core

Module : edn_core

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.12	100.00	90.40			98.10	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_core.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core	97.12	100.00	90.40			98.10	100.00

---

Module Instance : tb.dut.u_edn_core

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.12	100.00	90.40			98.10	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.07	99.92	92.44	82.54	91.86	98.81	98.88

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44		83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_ep_blk[0].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
gen_ep_blk[0].u_prim_packer_fifo_ep	98.81	100.00	95.24			100.00	100.00
gen_ep_blk[1].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
gen_ep_blk[1].u_prim_packer_fifo_ep	98.81	100.00	95.24			100.00	100.00
gen_ep_blk[2].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
gen_ep_blk[2].u_prim_packer_fifo_ep	98.81	100.00	95.24			100.00	100.00
gen_ep_blk[3].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
gen_ep_blk[3].u_prim_packer_fifo_ep	98.81	100.00	95.24			100.00	100.00
gen_ep_blk[4].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
gen_ep_blk[4].u_prim_packer_fifo_ep	98.81	100.00	95.24			100.00	100.00
gen_ep_blk[5].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
gen_ep_blk[5].u_prim_packer_fifo_ep	98.81	100.00	95.24			100.00	100.00
gen_ep_blk[6].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
gen_ep_blk[6].u_prim_packer_fifo_ep	98.81	100.00	95.24			100.00	100.00
u_edn_main_sm	97.35	100.00	94.44		94.59	97.73	100.00
u_intr_hw_edn_cmd_req_done	100.00	100.00	100.00			100.00	100.00
u_intr_hw_edn_fatal_err	100.00	100.00	100.00			100.00	100.00
u_prim_arbiter_ppc_packer_arb	95.16	95.00	92.31			100.00	93.33
u_prim_count_max_reqs_cntr	70.79			70.79
u_prim_edge_detector_recov_alert	100.00	100.00	100.00			100.00
u_prim_fifo_sync_gencmd	98.38	100.00	91.89	100.00		100.00	100.00
u_prim_fifo_sync_rescmd	98.38	100.00	91.89	100.00		100.00	100.00
u_prim_mubi4_sync_auto_req_mode	100.00	100.00					100.00
u_prim_mubi4_sync_boot_req_mode	100.00	100.00					100.00
u_prim_mubi4_sync_cmd_fifo_rst	100.00	100.00					100.00
u_prim_mubi4_sync_edn_enable	100.00	100.00					100.00
u_prim_packer_fifo_cs	95.24	100.00	95.24			85.71	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : edn_core

	Line No.	Total	Covered	Percent
TOTAL		255	255	100.00
ALWAYS	220	36	36	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	300	1	1	100.00
CONT_ASSIGN	307	1	1	100.00
CONT_ASSIGN	313	1	1	100.00
CONT_ASSIGN	315	1	1	100.00
CONT_ASSIGN	317	1	1	100.00
CONT_ASSIGN	319	1	1	100.00
CONT_ASSIGN	321	1	1	100.00
CONT_ASSIGN	324	1	1	100.00
CONT_ASSIGN	328	1	1	100.00
CONT_ASSIGN	332	1	1	100.00
CONT_ASSIGN	340	1	1	100.00
CONT_ASSIGN	343	1	1	100.00
CONT_ASSIGN	346	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	352	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	355	1	1	100.00
CONT_ASSIGN	360	1	1	100.00
CONT_ASSIGN	363	1	1	100.00
CONT_ASSIGN	366	1	1	100.00
CONT_ASSIGN	371	1	1	100.00
CONT_ASSIGN	371	1	1	100.00
CONT_ASSIGN	371	1	1	100.00
CONT_ASSIGN	371	1	1	100.00
CONT_ASSIGN	371	1	1	100.00
CONT_ASSIGN	371	1	1	100.00
CONT_ASSIGN	371	1	1	100.00
CONT_ASSIGN	371	1	1	100.00
CONT_ASSIGN	371	1	1	100.00
CONT_ASSIGN	371	1	1	100.00
CONT_ASSIGN	371	1	1	100.00
CONT_ASSIGN	371	1	1	100.00
CONT_ASSIGN	371	1	1	100.00
CONT_ASSIGN	371	1	1	100.00
CONT_ASSIGN	371	1	1	100.00
CONT_ASSIGN	371	1	1	100.00
CONT_ASSIGN	371	1	1	100.00
CONT_ASSIGN	371	1	1	100.00
CONT_ASSIGN	371	1	1	100.00
CONT_ASSIGN	371	1	1	100.00
CONT_ASSIGN	371	1	1	100.00
CONT_ASSIGN	371	1	1	100.00
CONT_ASSIGN	371	1	1	100.00
CONT_ASSIGN	371	1	1	100.00
CONT_ASSIGN	371	1	1	100.00
CONT_ASSIGN	371	1	1	100.00
CONT_ASSIGN	371	1	1	100.00
CONT_ASSIGN	371	1	1	100.00
CONT_ASSIGN	371	1	1	100.00
CONT_ASSIGN	371	1	1	100.00
CONT_ASSIGN	371	1	1	100.00
CONT_ASSIGN	375	1	1	100.00
CONT_ASSIGN	377	1	1	100.00
CONT_ASSIGN	378	1	1	100.00
CONT_ASSIGN	381	1	1	100.00
CONT_ASSIGN	400	1	1	100.00
CONT_ASSIGN	403	1	1	100.00
CONT_ASSIGN	407	1	1	100.00
CONT_ASSIGN	416	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	419	1	1	100.00
CONT_ASSIGN	422	1	1	100.00
CONT_ASSIGN	422	1	1	100.00
CONT_ASSIGN	422	1	1	100.00
CONT_ASSIGN	422	1	1	100.00
CONT_ASSIGN	422	1	1	100.00
CONT_ASSIGN	422	1	1	100.00
CONT_ASSIGN	422	1	1	100.00
CONT_ASSIGN	422	1	1	100.00
CONT_ASSIGN	422	1	1	100.00
CONT_ASSIGN	422	1	1	100.00
CONT_ASSIGN	422	1	1	100.00
CONT_ASSIGN	422	1	1	100.00
CONT_ASSIGN	422	1	1	100.00
CONT_ASSIGN	422	1	1	100.00
CONT_ASSIGN	422	1	1	100.00
CONT_ASSIGN	422	1	1	100.00
CONT_ASSIGN	422	1	1	100.00
CONT_ASSIGN	422	1	1	100.00
CONT_ASSIGN	422	1	1	100.00
CONT_ASSIGN	437	1	1	100.00
CONT_ASSIGN	438	1	1	100.00
CONT_ASSIGN	439	1	1	100.00
CONT_ASSIGN	440	1	1	100.00
CONT_ASSIGN	443	1	1	100.00
CONT_ASSIGN	443	1	1	100.00
CONT_ASSIGN	443	1	1	100.00
CONT_ASSIGN	457	1	1	100.00
CONT_ASSIGN	464	1	1	100.00
CONT_ASSIGN	465	1	1	100.00
CONT_ASSIGN	466	1	1	100.00
CONT_ASSIGN	467	1	1	100.00
CONT_ASSIGN	468	1	1	100.00
CONT_ASSIGN	483	1	1	100.00
CONT_ASSIGN	484	1	1	100.00
CONT_ASSIGN	486	1	1	100.00
CONT_ASSIGN	487	1	1	100.00
CONT_ASSIGN	489	1	1	100.00
CONT_ASSIGN	490	1	1	100.00
CONT_ASSIGN	492	1	1	100.00
CONT_ASSIGN	493	1	1	100.00
CONT_ASSIGN	495	1	1	100.00
CONT_ASSIGN	496	1	1	100.00
CONT_ASSIGN	497	1	1	100.00
CONT_ASSIGN	500	1	1	100.00
CONT_ASSIGN	509	1	1	100.00
CONT_ASSIGN	516	1	1	100.00
CONT_ASSIGN	520	1	1	100.00
CONT_ASSIGN	536	1	1	100.00
CONT_ASSIGN	544	1	1	100.00
CONT_ASSIGN	545	1	1	100.00
CONT_ASSIGN	550	1	1	100.00
CONT_ASSIGN	551	1	1	100.00
CONT_ASSIGN	555	1	1	100.00
CONT_ASSIGN	566	1	1	100.00
CONT_ASSIGN	567	1	1	100.00
CONT_ASSIGN	578	1	1	100.00
CONT_ASSIGN	579	1	1	100.00
CONT_ASSIGN	587	1	1	100.00
CONT_ASSIGN	588	1	1	100.00
CONT_ASSIGN	597	1	1	100.00
CONT_ASSIGN	598	1	1	100.00
CONT_ASSIGN	602	1	1	100.00
CONT_ASSIGN	603	1	1	100.00
CONT_ASSIGN	608	1	1	100.00
CONT_ASSIGN	609	1	1	100.00
CONT_ASSIGN	615	1	1	100.00
CONT_ASSIGN	616	1	1	100.00
CONT_ASSIGN	625	1	1	100.00
CONT_ASSIGN	626	1	1	100.00
CONT_ASSIGN	634	1	1	100.00
CONT_ASSIGN	635	1	1	100.00
CONT_ASSIGN	663	1	1	100.00
CONT_ASSIGN	665	1	1	100.00
CONT_ASSIGN	669	1	1	100.00
CONT_ASSIGN	673	1	1	100.00
CONT_ASSIGN	675	1	1	100.00
CONT_ASSIGN	677	1	1	100.00
CONT_ASSIGN	706	1	1	100.00
CONT_ASSIGN	708	1	1	100.00
CONT_ASSIGN	712	1	1	100.00
CONT_ASSIGN	716	1	1	100.00
CONT_ASSIGN	718	1	1	100.00
CONT_ASSIGN	720	1	1	100.00
CONT_ASSIGN	780	1	1	100.00
CONT_ASSIGN	784	1	1	100.00
CONT_ASSIGN	787	1	1	100.00
CONT_ASSIGN	797	1	1	100.00
CONT_ASSIGN	802	1	1	100.00
CONT_ASSIGN	803	1	1	100.00
CONT_ASSIGN	804	1	1	100.00
CONT_ASSIGN	805	1	1	100.00
CONT_ASSIGN	808	1	1	100.00
CONT_ASSIGN	844	1	1	100.00
CONT_ASSIGN	844	1	1	100.00
CONT_ASSIGN	844	1	1	100.00
CONT_ASSIGN	844	1	1	100.00
CONT_ASSIGN	844	1	1	100.00
CONT_ASSIGN	844	1	1	100.00
CONT_ASSIGN	844	1	1	100.00
CONT_ASSIGN	868	1	1	100.00
CONT_ASSIGN	869	1	1	100.00
CONT_ASSIGN	872	1	1	100.00
CONT_ASSIGN	873	1	1	100.00
CONT_ASSIGN	874	1	1	100.00
CONT_ASSIGN	875	1	1	100.00
CONT_ASSIGN	877	1	1	100.00
CONT_ASSIGN	892	1	1	100.00
CONT_ASSIGN	894	1	1	100.00
CONT_ASSIGN	896	1	1	100.00
CONT_ASSIGN	902	1	1	100.00
CONT_ASSIGN	905	1	1	100.00
CONT_ASSIGN	906	1	1	100.00
CONT_ASSIGN	930	1	1	100.00
CONT_ASSIGN	930	1	1	100.00
CONT_ASSIGN	930	1	1	100.00
CONT_ASSIGN	930	1	1	100.00
CONT_ASSIGN	930	1	1	100.00
CONT_ASSIGN	930	1	1	100.00
CONT_ASSIGN	930	1	1	100.00
CONT_ASSIGN	931	1	1	100.00
CONT_ASSIGN	931	1	1	100.00
CONT_ASSIGN	931	1	1	100.00
CONT_ASSIGN	931	1	1	100.00
CONT_ASSIGN	931	1	1	100.00
CONT_ASSIGN	931	1	1	100.00
CONT_ASSIGN	931	1	1	100.00
CONT_ASSIGN	934	1	1	100.00
CONT_ASSIGN	934	1	1	100.00
CONT_ASSIGN	934	1	1	100.00
CONT_ASSIGN	934	1	1	100.00
CONT_ASSIGN	934	1	1	100.00
CONT_ASSIGN	934	1	1	100.00
CONT_ASSIGN	934	1	1	100.00
CONT_ASSIGN	937	1	1	100.00
CONT_ASSIGN	937	1	1	100.00
CONT_ASSIGN	937	1	1	100.00
CONT_ASSIGN	937	1	1	100.00
CONT_ASSIGN	937	1	1	100.00
CONT_ASSIGN	937	1	1	100.00
CONT_ASSIGN	937	1	1	100.00
CONT_ASSIGN	940	1	1	100.00
CONT_ASSIGN	940	1	1	100.00
CONT_ASSIGN	940	1	1	100.00
CONT_ASSIGN	940	1	1	100.00
CONT_ASSIGN	940	1	1	100.00
CONT_ASSIGN	940	1	1	100.00
CONT_ASSIGN	940	1	1	100.00
CONT_ASSIGN	941	1	1	100.00
CONT_ASSIGN	941	1	1	100.00
CONT_ASSIGN	941	1	1	100.00
CONT_ASSIGN	941	1	1	100.00
CONT_ASSIGN	941	1	1	100.00
CONT_ASSIGN	941	1	1	100.00
CONT_ASSIGN	941	1	1	100.00
CONT_ASSIGN	961	1	1	100.00
CONT_ASSIGN	977	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_core.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_core.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
220	1	1
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
253	1	1
254	1	1
255	1	1
256	1	1
295	1	1
300	1	1
307	1	1
313	1	1
315	1	1
317	1	1
319	1	1
321	1	1
324	1	1
328	1	1
332	1	1
340	1	1
343	1	1
346	1	1
349	1	1
352	1	1
354	1	1
355	1	1
360	1	1
363	1	1
366	1	1
371	31	31
375	1	1
377	1	1
378	1	1
381	1	1
400	1	1
403	1	1
407	1	1
416	1	1
417	1	1
418	1	1
419	1	1
422	19	19
437	1	1
438	1	1
439	1	1
440	1	1
443	3	3
457	1	1
464	1	1
465	1	1
466	1	1
467	1	1
468	1	1
483	1	1
484	1	1
486	1	1
487	1	1
489	1	1
490	1	1
492	1	1
493	1	1
495	1	1
496	1	1
497	1	1
500	1	1
509	1	1
516	1	1
520	1	1
536	1	1
544	1	1
545	1	1
550	1	1
551	1	1
555	1	1
566	1	1
567	1	1
578	1	1
579	1	1
587	1	1
588	1	1
597	1	1
598	1	1
602	1	1
603	1	1
608	1	1
609	1	1
615	1	1
616	1	1
625	1	1
626	1	1
634	1	1
635	1	1
663	1	1
665	1	1
669	1	1
673	1	1
675	1	1
677	1	1
706	1	1
708	1	1
712	1	1
716	1	1
718	1	1
720	1	1
780	1	1
784	1	1
787	1	1
797	1	1
802	1	1
803	1	1
804	1	1
805	1	1
808	1	1
844	7	7
868	1	1
869	1	1
872	1	1
873	1	1
874	1	1
875	1	1
877	1	1
892	1	1
894	1	1
896	1	1
902	1	1
905	1	1
906	1	1
930	7	7
931	7	7
934	7	7
937	7	7
940	7	7
941	7	7
961	1	1
977	1	1

---

Cond Coverage for Module : edn_core

	Total	Covered	Percent
Conditions	646	584	90.40
Logical	646	584	90.40
Non-Logical	0	0
Event	0	0

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.

Line numbers	Percent
295-706	91.52
708-977	87.88

---

Branch Coverage for Module : edn_core

	Line No.	Total	Covered	Percent
Branches		105	103	98.10
TERNARY	500	6	6	100.00
TERNARY	509	4	4	100.00
TERNARY	520	7	7	100.00
TERNARY	536	5	5	100.00
TERNARY	555	7	6	85.71
TERNARY	567	7	6	85.71
TERNARY	579	3	3	100.00
TERNARY	588	4	4	100.00
TERNARY	603	3	3	100.00
TERNARY	609	3	3	100.00
TERNARY	616	4	4	100.00
TERNARY	626	4	4	100.00
TERNARY	635	3	3	100.00
TERNARY	665	2	2	100.00
TERNARY	669	2	2	100.00
TERNARY	708	2	2	100.00
TERNARY	712	2	2	100.00
TERNARY	787	6	6	100.00
TERNARY	877	3	3	100.00
TERNARY	894	2	2	100.00
TERNARY	896	3	3	100.00
TERNARY	934	3	3	100.00
TERNARY	934	3	3	100.00
TERNARY	934	3	3	100.00
TERNARY	934	3	3	100.00
TERNARY	934	3	3	100.00
TERNARY	934	3	3	100.00
TERNARY	934	3	3	100.00
IF	220	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_core.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_core.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	500	((!edn_enable_fo[CsrngCmdReq])) ? 
-2-:	500	(boot_wr_ins_cmd) ? 
-3-:	500	(boot_wr_gen_cmd) ? 
-4-:	500	(boot_wr_uni_cmd) ? 
-5-:	500	(sw_cmd_req_load) ? 

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T22,T27,T28
0	0	1	-	-	Covered	T22,T27,T28
0	0	0	1	-	Covered	T29,T48,T49
0	0	0	0	1	Covered	T1,T2,T4
0	0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	509	((!edn_enable_fo[CsrngCmdReqValid])) ? 
-2-:	509	(cs_cmd_handshake) ? 
-3-:	509	((((sw_cmd_req_load || boot_wr_ins_cmd) || boot_wr_gen_cmd) || boot_wr_uni_cmd)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T4
0	0	1	Covered	T1,T2,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	520	((!edn_enable_fo[CsrngCmdReqOut])) ? 
-2-:	520	((send_rescmd || capt_rescmd_fifo_cnt)) ? 
-3-:	520	(sfifo_rescmd_pop) ? 
-4-:	520	((send_gencmd || capt_gencmd_fifo_cnt)) ? 
-5-:	520	(sfifo_gencmd_pop) ? 
-6-:	520	((cs_cmd_req_vld_q && (!cs_cmd_handshake))) ? 

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
1	-	-	-	-	-	Covered	T1,T2,T3
0	1	1	-	-	-	Covered	T1,T8,T12
0	1	0	-	-	-	Covered	T1,T8,T12
0	0	-	1	1	-	Covered	T1,T8,T18
0	0	-	1	0	-	Covered	T1,T8,T18
0	0	-	0	-	1	Covered	T1,T2,T4
0	0	-	0	-	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	536	((!edn_enable_fo[CsrngCmdReqValidOut])) ? 
-2-:	536	(cmd_sent) ? 
-3-:	536	((send_rescmd || capt_rescmd_fifo_cnt)) ? 
-4-:	536	((send_gencmd || capt_gencmd_fifo_cnt)) ? 

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Covered	T1,T8,T18
0	0	1	-	Covered	T1,T8,T12
0	0	0	1	Covered	T1,T8,T18
0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	555	((!edn_enable_fo[SwCmdSts])) ? 
-2-:	555	((!sw_cmd_mode)) ? 
-3-:	555	(reject_csrng_entropy) ? 
-4-:	555	(sw_cmd_req_load) ? 
-5-:	555	(accept_sw_cmds_pulse) ? 
-6-:	555	(csrng_cmd_i.csrng_rsp_ack) ? 

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
1	-	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	-	Covered	T1,T3,T21
0	0	1	-	-	-	Not Covered
0	0	0	1	-	-	Covered	T1,T2,T4
0	0	0	0	1	-	Covered	T1,T2,T3
0	0	0	0	0	1	Covered	T1,T2,T4
0	0	0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	567	((!edn_enable_fo[SwCmdSts])) ? 
-2-:	567	((!sw_cmd_mode)) ? 
-3-:	567	(reject_csrng_entropy) ? 
-4-:	567	(sw_cmd_req_load) ? 
-5-:	567	(accept_sw_cmds_pulse) ? 
-6-:	567	(cs_cmd_handshake) ? 

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
1	-	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	-	Covered	T1,T3,T21
0	0	1	-	-	-	Not Covered
0	0	0	1	-	-	Covered	T1,T2,T4
0	0	0	0	1	-	Covered	T1,T2,T3
0	0	0	0	0	1	Covered	T1,T2,T4
0	0	0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	579	((!edn_enable_fo[SwCmdSts])) ? 
-2-:	579	(((csrng_cmd_i.csrng_rsp_ack && sw_cmd_mode) && (!reject_csrng_entropy))) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	588	((!edn_enable_fo[SwCmdSts])) ? 
-2-:	588	(sw_cmd_req_load) ? 
-3-:	588	(((csrng_cmd_i.csrng_rsp_ack && sw_cmd_mode) && (!reject_csrng_entropy))) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T4
0	0	1	Covered	T1,T2,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	603	((main_sm_done_pulse || main_sm_idle)) ? 
-2-:	603	((boot_send_ins_cmd && cs_hw_cmd_handshake)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T22,T27,T28
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	609	((main_sm_done_pulse || main_sm_idle)) ? 
-2-:	609	((auto_req_mode_busy && cs_hw_cmd_handshake)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T8,T18
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	616	((!edn_enable_fo[HwCmdSts])) ? 
-2-:	616	(((csrng_cmd_i.csrng_rsp_ack && (!sw_cmd_mode)) && (!reject_csrng_entropy))) ? 
-3-:	616	(cs_hw_cmd_handshake) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T8,T22
0	0	1	Covered	T1,T8,T22
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	626	((!edn_enable_fo[HwCmdSts])) ? 
-2-:	626	(((csrng_cmd_i.csrng_rsp_ack && (!sw_cmd_mode)) && (!reject_csrng_entropy))) ? 
-3-:	626	(cs_hw_cmd_handshake) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T8,T22
0	0	1	Covered	T1,T8,T22
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	635	((!edn_enable_fo[HwCmdSts])) ? 
-2-:	635	(cs_hw_cmd_handshake) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T8,T22
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	665	(rescmd_handshake) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T8,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	669	(auto_req_mode_busy) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T8,T18
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	708	(gencmd_handshake) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T8,T18
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	712	(auto_req_mode_busy) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T8,T18
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	787	((!edn_enable_fo[CmdFifoCnt])) ? 
-2-:	787	((cmd_fifo_rst_fo[3] || main_sm_done_pulse)) ? 
-3-:	787	(capt_gencmd_fifo_cnt) ? 
-4-:	787	(capt_rescmd_fifo_cnt) ? 
-5-:	787	((sfifo_gencmd_pop || sfifo_rescmd_pop)) ? 

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T1,T2,T3
0	0	1	-	-	Covered	T1,T8,T18
0	0	0	1	-	Covered	T1,T8,T12
0	0	0	0	1	Covered	T1,T8,T12
0	0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	877	((!edn_enable_fo[CsrngFipsEn])) ? 
-2-:	877	((packer_cs_push && packer_cs_wready)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	894	(cs_rdata_capt_vld) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	896	((!edn_enable_fo[CsrngDataVld])) ? 
-2-:	896	(cs_rdata_capt_vld) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	934	(packer_ep_clr[0]) ? 
-2-:	934	((packer_ep_push[0] && packer_ep_wready[0])) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	934	(packer_ep_clr[1]) ? 
-2-:	934	((packer_ep_push[1] && packer_ep_wready[1])) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T17,T38
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	934	(packer_ep_clr[2]) ? 
-2-:	934	((packer_ep_push[2] && packer_ep_wready[2])) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T8,T12
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	934	(packer_ep_clr[3]) ? 
-2-:	934	((packer_ep_push[3] && packer_ep_wready[3])) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T39,T17,T40
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	934	(packer_ep_clr[4]) ? 
-2-:	934	((packer_ep_push[4] && packer_ep_wready[4])) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T38,T45
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	934	(packer_ep_clr[5]) ? 
-2-:	934	((packer_ep_push[5] && packer_ep_wready[5])) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T42,T27,T17
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	934	(packer_ep_clr[6]) ? 
-2-:	934	((packer_ep_push[6] && packer_ep_wready[6])) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T43,T38,T48
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	220	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_core

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CsErrAcceptNoEntropy_A	200199254	7770	0	0
CsErrIssueNoCommands_A	200199254	7770	0	0

CsErrAcceptNoEntropy_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200199254	7770	0	0
T12	5380	0	0	0
T17	3387	0	0	0
T18	2284	204	0	0
T28	1280	0	0	0
T29	2239	187	0	0
T30	0	148	0	0
T31	827	0	0	0
T39	1587	0	0	0
T51	0	136	0	0
T52	0	1	0	0
T53	1512	0	0	0
T54	1655	0	0	0
T63	6659	0	0	0
T92	0	218	0	0
T93	0	172	0	0
T95	0	148	0	0
T96	0	136	0	0
T101	0	205	0	0

CsErrIssueNoCommands_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200199254	7770	0	0
T12	5380	0	0	0
T17	3387	0	0	0
T18	2284	204	0	0
T28	1280	0	0	0
T29	2239	187	0	0
T30	0	148	0	0
T31	827	0	0	0
T39	1587	0	0	0
T51	0	136	0	0
T52	0	1	0	0
T53	1512	0	0	0
T54	1655	0	0	0
T63	6659	0	0	0
T92	0	218	0	0
T93	0	172	0	0
T95	0	148	0	0
T96	0	136	0	0
T101	0	205	0	0