Unified Coverage Report :: Module :: edn_ack_sm

Module : edn_ack_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.12	100.00	90.40			98.10	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.12	100.00	90.40			98.10	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.12	100.00	90.40			98.10	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.12	100.00	90.40			98.10	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.12	100.00	90.40			98.10	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.12	100.00	90.40			98.10	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.12	100.00	90.40			98.10	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_ack_sm

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T22,T5

---

FSM Coverage for Module : edn_ack_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T1,T2,T4
DataWait	75	Covered	T1,T2,T4
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T3,T21,T5
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T22,T166,T174
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T1,T2,T4
DataWait->AckPls	80	Covered	T1,T2,T4
DataWait->Disabled	107	Covered	T27,T28,T65
DataWait->Error	99	Covered	T55,T175,T176
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T3,T13,T14
EndPointClear->Disabled	107	Covered	T19,T79,T160
EndPointClear->Error	99	Covered	T3,T5,T13
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T1,T2,T4
Idle->Disabled	107	Covered	T2,T3,T4
Idle->Error	99	Covered	T21,T42,T43

---

Branch Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T1,T2,T4
Idle	-	1	0	-	Covered	T1,T2,T4
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T1,T2,T4
DataWait	-	-	-	0	Covered	T1,T4,T19
AckPls	-	-	-	-	Covered	T1,T2,T4
Error	-	-	-	-	Covered	T3,T21,T5
default	-	-	-	-	Covered	T3,T21,T13

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T21,T5
0	1	Covered	T2,T22,T5
0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_ack_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	1401394778	1007240	0	0
FpvSecCmErrorStEscalate_A	1401394778	1014534	0	0
u_state_regs_A	1401355943	1400184017	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1401394778	1007240	0	0
T3	176806	49868	0	0
T4	2296175	0	0	0
T5	8169	4214	0	0
T8	24479	0	0	0
T13	161112	59556	0	0
T19	74697	0	0	0
T20	1359904	0	0	0
T21	8281	3373	0	0
T22	9205	0	0	0
T23	170898	0	0	0
T41	0	8015	0	0
T42	0	1820	0	0
T43	0	4444	0	0
T55	0	4641	0	0
T66	0	2506	0	0
T146	0	6733	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1401394778	1014534	0	0
T3	176806	50778	0	0
T4	2296175	0	0	0
T5	8169	4221	0	0
T8	24479	0	0	0
T13	161112	60466	0	0
T19	74697	0	0	0
T20	1359904	0	0	0
T21	8281	3380	0	0
T22	9205	0	0	0
T23	170898	0	0	0
T41	0	8022	0	0
T42	0	1827	0	0
T43	0	4451	0	0
T55	0	4648	0	0
T66	0	2513	0	0
T146	0	6740	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1401355943	1400184017	0	0
T1	16814	16443	0	0
T2	14210	12852	0	0
T3	176806	101864	0	0
T4	2296175	2296070	0	0
T8	24479	23849	0	0
T19	74697	72380	0	0
T20	1359904	1359820	0	0
T21	8108	7135	0	0
T22	9205	8610	0	0
T23	170898	165585	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T22,T5

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T1,T17,T38
DataWait	75	Covered	T1,T17,T38
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T3,T21,T5
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T1,T17,T38
DataWait->AckPls	80	Covered	T1,T17,T38
DataWait->Disabled	107	Covered	T177,T178,T127
DataWait->Error	99	Covered	T176,T163,T142
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T3,T13,T14
EndPointClear->Disabled	107	Covered	T19,T79,T160
EndPointClear->Error	99	Covered	T3,T5,T13
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T1,T17,T38
Idle->Disabled	107	Covered	T2,T3,T4
Idle->Error	99	Covered	T21,T42,T43

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T1,T17,T38
Idle	-	1	0	-	Covered	T1,T17,T38
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T1,T17,T38
DataWait	-	-	-	0	Covered	T1,T17,T38
AckPls	-	-	-	-	Covered	T1,T17,T38
Error	-	-	-	-	Covered	T3,T21,T5
default	-	-	-	-	Covered	T3,T13,T14

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T21,T5
0	1	Covered	T2,T22,T5
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	200199254	144170	0	0
FpvSecCmErrorStEscalate_A	200199254	145212	0	0
u_state_regs_A	200199254	200031836	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200199254	144170	0	0
T3	25258	7124	0	0
T4	328025	0	0	0
T5	1167	602	0	0
T8	3497	0	0	0
T13	23016	8508	0	0
T19	10671	0	0	0
T20	194272	0	0	0
T21	1183	489	0	0
T22	1315	0	0	0
T23	24414	0	0	0
T41	0	1145	0	0
T42	0	260	0	0
T43	0	642	0	0
T55	0	663	0	0
T66	0	358	0	0
T146	0	969	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200199254	145212	0	0
T3	25258	7254	0	0
T4	328025	0	0	0
T5	1167	603	0	0
T8	3497	0	0	0
T13	23016	8638	0	0
T19	10671	0	0	0
T20	194272	0	0	0
T21	1183	490	0	0
T22	1315	0	0	0
T23	24414	0	0	0
T41	0	1146	0	0
T42	0	261	0	0
T43	0	643	0	0
T55	0	664	0	0
T66	0	359	0	0
T146	0	970	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200199254	200031836	0	0
T1	2402	2349	0	0
T2	2035	1841	0	0
T3	25258	14552	0	0
T4	328025	328010	0	0
T8	3497	3407	0	0
T19	10671	10340	0	0
T20	194272	194260	0	0
T21	1183	1044	0	0
T22	1315	1230	0	0
T23	24414	23655	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T22,T5

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T1,T8,T12
DataWait	75	Covered	T1,T8,T12
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T3,T21,T5
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T1,T8,T12
DataWait->AckPls	80	Covered	T1,T8,T12
DataWait->Disabled	107	Covered	T28,T179
DataWait->Error	99	Covered	T55,T134,T172
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T3,T13,T14
EndPointClear->Disabled	107	Covered	T19,T79,T160
EndPointClear->Error	99	Covered	T3,T5,T13
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T1,T8,T12
Idle->Disabled	107	Covered	T2,T3,T4
Idle->Error	99	Covered	T21,T42,T43

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T1,T8,T12
Idle	-	1	0	-	Covered	T1,T8,T12
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T1,T8,T12
DataWait	-	-	-	0	Covered	T1,T8,T12
AckPls	-	-	-	-	Covered	T1,T8,T12
Error	-	-	-	-	Covered	T3,T21,T5
default	-	-	-	-	Covered	T3,T13,T14

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T21,T5
0	1	Covered	T2,T22,T5
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	200199254	144170	0	0
FpvSecCmErrorStEscalate_A	200199254	145212	0	0
u_state_regs_A	200199254	200031836	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200199254	144170	0	0
T3	25258	7124	0	0
T4	328025	0	0	0
T5	1167	602	0	0
T8	3497	0	0	0
T13	23016	8508	0	0
T19	10671	0	0	0
T20	194272	0	0	0
T21	1183	489	0	0
T22	1315	0	0	0
T23	24414	0	0	0
T41	0	1145	0	0
T42	0	260	0	0
T43	0	642	0	0
T55	0	663	0	0
T66	0	358	0	0
T146	0	969	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200199254	145212	0	0
T3	25258	7254	0	0
T4	328025	0	0	0
T5	1167	603	0	0
T8	3497	0	0	0
T13	23016	8638	0	0
T19	10671	0	0	0
T20	194272	0	0	0
T21	1183	490	0	0
T22	1315	0	0	0
T23	24414	0	0	0
T41	0	1146	0	0
T42	0	261	0	0
T43	0	643	0	0
T55	0	664	0	0
T66	0	359	0	0
T146	0	970	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200199254	200031836	0	0
T1	2402	2349	0	0
T2	2035	1841	0	0
T3	25258	14552	0	0
T4	328025	328010	0	0
T8	3497	3407	0	0
T19	10671	10340	0	0
T20	194272	194260	0	0
T21	1183	1044	0	0
T22	1315	1230	0	0
T23	24414	23655	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T22,T5

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T43,T38,T48
DataWait	75	Covered	T43,T38,T48
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T3,T21,T5
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T43,T38,T48
DataWait->AckPls	80	Covered	T43,T38,T48
DataWait->Disabled	107	Covered	T180,T107,T181
DataWait->Error	99	Covered	T106
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T3,T13,T14
EndPointClear->Disabled	107	Covered	T19,T79,T160
EndPointClear->Error	99	Covered	T3,T5,T13
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T43,T38,T48
Idle->Disabled	107	Covered	T2,T3,T4
Idle->Error	99	Covered	T21,T42,T43

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T43,T38,T48
Idle	-	1	0	-	Covered	T43,T38,T48
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T43,T38,T48
DataWait	-	-	-	0	Covered	T38,T48,T49
AckPls	-	-	-	-	Covered	T43,T38,T48
Error	-	-	-	-	Covered	T3,T21,T5
default	-	-	-	-	Covered	T3,T13,T14

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T21,T5
0	1	Covered	T2,T22,T5
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	200199254	144170	0	0
FpvSecCmErrorStEscalate_A	200199254	145212	0	0
u_state_regs_A	200199254	200031836	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200199254	144170	0	0
T3	25258	7124	0	0
T4	328025	0	0	0
T5	1167	602	0	0
T8	3497	0	0	0
T13	23016	8508	0	0
T19	10671	0	0	0
T20	194272	0	0	0
T21	1183	489	0	0
T22	1315	0	0	0
T23	24414	0	0	0
T41	0	1145	0	0
T42	0	260	0	0
T43	0	642	0	0
T55	0	663	0	0
T66	0	358	0	0
T146	0	969	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200199254	145212	0	0
T3	25258	7254	0	0
T4	328025	0	0	0
T5	1167	603	0	0
T8	3497	0	0	0
T13	23016	8638	0	0
T19	10671	0	0	0
T20	194272	0	0	0
T21	1183	490	0	0
T22	1315	0	0	0
T23	24414	0	0	0
T41	0	1146	0	0
T42	0	261	0	0
T43	0	643	0	0
T55	0	664	0	0
T66	0	359	0	0
T146	0	970	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200199254	200031836	0	0
T1	2402	2349	0	0
T2	2035	1841	0	0
T3	25258	14552	0	0
T4	328025	328010	0	0
T8	3497	3407	0	0
T19	10671	10340	0	0
T20	194272	194260	0	0
T21	1183	1044	0	0
T22	1315	1230	0	0
T23	24414	23655	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T22,T5

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T1,T2,T4
DataWait	75	Covered	T1,T2,T4
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T3,T21,T5
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T22,T174
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T1,T2,T4
DataWait->AckPls	80	Covered	T1,T2,T4
DataWait->Disabled	107	Covered	T65,T152,T182
DataWait->Error	99	Covered	T175,T183,T184
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T3,T13,T14
EndPointClear->Disabled	107	Covered	T19,T79,T160
EndPointClear->Error	99	Covered	T3,T5,T13
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T1,T2,T4
Idle->Disabled	107	Covered	T2,T3,T4
Idle->Error	99	Covered	T42,T66,T41

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T1,T2,T4
Idle	-	1	0	-	Covered	T1,T2,T4
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T1,T2,T4
DataWait	-	-	-	0	Covered	T1,T4,T19
AckPls	-	-	-	-	Covered	T1,T2,T4
Error	-	-	-	-	Covered	T3,T21,T5
default	-	-	-	-	Covered	T3,T21,T13

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T21,T5
0	1	Covered	T2,T22,T5
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	200199254	142220	0	0
FpvSecCmErrorStEscalate_A	200199254	143262	0	0
u_state_regs_A	200160419	199993001	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200199254	142220	0	0
T3	25258	7124	0	0
T4	328025	0	0	0
T5	1167	602	0	0
T8	3497	0	0	0
T13	23016	8508	0	0
T19	10671	0	0	0
T20	194272	0	0	0
T21	1183	439	0	0
T22	1315	0	0	0
T23	24414	0	0	0
T41	0	1145	0	0
T42	0	260	0	0
T43	0	592	0	0
T55	0	663	0	0
T66	0	358	0	0
T146	0	919	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200199254	143262	0	0
T3	25258	7254	0	0
T4	328025	0	0	0
T5	1167	603	0	0
T8	3497	0	0	0
T13	23016	8638	0	0
T19	10671	0	0	0
T20	194272	0	0	0
T21	1183	440	0	0
T22	1315	0	0	0
T23	24414	0	0	0
T41	0	1146	0	0
T42	0	261	0	0
T43	0	593	0	0
T55	0	664	0	0
T66	0	359	0	0
T146	0	920	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200160419	199993001	0	0
T1	2402	2349	0	0
T2	2000	1806	0	0
T3	25258	14552	0	0
T4	328025	328010	0	0
T8	3497	3407	0	0
T19	10671	10340	0	0
T20	194272	194260	0	0
T21	1010	871	0	0
T22	1315	1230	0	0
T23	24414	23655	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T22,T5

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T39,T17,T40
DataWait	75	Covered	T39,T17,T40
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T3,T21,T5
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T185
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T39,T17,T40
DataWait->AckPls	80	Covered	T39,T17,T40
DataWait->Disabled	107	Covered	T73,T15,T153
DataWait->Error	99	Covered	T52,T58,T186
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T3,T13,T14
EndPointClear->Disabled	107	Covered	T19,T79,T160
EndPointClear->Error	99	Covered	T3,T5,T13
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T39,T17,T40
Idle->Disabled	107	Covered	T2,T3,T4
Idle->Error	99	Covered	T21,T42,T43

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T39,T17,T40
Idle	-	1	0	-	Covered	T39,T17,T40
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T39,T17,T40
DataWait	-	-	-	0	Covered	T39,T17,T40
AckPls	-	-	-	-	Covered	T39,T17,T40
Error	-	-	-	-	Covered	T3,T21,T5
default	-	-	-	-	Covered	T3,T13,T14

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T21,T5
0	1	Covered	T2,T22,T5
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	200199254	144170	0	0
FpvSecCmErrorStEscalate_A	200199254	145212	0	0
u_state_regs_A	200199254	200031836	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200199254	144170	0	0
T3	25258	7124	0	0
T4	328025	0	0	0
T5	1167	602	0	0
T8	3497	0	0	0
T13	23016	8508	0	0
T19	10671	0	0	0
T20	194272	0	0	0
T21	1183	489	0	0
T22	1315	0	0	0
T23	24414	0	0	0
T41	0	1145	0	0
T42	0	260	0	0
T43	0	642	0	0
T55	0	663	0	0
T66	0	358	0	0
T146	0	969	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200199254	145212	0	0
T3	25258	7254	0	0
T4	328025	0	0	0
T5	1167	603	0	0
T8	3497	0	0	0
T13	23016	8638	0	0
T19	10671	0	0	0
T20	194272	0	0	0
T21	1183	490	0	0
T22	1315	0	0	0
T23	24414	0	0	0
T41	0	1146	0	0
T42	0	261	0	0
T43	0	643	0	0
T55	0	664	0	0
T66	0	359	0	0
T146	0	970	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200199254	200031836	0	0
T1	2402	2349	0	0
T2	2035	1841	0	0
T3	25258	14552	0	0
T4	328025	328010	0	0
T8	3497	3407	0	0
T19	10671	10340	0	0
T20	194272	194260	0	0
T21	1183	1044	0	0
T22	1315	1230	0	0
T23	24414	23655	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T22,T5

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T1,T38,T45
DataWait	75	Covered	T1,T38,T45
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T3,T21,T5
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T166,T187
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T1,T38,T45
DataWait->AckPls	80	Covered	T1,T38,T45
DataWait->Disabled	107	Covered	T188
DataWait->Error	99	Covered	T189,T105,T165
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T3,T13,T14
EndPointClear->Disabled	107	Covered	T19,T79,T160
EndPointClear->Error	99	Covered	T3,T5,T13
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T1,T38,T45
Idle->Disabled	107	Covered	T2,T3,T4
Idle->Error	99	Covered	T21,T42,T43

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T1,T38,T45
Idle	-	1	0	-	Covered	T1,T41,T38
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T1,T38,T45
DataWait	-	-	-	0	Covered	T1,T38,T45
AckPls	-	-	-	-	Covered	T1,T38,T45
Error	-	-	-	-	Covered	T3,T21,T5
default	-	-	-	-	Covered	T3,T13,T14

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T21,T5
0	1	Covered	T2,T22,T5
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	200199254	144170	0	0
FpvSecCmErrorStEscalate_A	200199254	145212	0	0
u_state_regs_A	200199254	200031836	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200199254	144170	0	0
T3	25258	7124	0	0
T4	328025	0	0	0
T5	1167	602	0	0
T8	3497	0	0	0
T13	23016	8508	0	0
T19	10671	0	0	0
T20	194272	0	0	0
T21	1183	489	0	0
T22	1315	0	0	0
T23	24414	0	0	0
T41	0	1145	0	0
T42	0	260	0	0
T43	0	642	0	0
T55	0	663	0	0
T66	0	358	0	0
T146	0	969	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200199254	145212	0	0
T3	25258	7254	0	0
T4	328025	0	0	0
T5	1167	603	0	0
T8	3497	0	0	0
T13	23016	8638	0	0
T19	10671	0	0	0
T20	194272	0	0	0
T21	1183	490	0	0
T22	1315	0	0	0
T23	24414	0	0	0
T41	0	1146	0	0
T42	0	261	0	0
T43	0	643	0	0
T55	0	664	0	0
T66	0	359	0	0
T146	0	970	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200199254	200031836	0	0
T1	2402	2349	0	0
T2	2035	1841	0	0
T3	25258	14552	0	0
T4	328025	328010	0	0
T8	3497	3407	0	0
T19	10671	10340	0	0
T20	194272	194260	0	0
T21	1183	1044	0	0
T22	1315	1230	0	0
T23	24414	23655	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T22,T5

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T42,T27,T17
DataWait	75	Covered	T42,T27,T17
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T3,T21,T5
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T190
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T42,T27,T17
DataWait->AckPls	80	Covered	T42,T27,T17
DataWait->Disabled	107	Covered	T27,T77,T154
DataWait->Error	99	Covered	T7,T169,T150
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T3,T13,T14
EndPointClear->Disabled	107	Covered	T19,T79,T160
EndPointClear->Error	99	Covered	T3,T5,T13
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T42,T27,T17
Idle->Disabled	107	Covered	T2,T3,T4
Idle->Error	99	Covered	T21,T42,T43

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T42,T27,T17
Idle	-	1	0	-	Covered	T42,T27,T17
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T42,T27,T17
DataWait	-	-	-	0	Covered	T27,T17,T38
AckPls	-	-	-	-	Covered	T42,T27,T17
Error	-	-	-	-	Covered	T3,T21,T5
default	-	-	-	-	Covered	T3,T13,T14

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T21,T5
0	1	Covered	T2,T22,T5
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	200199254	144170	0	0
FpvSecCmErrorStEscalate_A	200199254	145212	0	0
u_state_regs_A	200199254	200031836	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200199254	144170	0	0
T3	25258	7124	0	0
T4	328025	0	0	0
T5	1167	602	0	0
T8	3497	0	0	0
T13	23016	8508	0	0
T19	10671	0	0	0
T20	194272	0	0	0
T21	1183	489	0	0
T22	1315	0	0	0
T23	24414	0	0	0
T41	0	1145	0	0
T42	0	260	0	0
T43	0	642	0	0
T55	0	663	0	0
T66	0	358	0	0
T146	0	969	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200199254	145212	0	0
T3	25258	7254	0	0
T4	328025	0	0	0
T5	1167	603	0	0
T8	3497	0	0	0
T13	23016	8638	0	0
T19	10671	0	0	0
T20	194272	0	0	0
T21	1183	490	0	0
T22	1315	0	0	0
T23	24414	0	0	0
T41	0	1146	0	0
T42	0	261	0	0
T43	0	643	0	0
T55	0	664	0	0
T66	0	359	0	0
T146	0	970	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200199254	200031836	0	0
T1	2402	2349	0	0
T2	2035	1841	0	0
T3	25258	14552	0	0
T4	328025	328010	0	0
T8	3497	3407	0	0
T19	10671	10340	0	0
T20	194272	194260	0	0
T21	1183	1044	0	0
T22	1315	1230	0	0
T23	24414	23655	0	0