Module Definition
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Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.64 100.00 78.57 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.38 100.00 91.89 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.12 100.00 90.40 98.10 100.00 u_edn_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.64 100.00 78.57 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.38 100.00 91.89 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.12 100.00 90.40 98.10 100.00 u_edn_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 100.00 100.00 100.00 100.00 100.00

Line Coverage for Module : prim_fifo_sync
Line No.TotalCoveredPercent
TOTAL1414100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN12011100.00
ALWAYS12322100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN14011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
120 1 1
123 1 1
124 1 1
MISSING_ELSE
133 1 1
134 1 1
140 1 1


Cond Coverage for Module : prim_fifo_sync
TotalCoveredPercent
Conditions141178.57
Logical141178.57
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T8
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T8

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT2,T32,T82
110Not Covered
111CoveredT1,T2,T8

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT34,T35,T36
101CoveredT1,T2,T8
110Not Covered
111CoveredT1,T8,T18

Branch Coverage for Module : prim_fifo_sync
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 69 3 3 100.00
IF 123 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 123 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T1,T2,T8
0 Covered T1,T2,T3


Assert Coverage for Module : prim_fifo_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 399685570 1374038 0 0
DepthKnown_A 400398508 400063672 0 0
RvalidKnown_A 400398508 400063672 0 0
WreadyKnown_A 400398508 400063672 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 400061388 1463307 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 399685570 1374038 0 0
T1 4804 1027 0 0
T2 856 0 0 0
T3 1364 0 0 0
T4 656050 0 0 0
T5 0 87 0 0
T8 6994 4528 0 0
T12 0 8505 0 0
T17 0 3077 0 0
T18 0 611 0 0
T19 21342 0 0 0
T20 388544 0 0 0
T21 796 0 0 0
T22 2630 0 0 0
T23 48828 0 0 0
T29 0 571 0 0
T40 0 3186 0 0
T63 0 11101 0 0
T72 0 1537 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 400398508 400063672 0 0
T1 4804 4698 0 0
T2 4070 3682 0 0
T3 50516 29104 0 0
T4 656050 656020 0 0
T8 6994 6814 0 0
T19 21342 20680 0 0
T20 388544 388520 0 0
T21 2366 2088 0 0
T22 2630 2460 0 0
T23 48828 47310 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 400398508 400063672 0 0
T1 4804 4698 0 0
T2 4070 3682 0 0
T3 50516 29104 0 0
T4 656050 656020 0 0
T8 6994 6814 0 0
T19 21342 20680 0 0
T20 388544 388520 0 0
T21 2366 2088 0 0
T22 2630 2460 0 0
T23 48828 47310 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 400398508 400063672 0 0
T1 4804 4698 0 0
T2 4070 3682 0 0
T3 50516 29104 0 0
T4 656050 656020 0 0
T8 6994 6814 0 0
T19 21342 20680 0 0
T20 388544 388520 0 0
T21 2366 2088 0 0
T22 2630 2460 0 0
T23 48828 47310 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 400061388 1463307 0 0
T1 4804 1027 0 0
T2 4070 24 0 0
T3 1364 0 0 0
T4 656050 0 0 0
T5 0 878 0 0
T8 6994 4528 0 0
T12 0 8505 0 0
T17 0 3077 0 0
T18 0 611 0 0
T19 21342 0 0 0
T20 388544 0 0 0
T21 2366 0 0 0
T22 2630 0 0 0
T23 48828 0 0 0
T29 0 571 0 0
T41 0 268 0 0
T55 0 148 0 0
T63 0 11101 0 0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd
Line No.TotalCoveredPercent
TOTAL1414100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN12011100.00
ALWAYS12322100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN14011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
120 1 1
123 1 1
124 1 1
MISSING_ELSE
133 1 1
134 1 1
140 1 1


Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd
TotalCoveredPercent
Conditions141178.57
Logical141178.57
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT2,T69,T11
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T8

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT2,T32,T82
110Not Covered
111CoveredT1,T2,T8

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT35,T36,T83
101CoveredT1,T2,T8
110Not Covered
111CoveredT1,T8,T12

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 69 3 3 100.00
IF 123 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 123 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T1,T2,T8
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 199842785 681925 0 0
DepthKnown_A 200199254 200031836 0 0
RvalidKnown_A 200199254 200031836 0 0
WreadyKnown_A 200199254 200031836 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 200030694 726612 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 199842785 681925 0 0
T1 2402 508 0 0
T2 428 0 0 0
T3 682 0 0 0
T4 328025 0 0 0
T5 0 35 0 0
T8 3497 2204 0 0
T12 0 4241 0 0
T17 0 1495 0 0
T18 0 318 0 0
T19 10671 0 0 0
T20 194272 0 0 0
T21 398 0 0 0
T22 1315 0 0 0
T23 24414 0 0 0
T29 0 289 0 0
T40 0 1573 0 0
T63 0 5478 0 0
T72 0 754 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 200199254 200031836 0 0
T1 2402 2349 0 0
T2 2035 1841 0 0
T3 25258 14552 0 0
T4 328025 328010 0 0
T8 3497 3407 0 0
T19 10671 10340 0 0
T20 194272 194260 0 0
T21 1183 1044 0 0
T22 1315 1230 0 0
T23 24414 23655 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 200199254 200031836 0 0
T1 2402 2349 0 0
T2 2035 1841 0 0
T3 25258 14552 0 0
T4 328025 328010 0 0
T8 3497 3407 0 0
T19 10671 10340 0 0
T20 194272 194260 0 0
T21 1183 1044 0 0
T22 1315 1230 0 0
T23 24414 23655 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 200199254 200031836 0 0
T1 2402 2349 0 0
T2 2035 1841 0 0
T3 25258 14552 0 0
T4 328025 328010 0 0
T8 3497 3407 0 0
T19 10671 10340 0 0
T20 194272 194260 0 0
T21 1183 1044 0 0
T22 1315 1230 0 0
T23 24414 23655 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 200030694 726612 0 0
T1 2402 508 0 0
T2 2035 24 0 0
T3 682 0 0 0
T4 328025 0 0 0
T5 0 430 0 0
T8 3497 2204 0 0
T12 0 4241 0 0
T17 0 1495 0 0
T18 0 318 0 0
T19 10671 0 0 0
T20 194272 0 0 0
T21 1183 0 0 0
T22 1315 0 0 0
T23 24414 0 0 0
T29 0 289 0 0
T41 0 138 0 0
T63 0 5478 0 0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd
Line No.TotalCoveredPercent
TOTAL1414100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN12011100.00
ALWAYS12322100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN14011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
120 1 1
123 1 1
124 1 1
MISSING_ELSE
133 1 1
134 1 1
140 1 1


Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd
TotalCoveredPercent
Conditions141178.57
Logical141178.57
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T8,T5
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T8,T5

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT84
110Not Covered
111CoveredT1,T8,T5

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT34,T85,T86
101CoveredT1,T8,T5
110Not Covered
111CoveredT1,T8,T18

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 69 3 3 100.00
IF 123 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 123 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T1,T8,T5
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 199842785 692113 0 0
DepthKnown_A 200199254 200031836 0 0
RvalidKnown_A 200199254 200031836 0 0
WreadyKnown_A 200199254 200031836 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 200030694 736695 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 199842785 692113 0 0
T1 2402 519 0 0
T2 428 0 0 0
T3 682 0 0 0
T4 328025 0 0 0
T5 0 52 0 0
T8 3497 2324 0 0
T12 0 4264 0 0
T17 0 1582 0 0
T18 0 293 0 0
T19 10671 0 0 0
T20 194272 0 0 0
T21 398 0 0 0
T22 1315 0 0 0
T23 24414 0 0 0
T29 0 282 0 0
T40 0 1613 0 0
T63 0 5623 0 0
T72 0 783 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 200199254 200031836 0 0
T1 2402 2349 0 0
T2 2035 1841 0 0
T3 25258 14552 0 0
T4 328025 328010 0 0
T8 3497 3407 0 0
T19 10671 10340 0 0
T20 194272 194260 0 0
T21 1183 1044 0 0
T22 1315 1230 0 0
T23 24414 23655 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 200199254 200031836 0 0
T1 2402 2349 0 0
T2 2035 1841 0 0
T3 25258 14552 0 0
T4 328025 328010 0 0
T8 3497 3407 0 0
T19 10671 10340 0 0
T20 194272 194260 0 0
T21 1183 1044 0 0
T22 1315 1230 0 0
T23 24414 23655 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 200199254 200031836 0 0
T1 2402 2349 0 0
T2 2035 1841 0 0
T3 25258 14552 0 0
T4 328025 328010 0 0
T8 3497 3407 0 0
T19 10671 10340 0 0
T20 194272 194260 0 0
T21 1183 1044 0 0
T22 1315 1230 0 0
T23 24414 23655 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 200030694 736695 0 0
T1 2402 519 0 0
T2 2035 0 0 0
T3 682 0 0 0
T4 328025 0 0 0
T5 0 448 0 0
T8 3497 2324 0 0
T12 0 4264 0 0
T17 0 1582 0 0
T18 0 293 0 0
T19 10671 0 0 0
T20 194272 0 0 0
T21 1183 0 0 0
T22 1315 0 0 0
T23 24414 0 0 0
T29 0 282 0 0
T41 0 130 0 0
T55 0 148 0 0
T63 0 5623 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%