Unified Coverage Report :: Module :: edn

Module : edn

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	94.44		83.33	100.00			100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.40	98.25	93.97	97.02	93.02	96.37	99.77

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
edn_csr_assert	100.00						100.00
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_edn_core	94.32	99.92	92.75	82.54	93.02	98.83	98.88
u_edn_cov_if	25.00	50.00	0.00
u_reg	96.95	95.02	97.57	100.00		92.16	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Cond Coverage for Module : edn

	Total	Covered	Percent
Conditions	6	5	83.33
Logical	6	5	83.33
Non-Logical	0	0
Event	0	0

 LINE       98
 EXPRESSION (alert[0] || intg_err_alert[0])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T28,T29

 LINE       98
 EXPRESSION (alert[1] || intg_err_alert[1])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T15
1	0	Covered	T4,T5,T8

---

Toggle Coverage for Module : edn

	Total	Covered	Percent
Totals	69	69	100.00
Total Bits	1172	1172	100.00
Total Bits 0->1	586	586	100.00
Total Bits 1->0	586	586	100.00

Ports	69	69	100.00
Port Bits	1172	1172	100.00
Port Bits 0->1	586	586	100.00
Port Bits 1->0	586	586	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T4,T5,T6	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T7,T19	Yes	T1,T7,T19	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T7	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T7	Yes	T1,T2,T7	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T6,T38,T39	Yes	T6,T38,T39	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T7	Yes	T1,T2,T7	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T3,T19	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T7	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i[0].edn_req	Yes	Yes	T2,T7,T19	Yes	T2,T7,T19	INPUT
edn_i[1].edn_req	Yes	Yes	T7,T23,T40	Yes	T7,T23,T40	INPUT
edn_i[2].edn_req	Yes	Yes	T1,T7,T20	Yes	T1,T7,T20	INPUT
edn_i[3].edn_req	Yes	Yes	T20,T40,T16	Yes	T20,T40,T16	INPUT
edn_i[4].edn_req	Yes	Yes	T1,T7,T20	Yes	T1,T7,T20	INPUT
edn_i[5].edn_req	Yes	Yes	T7,T41,T17	Yes	T7,T41,T17	INPUT
edn_i[6].edn_req	Yes	Yes	T7,T29,T16	Yes	T7,T29,T16	INPUT
edn_o[0].edn_bus[31:0]	Yes	Yes	T2,T7,T19	Yes	T2,T7,T19	OUTPUT
edn_o[0].edn_fips	Yes	Yes	T2,T7,T24	Yes	T2,T7,T19	OUTPUT
edn_o[0].edn_ack	Yes	Yes	T2,T7,T19	Yes	T2,T7,T19	OUTPUT
edn_o[1].edn_bus[31:0]	Yes	Yes	T7,T23,T40	Yes	T7,T23,T40	OUTPUT
edn_o[1].edn_fips	Yes	Yes	T40,T16,T42	Yes	T40,T16,T43	OUTPUT
edn_o[1].edn_ack	Yes	Yes	T7,T23,T40	Yes	T7,T23,T40	OUTPUT
edn_o[2].edn_bus[31:0]	Yes	Yes	T1,T7,T20	Yes	T1,T7,T20	OUTPUT
edn_o[2].edn_fips	Yes	Yes	T1,T7,T44	Yes	T1,T7,T40	OUTPUT
edn_o[2].edn_ack	Yes	Yes	T1,T7,T20	Yes	T1,T7,T20	OUTPUT
edn_o[3].edn_bus[31:0]	Yes	Yes	T20,T40,T16	Yes	T20,T40,T16	OUTPUT
edn_o[3].edn_fips	Yes	Yes	T20,T16,T44	Yes	T20,T40,T16	OUTPUT
edn_o[3].edn_ack	Yes	Yes	T20,T40,T16	Yes	T20,T40,T16	OUTPUT
edn_o[4].edn_bus[31:0]	Yes	Yes	T1,T7,T20	Yes	T1,T7,T20	OUTPUT
edn_o[4].edn_fips	Yes	Yes	T7,T20,T45	Yes	T7,T20,T45	OUTPUT
edn_o[4].edn_ack	Yes	Yes	T1,T7,T20	Yes	T1,T7,T20	OUTPUT
edn_o[5].edn_bus[31:0]	Yes	Yes	T41,T17,T42	Yes	T7,T41,T17	OUTPUT
edn_o[5].edn_fips	Yes	Yes	T17,T42,T46	Yes	T41,T17,T42	OUTPUT
edn_o[5].edn_ack	Yes	Yes	T7,T41,T17	Yes	T7,T41,T17	OUTPUT
edn_o[6].edn_bus[31:0]	Yes	Yes	T7,T29,T16	Yes	T7,T29,T16	OUTPUT
edn_o[6].edn_fips	Yes	Yes	T29,T47,T48	Yes	T7,T29,T43	OUTPUT
edn_o[6].edn_ack	Yes	Yes	T7,T29,T16	Yes	T7,T29,T16	OUTPUT
csrng_cmd_o.genbits_ready	Yes	Yes	T1,T2,T7	Yes	T1,T2,T7	OUTPUT
csrng_cmd_o.csrng_req_bus[31:0]	Yes	Yes	T1,T2,T7	Yes	T1,T2,T7	OUTPUT
csrng_cmd_o.csrng_req_valid	Yes	Yes	T1,T2,T7	Yes	T1,T2,T7	OUTPUT
csrng_cmd_i.genbits_bus[127:0]	Yes	Yes	T1,T2,T7	Yes	T2,T7,T20	INPUT
csrng_cmd_i.genbits_fips	Yes	Yes	T1,T2,T7	Yes	T2,T7,T20	INPUT
csrng_cmd_i.genbits_valid	Yes	Yes	T1,T2,T7	Yes	T1,T2,T7	INPUT
csrng_cmd_i.csrng_rsp_sts[2:0]	Yes	Yes	T1,T49,T50	Yes	T1,T49,T50	INPUT
csrng_cmd_i.csrng_rsp_ack	Yes	Yes	T1,T2,T7	Yes	T1,T2,T7	INPUT
csrng_cmd_i.csrng_req_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T1,T3,T21	Yes	T1,T3,T21	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T3,T21,T4	Yes	T3,T21,T4	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T1,T3,T21	Yes	T1,T3,T21	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T3,T21,T4	Yes	T3,T21,T4	OUTPUT
intr_edn_cmd_req_done_o	Yes	Yes	T6,T38,T39	Yes	T6,T38,T39	OUTPUT
intr_edn_fatal_err_o	Yes	Yes	T6,T38,T39	Yes	T6,T38,T39	OUTPUT

*Tests covering at least one bit in the range

---

Assert Coverage for Module : edn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	47	47	100.00	47	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	47	47	100.00	47	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxKnownO_A	189697645	189485357	0	0
CsrngAppIfOut_A	189697645	189485357	0	0
FpvSecCmCntAlertCheck_A	189697645	148	0	0
FpvSecCmGenCmdFifoRptrCheck_A	189697645	100	0	0
FpvSecCmGenCmdFifoWptrCheck_A	189697645	100	0	0
FpvSecCmMainFsmCheck_A	189697645	100	0	0
FpvSecCmRegWeOnehotCheck_A	189697645	100	0	0
FpvSecCmResCmdFifoRptrCheck_A	189697645	100	0	0
FpvSecCmResCmdFifoWptrCheck_A	189697645	100	0	0
IntrEdnCmdReqDoneKnownO_A	189697645	189485357	0	0
TlAReadyKnownO_A	189697645	189485357	0	0
TlDValidKnownO_A	189697645	189485357	0	0
gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A	189697645	100	0	0
gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A	189697645	100	0	0
gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A	189697645	100	0	0
gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A	189697645	100	0	0
gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A	189697645	100	0	0
gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A	189697645	100	0	0
gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A	189697645	100	0	0
gen_edn_if_asserts[0].EdnDataStableDisable_A	189697645	644592	0	318
gen_edn_if_asserts[0].EdnDataStable_A	189697645	73868	0	409
gen_edn_if_asserts[0].EdnEndPointOut_A	189697645	189485357	0	0
gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A	189697645	180102	0	0
gen_edn_if_asserts[1].EdnDataStableDisable_A	189697645	644592	0	318
gen_edn_if_asserts[1].EdnDataStable_A	189697645	10462	0	145
gen_edn_if_asserts[1].EdnEndPointOut_A	189697645	189485357	0	0
gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A	189697645	180102	0	0
gen_edn_if_asserts[2].EdnDataStableDisable_A	189697645	644592	0	318
gen_edn_if_asserts[2].EdnDataStable_A	189697645	6034	0	112
gen_edn_if_asserts[2].EdnEndPointOut_A	189697645	189485357	0	0
gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A	189697645	180102	0	0
gen_edn_if_asserts[3].EdnDataStableDisable_A	189697645	644592	0	318
gen_edn_if_asserts[3].EdnDataStable_A	189697645	3678	0	98
gen_edn_if_asserts[3].EdnEndPointOut_A	189697645	189485357	0	0
gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A	189697645	180102	0	0
gen_edn_if_asserts[4].EdnDataStableDisable_A	189697645	644592	0	318
gen_edn_if_asserts[4].EdnDataStable_A	189697645	1720	0	93
gen_edn_if_asserts[4].EdnEndPointOut_A	189697645	189485357	0	0
gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A	189697645	180102	0	0
gen_edn_if_asserts[5].EdnDataStableDisable_A	189697645	644592	0	318
gen_edn_if_asserts[5].EdnDataStable_A	189697645	5172	0	82
gen_edn_if_asserts[5].EdnEndPointOut_A	189697645	189485357	0	0
gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A	189697645	180102	0	0
gen_edn_if_asserts[6].EdnDataStableDisable_A	189697645	644592	0	318
gen_edn_if_asserts[6].EdnDataStable_A	189697645	2940	0	75
gen_edn_if_asserts[6].EdnEndPointOut_A	189697645	189485357	0	0
gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A	189697645	180102	0	0

AlertTxKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	189697645	189485357	0	0
T1	2722	2642	0	0
T2	1981	1903	0	0
T3	1180	1105	0	0
T7	2859	2786	0	0
T19	3199	3103	0	0
T20	4127	4050	0	0
T21	757	687	0	0
T22	1347	1270	0	0
T23	2412	2359	0	0
T24	2019	1940	0	0

CsrngAppIfOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	189697645	189485357	0	0
T1	2722	2642	0	0
T2	1981	1903	0	0
T3	1180	1105	0	0
T7	2859	2786	0	0
T19	3199	3103	0	0
T20	4127	4050	0	0
T21	757	687	0	0
T22	1347	1270	0	0
T23	2412	2359	0	0
T24	2019	1940	0	0

FpvSecCmCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	189697645	148	0	0
T5	2545	1	0	0
T6	402687	0	0	0
T8	0	1	0	0
T12	0	1	0	0
T16	8336	0	0	0
T25	885	0	0	0
T38	266467	0	0	0
T40	3099	0	0	0
T45	1143	0	0	0
T49	1526	0	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	2802	0	0	0
T59	1502	0	0	0

FpvSecCmGenCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	189697645	100	0	0
T13	47419	20	0	0
T14	0	20	0	0
T15	0	20	0	0
T60	0	20	0	0
T61	0	20	0	0
T62	3700	0	0	0
T63	1750	0	0	0
T64	1504	0	0	0
T65	8088	0	0	0
T66	566597	0	0	0
T67	8575	0	0	0
T68	1529	0	0	0
T69	926	0	0	0
T70	914477	0	0	0

FpvSecCmGenCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	189697645	100	0	0
T13	47419	20	0	0
T14	0	20	0	0
T15	0	20	0	0
T60	0	20	0	0
T61	0	20	0	0
T62	3700	0	0	0
T63	1750	0	0	0
T64	1504	0	0	0
T65	8088	0	0	0
T66	566597	0	0	0
T67	8575	0	0	0
T68	1529	0	0	0
T69	926	0	0	0
T70	914477	0	0	0

FpvSecCmMainFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	189697645	100	0	0
T13	47419	20	0	0
T14	0	20	0	0
T15	0	20	0	0
T60	0	20	0	0
T61	0	20	0	0
T62	3700	0	0	0
T63	1750	0	0	0
T64	1504	0	0	0
T65	8088	0	0	0
T66	566597	0	0	0
T67	8575	0	0	0
T68	1529	0	0	0
T69	926	0	0	0
T70	914477	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	189697645	100	0	0
T13	47419	20	0	0
T14	0	20	0	0
T15	0	20	0	0
T60	0	20	0	0
T61	0	20	0	0
T62	3700	0	0	0
T63	1750	0	0	0
T64	1504	0	0	0
T65	8088	0	0	0
T66	566597	0	0	0
T67	8575	0	0	0
T68	1529	0	0	0
T69	926	0	0	0
T70	914477	0	0	0

FpvSecCmResCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	189697645	100	0	0
T13	47419	20	0	0
T14	0	20	0	0
T15	0	20	0	0
T60	0	20	0	0
T61	0	20	0	0
T62	3700	0	0	0
T63	1750	0	0	0
T64	1504	0	0	0
T65	8088	0	0	0
T66	566597	0	0	0
T67	8575	0	0	0
T68	1529	0	0	0
T69	926	0	0	0
T70	914477	0	0	0

FpvSecCmResCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	189697645	100	0	0
T13	47419	20	0	0
T14	0	20	0	0
T15	0	20	0	0
T60	0	20	0	0
T61	0	20	0	0
T62	3700	0	0	0
T63	1750	0	0	0
T64	1504	0	0	0
T65	8088	0	0	0
T66	566597	0	0	0
T67	8575	0	0	0
T68	1529	0	0	0
T69	926	0	0	0
T70	914477	0	0	0

IntrEdnCmdReqDoneKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	189697645	189485357	0	0
T1	2722	2642	0	0
T2	1981	1903	0	0
T3	1180	1105	0	0
T7	2859	2786	0	0
T19	3199	3103	0	0
T20	4127	4050	0	0
T21	757	687	0	0
T22	1347	1270	0	0
T23	2412	2359	0	0
T24	2019	1940	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	189697645	189485357	0	0
T1	2722	2642	0	0
T2	1981	1903	0	0
T3	1180	1105	0	0
T7	2859	2786	0	0
T19	3199	3103	0	0
T20	4127	4050	0	0
T21	757	687	0	0
T22	1347	1270	0	0
T23	2412	2359	0	0
T24	2019	1940	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	189697645	189485357	0	0
T1	2722	2642	0	0
T2	1981	1903	0	0
T3	1180	1105	0	0
T7	2859	2786	0	0
T19	3199	3103	0	0
T20	4127	4050	0	0
T21	757	687	0	0
T22	1347	1270	0	0
T23	2412	2359	0	0
T24	2019	1940	0	0

gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	189697645	100	0	0
T13	47419	20	0	0
T14	0	20	0	0
T15	0	20	0	0
T60	0	20	0	0
T61	0	20	0	0
T62	3700	0	0	0
T63	1750	0	0	0
T64	1504	0	0	0
T65	8088	0	0	0
T66	566597	0	0	0
T67	8575	0	0	0
T68	1529	0	0	0
T69	926	0	0	0
T70	914477	0	0	0

gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	189697645	100	0	0
T13	47419	20	0	0
T14	0	20	0	0
T15	0	20	0	0
T60	0	20	0	0
T61	0	20	0	0
T62	3700	0	0	0
T63	1750	0	0	0
T64	1504	0	0	0
T65	8088	0	0	0
T66	566597	0	0	0
T67	8575	0	0	0
T68	1529	0	0	0
T69	926	0	0	0
T70	914477	0	0	0

gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	189697645	100	0	0
T13	47419	20	0	0
T14	0	20	0	0
T15	0	20	0	0
T60	0	20	0	0
T61	0	20	0	0
T62	3700	0	0	0
T63	1750	0	0	0
T64	1504	0	0	0
T65	8088	0	0	0
T66	566597	0	0	0
T67	8575	0	0	0
T68	1529	0	0	0
T69	926	0	0	0
T70	914477	0	0	0

gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	189697645	100	0	0
T13	47419	20	0	0
T14	0	20	0	0
T15	0	20	0	0
T60	0	20	0	0
T61	0	20	0	0
T62	3700	0	0	0
T63	1750	0	0	0
T64	1504	0	0	0
T65	8088	0	0	0
T66	566597	0	0	0
T67	8575	0	0	0
T68	1529	0	0	0
T69	926	0	0	0
T70	914477	0	0	0

gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	189697645	100	0	0
T13	47419	20	0	0
T14	0	20	0	0
T15	0	20	0	0
T60	0	20	0	0
T61	0	20	0	0
T62	3700	0	0	0
T63	1750	0	0	0
T64	1504	0	0	0
T65	8088	0	0	0
T66	566597	0	0	0
T67	8575	0	0	0
T68	1529	0	0	0
T69	926	0	0	0
T70	914477	0	0	0

gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	189697645	100	0	0
T13	47419	20	0	0
T14	0	20	0	0
T15	0	20	0	0
T60	0	20	0	0
T61	0	20	0	0
T62	3700	0	0	0
T63	1750	0	0	0
T64	1504	0	0	0
T65	8088	0	0	0
T66	566597	0	0	0
T67	8575	0	0	0
T68	1529	0	0	0
T69	926	0	0	0
T70	914477	0	0	0

gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	189697645	100	0	0
T13	47419	20	0	0
T14	0	20	0	0
T15	0	20	0	0
T60	0	20	0	0
T61	0	20	0	0
T62	3700	0	0	0
T63	1750	0	0	0
T64	1504	0	0	0
T65	8088	0	0	0
T66	566597	0	0	0
T67	8575	0	0	0
T68	1529	0	0	0
T69	926	0	0	0
T70	914477	0	0	0

gen_edn_if_asserts[0].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	189697645	644592	0	318
T1	2722	205	0	0
T2	1981	217	0	0
T3	1180	1103	0	2
T6	0	0	0	2
T7	2859	261	0	0
T19	3199	65	0	0
T20	4127	95	0	0
T21	757	685	0	2
T22	1347	13	0	0
T23	2412	13	0	0
T24	2019	38	0	0
T38	0	0	0	2
T39	0	0	0	2
T59	0	0	0	2
T71	0	0	0	2
T72	0	0	0	2
T73	0	0	0	2
T74	0	0	0	2

gen_edn_if_asserts[0].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	189697645	73868	0	409
T2	1981	15	0	1
T3	1180	0	0	0
T7	2859	22	0	1
T19	3199	7	0	1
T20	4127	0	0	0
T21	757	0	0	0
T22	1347	3	0	1
T23	2412	0	0	0
T24	2019	19	0	1
T25	0	3	0	1
T28	0	4	0	1
T40	0	55	0	1
T75	2426	3	0	1
T76	0	8	0	1

gen_edn_if_asserts[0].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	189697645	189485357	0	0
T1	2722	2642	0	0
T2	1981	1903	0	0
T3	1180	1105	0	0
T7	2859	2786	0	0
T19	3199	3103	0	0
T20	4127	4050	0	0
T21	757	687	0	0
T22	1347	1270	0	0
T23	2412	2359	0	0
T24	2019	1940	0	0

gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	189697645	180102	0	0
T4	2027	1072	0	0
T5	2545	1149	0	0
T8	0	594	0	0
T12	0	1070	0	0
T16	8336	0	0	0
T25	885	0	0	0
T29	2306	0	0	0
T30	0	7	0	0
T33	0	7	0	0
T34	0	7	0	0
T40	3099	0	0	0
T45	1143	0	0	0
T49	1526	0	0	0
T51	0	433	0	0
T58	2802	0	0	0
T76	2066	0	0	0
T77	0	1116	0	0
T78	0	667	0	0

gen_edn_if_asserts[1].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	189697645	644592	0	318
T1	2722	205	0	0
T2	1981	217	0	0
T3	1180	1103	0	2
T6	0	0	0	2
T7	2859	261	0	0
T19	3199	65	0	0
T20	4127	95	0	0
T21	757	685	0	2
T22	1347	13	0	0
T23	2412	13	0	0
T24	2019	38	0	0
T38	0	0	0	2
T39	0	0	0	2
T59	0	0	0	2
T71	0	0	0	2
T72	0	0	0	2
T73	0	0	0	2
T74	0	0	0	2

gen_edn_if_asserts[1].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	189697645	10462	0	145
T4	2027	0	0	0
T7	2859	3	0	1
T16	0	25	0	1
T19	3199	0	0	0
T20	4127	0	0	0
T21	757	0	0	0
T22	1347	0	0	0
T23	2412	3	0	1
T24	2019	0	0	0
T28	2259	0	0	0
T40	0	18	0	1
T41	0	22	0	1
T43	0	3	0	1
T44	0	3	0	1
T58	0	3	0	1
T75	2426	0	0	0
T79	0	3	0	1
T80	0	4	0	1

gen_edn_if_asserts[1].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	189697645	189485357	0	0
T1	2722	2642	0	0
T2	1981	1903	0	0
T3	1180	1105	0	0
T7	2859	2786	0	0
T19	3199	3103	0	0
T20	4127	4050	0	0
T21	757	687	0	0
T22	1347	1270	0	0
T23	2412	2359	0	0
T24	2019	1940	0	0

gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	189697645	180102	0	0
T4	2027	1072	0	0
T5	2545	1149	0	0
T8	0	594	0	0
T12	0	1070	0	0
T16	8336	0	0	0
T25	885	0	0	0
T29	2306	0	0	0
T30	0	7	0	0
T33	0	7	0	0
T34	0	7	0	0
T40	3099	0	0	0
T45	1143	0	0	0
T49	1526	0	0	0
T51	0	433	0	0
T58	2802	0	0	0
T76	2066	0	0	0
T77	0	1116	0	0
T78	0	667	0	0

gen_edn_if_asserts[2].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	189697645	644592	0	318
T1	2722	205	0	0
T2	1981	217	0	0
T3	1180	1103	0	2
T6	0	0	0	2
T7	2859	261	0	0
T19	3199	65	0	0
T20	4127	95	0	0
T21	757	685	0	2
T22	1347	13	0	0
T23	2412	13	0	0
T24	2019	38	0	0
T38	0	0	0	2
T39	0	0	0	2
T59	0	0	0	2
T71	0	0	0	2
T72	0	0	0	2
T73	0	0	0	2
T74	0	0	0	2

gen_edn_if_asserts[2].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	189697645	6034	0	112
T1	2722	4	0	0
T2	1981	0	0	0
T3	1180	0	0	0
T7	2859	18	0	1
T17	0	3	0	1
T19	3199	0	0	0
T20	4127	3	0	1
T21	757	0	0	0
T22	1347	0	0	0
T23	2412	0	0	0
T24	2019	0	0	0
T40	0	9	0	1
T41	0	3	0	1
T42	0	0	0	1
T43	0	3	0	1
T44	0	6	0	1
T81	0	4	0	0
T82	0	3	0	1
T83	0	0	0	1

gen_edn_if_asserts[2].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	189697645	189485357	0	0
T1	2722	2642	0	0
T2	1981	1903	0	0
T3	1180	1105	0	0
T7	2859	2786	0	0
T19	3199	3103	0	0
T20	4127	4050	0	0
T21	757	687	0	0
T22	1347	1270	0	0
T23	2412	2359	0	0
T24	2019	1940	0	0

gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	189697645	180102	0	0
T4	2027	1072	0	0
T5	2545	1149	0	0
T8	0	594	0	0
T12	0	1070	0	0
T16	8336	0	0	0
T25	885	0	0	0
T29	2306	0	0	0
T30	0	7	0	0
T33	0	7	0	0
T34	0	7	0	0
T40	3099	0	0	0
T45	1143	0	0	0
T49	1526	0	0	0
T51	0	433	0	0
T58	2802	0	0	0
T76	2066	0	0	0
T77	0	1116	0	0
T78	0	667	0	0

gen_edn_if_asserts[3].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	189697645	644592	0	318
T1	2722	205	0	0
T2	1981	217	0	0
T3	1180	1103	0	2
T6	0	0	0	2
T7	2859	261	0	0
T19	3199	65	0	0
T20	4127	95	0	0
T21	757	685	0	2
T22	1347	13	0	0
T23	2412	13	0	0
T24	2019	38	0	0
T38	0	0	0	2
T39	0	0	0	2
T59	0	0	0	2
T71	0	0	0	2
T72	0	0	0	2
T73	0	0	0	2
T74	0	0	0	2

gen_edn_if_asserts[3].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	189697645	3678	0	98
T4	2027	0	0	0
T16	0	1236	0	1
T20	4127	19	0	1
T21	757	0	0	0
T22	1347	0	0	0
T23	2412	0	0	0
T24	2019	0	0	0
T28	2259	0	0	0
T29	2306	0	0	0
T40	0	15	0	1
T41	0	20	0	1
T43	0	3	0	1
T44	0	35	0	1
T75	2426	0	0	0
T76	2066	0	0	0
T81	0	4	0	1
T84	0	3	0	1
T85	0	4	0	1
T86	0	4	0	1

gen_edn_if_asserts[3].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	189697645	189485357	0	0
T1	2722	2642	0	0
T2	1981	1903	0	0
T3	1180	1105	0	0
T7	2859	2786	0	0
T19	3199	3103	0	0
T20	4127	4050	0	0
T21	757	687	0	0
T22	1347	1270	0	0
T23	2412	2359	0	0
T24	2019	1940	0	0

gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	189697645	180102	0	0
T4	2027	1072	0	0
T5	2545	1149	0	0
T8	0	594	0	0
T12	0	1070	0	0
T16	8336	0	0	0
T25	885	0	0	0
T29	2306	0	0	0
T30	0	7	0	0
T33	0	7	0	0
T34	0	7	0	0
T40	3099	0	0	0
T45	1143	0	0	0
T49	1526	0	0	0
T51	0	433	0	0
T58	2802	0	0	0
T76	2066	0	0	0
T77	0	1116	0	0
T78	0	667	0	0

gen_edn_if_asserts[4].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	189697645	644592	0	318
T1	2722	205	0	0
T2	1981	217	0	0
T3	1180	1103	0	2
T6	0	0	0	2
T7	2859	261	0	0
T19	3199	65	0	0
T20	4127	95	0	0
T21	757	685	0	2
T22	1347	13	0	0
T23	2412	13	0	0
T24	2019	38	0	0
T38	0	0	0	2
T39	0	0	0	2
T59	0	0	0	2
T71	0	0	0	2
T72	0	0	0	2
T73	0	0	0	2
T74	0	0	0	2

gen_edn_if_asserts[4].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	189697645	1720	0	93
T1	2722	4	0	1
T2	1981	0	0	0
T3	1180	0	0	0
T5	0	1	0	0
T7	2859	38	0	1
T19	3199	0	0	0
T20	4127	61	0	1
T21	757	0	0	0
T22	1347	0	0	0
T23	2412	0	0	0
T24	2019	0	0	0
T41	0	11	0	1
T42	0	3	0	1
T45	0	4	0	0
T48	0	0	0	1
T87	0	4	0	1
T88	0	8	0	1
T89	0	3	0	1
T90	0	0	0	1

gen_edn_if_asserts[4].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	189697645	189485357	0	0
T1	2722	2642	0	0
T2	1981	1903	0	0
T3	1180	1105	0	0
T7	2859	2786	0	0
T19	3199	3103	0	0
T20	4127	4050	0	0
T21	757	687	0	0
T22	1347	1270	0	0
T23	2412	2359	0	0
T24	2019	1940	0	0

gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	189697645	180102	0	0
T4	2027	1072	0	0
T5	2545	1149	0	0
T8	0	594	0	0
T12	0	1070	0	0
T16	8336	0	0	0
T25	885	0	0	0
T29	2306	0	0	0
T30	0	7	0	0
T33	0	7	0	0
T34	0	7	0	0
T40	3099	0	0	0
T45	1143	0	0	0
T49	1526	0	0	0
T51	0	433	0	0
T58	2802	0	0	0
T76	2066	0	0	0
T77	0	1116	0	0
T78	0	667	0	0

gen_edn_if_asserts[5].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	189697645	644592	0	318
T1	2722	205	0	0
T2	1981	217	0	0
T3	1180	1103	0	2
T6	0	0	0	2
T7	2859	261	0	0
T19	3199	65	0	0
T20	4127	95	0	0
T21	757	685	0	2
T22	1347	13	0	0
T23	2412	13	0	0
T24	2019	38	0	0
T38	0	0	0	2
T39	0	0	0	2
T59	0	0	0	2
T71	0	0	0	2
T72	0	0	0	2
T73	0	0	0	2
T74	0	0	0	2

gen_edn_if_asserts[5].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	189697645	5172	0	82
T4	2027	0	0	0
T7	2859	3	0	1
T17	0	1093	0	1
T19	3199	0	0	0
T20	4127	0	0	0
T21	757	0	0	0
T22	1347	0	0	0
T23	2412	0	0	0
T24	2019	0	0	0
T28	2259	0	0	0
T41	0	3	0	1
T42	0	26	0	1
T46	0	161	0	1
T47	0	3	0	1
T57	0	1	0	0
T62	0	0	0	1
T75	2426	0	0	0
T91	0	3	0	1
T92	0	5	0	1
T93	0	755	0	1

gen_edn_if_asserts[5].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	189697645	189485357	0	0
T1	2722	2642	0	0
T2	1981	1903	0	0
T3	1180	1105	0	0
T7	2859	2786	0	0
T19	3199	3103	0	0
T20	4127	4050	0	0
T21	757	687	0	0
T22	1347	1270	0	0
T23	2412	2359	0	0
T24	2019	1940	0	0

gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	189697645	180102	0	0
T4	2027	1072	0	0
T5	2545	1149	0	0
T8	0	594	0	0
T12	0	1070	0	0
T16	8336	0	0	0
T25	885	0	0	0
T29	2306	0	0	0
T30	0	7	0	0
T33	0	7	0	0
T34	0	7	0	0
T40	3099	0	0	0
T45	1143	0	0	0
T49	1526	0	0	0
T51	0	433	0	0
T58	2802	0	0	0
T76	2066	0	0	0
T77	0	1116	0	0
T78	0	667	0	0

gen_edn_if_asserts[6].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	189697645	644592	0	318
T1	2722	205	0	0
T2	1981	217	0	0
T3	1180	1103	0	2
T6	0	0	0	2
T7	2859	261	0	0
T19	3199	65	0	0
T20	4127	95	0	0
T21	757	685	0	2
T22	1347	13	0	0
T23	2412	13	0	0
T24	2019	38	0	0
T38	0	0	0	2
T39	0	0	0	2
T59	0	0	0	2
T71	0	0	0	2
T72	0	0	0	2
T73	0	0	0	2
T74	0	0	0	2

gen_edn_if_asserts[6].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	189697645	2940	0	75
T4	2027	0	0	0
T7	2859	15	0	1
T16	0	3	0	1
T19	3199	0	0	0
T20	4127	0	0	0
T21	757	0	0	0
T22	1347	0	0	0
T23	2412	0	0	0
T24	2019	0	0	0
T28	2259	0	0	0
T29	0	8	0	1
T41	0	3	0	1
T42	0	3	0	1
T43	0	3	0	1
T75	2426	0	0	0
T89	0	0	0	1
T94	0	3	0	1
T95	0	4	0	1
T96	0	3	0	1
T97	0	4	0	0

gen_edn_if_asserts[6].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	189697645	189485357	0	0
T1	2722	2642	0	0
T2	1981	1903	0	0
T3	1180	1105	0	0
T7	2859	2786	0	0
T19	3199	3103	0	0
T20	4127	4050	0	0
T21	757	687	0	0
T22	1347	1270	0	0
T23	2412	2359	0	0
T24	2019	1940	0	0

gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	189697645	180102	0	0
T4	2027	1072	0	0
T5	2545	1149	0	0
T8	0	594	0	0
T12	0	1070	0	0
T16	8336	0	0	0
T25	885	0	0	0
T29	2306	0	0	0
T30	0	7	0	0
T33	0	7	0	0
T34	0	7	0	0
T40	3099	0	0	0
T45	1143	0	0	0
T49	1526	0	0	0
T51	0	433	0	0
T58	2802	0	0	0
T76	2066	0	0	0
T77	0	1116	0	0
T78	0	667	0	0