Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44		83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	190221597	8469846	0	0
boot_gen_cmd_rd_A	190221597	43038	0	0
boot_ins_cmd_rd_A	190221597	48040	0	0
ctrl_rd_A	190221597	41762	0	0
err_code_test_rd_A	190221597	48055	0	0
intr_enable_rd_A	190221597	47902	0	0
max_num_reqs_between_reseeds_rd_A	190221597	42217	0	0
regwen_rd_A	190221597	47002	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	190221597	8469846	0	0
T6	402687	163411	0	0
T38	266467	100261	0	0
T39	930481	387986	0	0
T43	3797	0	0	0
T50	2114	0	0	0
T59	1502	0	0	0
T71	0	48151	0	0
T79	1753	0	0	0
T101	4464	0	0	0
T106	4229	0	0	0
T107	5185	0	0	0
T109	0	29963	0	0
T230	0	116229	0	0
T231	0	193477	0	0
T232	0	110615	0	0
T233	0	159465	0	0
T234	0	82975	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	190221597	43038	0	0
T38	266467	1448	0	0
T39	930481	0	0	0
T43	3797	0	0	0
T50	2114	0	0	0
T59	1502	0	0	0
T71	137873	1273	0	0
T79	1753	0	0	0
T101	4464	0	0	0
T106	4229	0	0	0
T107	5185	0	0	0
T231	0	5493	0	0
T233	0	2463	0	0
T235	0	4191	0	0
T236	0	6273	0	0
T237	0	2203	0	0
T238	0	2376	0	0
T239	0	5621	0	0
T240	0	4094	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	190221597	48040	0	0
T38	266467	1814	0	0
T39	930481	0	0	0
T43	3797	0	0	0
T50	2114	0	0	0
T59	1502	0	0	0
T71	137873	1672	0	0
T79	1753	0	0	0
T101	4464	0	0	0
T106	4229	0	0	0
T107	5185	0	0	0
T231	0	6144	0	0
T233	0	2741	0	0
T235	0	4896	0	0
T236	0	6973	0	0
T237	0	2331	0	0
T238	0	2838	0	0
T239	0	5890	0	0
T240	0	4599	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	190221597	41762	0	0
T26	0	4	0	0
T38	266467	1549	0	0
T39	930481	0	0	0
T43	3797	0	0	0
T50	2114	0	0	0
T59	1502	0	0	0
T71	137873	1291	0	0
T79	1753	0	0	0
T101	4464	0	0	0
T106	4229	0	0	0
T107	5185	0	0	0
T171	0	1	0	0
T231	0	5104	0	0
T233	0	2417	0	0
T235	0	4085	0	0
T241	0	7	0	0
T242	0	5	0	0
T243	0	2	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	190221597	48055	0	0
T38	266467	1979	0	0
T39	930481	0	0	0
T43	3797	0	0	0
T50	2114	0	0	0
T59	1502	0	0	0
T71	137873	1519	0	0
T79	1753	0	0	0
T101	4464	0	0	0
T106	4229	0	0	0
T107	5185	0	0	0
T231	0	5864	0	0
T233	0	2891	0	0
T235	0	4661	0	0
T236	0	7155	0	0
T237	0	2308	0	0
T238	0	2766	0	0
T239	0	6117	0	0
T240	0	4385	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	190221597	47902	0	0
T38	266467	1711	0	0
T39	930481	0	0	0
T43	3797	0	0	0
T50	2114	0	0	0
T59	1502	0	0	0
T71	137873	1524	0	0
T79	1753	0	0	0
T101	4464	0	0	0
T106	4229	0	0	0
T107	5185	0	0	0
T231	0	5491	0	0
T233	0	2651	0	0
T235	0	4541	0	0
T236	0	6506	0	0
T237	0	2459	0	0
T238	0	2344	0	0
T241	0	81	0	0
T244	0	49	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	190221597	42217	0	0
T38	266467	1540	0	0
T39	930481	0	0	0
T43	3797	0	0	0
T50	2114	0	0	0
T59	1502	0	0	0
T71	137873	1390	0	0
T79	1753	0	0	0
T101	4464	0	0	0
T106	4229	0	0	0
T107	5185	0	0	0
T231	0	5440	0	0
T233	0	2370	0	0
T235	0	3972	0	0
T236	0	6156	0	0
T237	0	1873	0	0
T238	0	2262	0	0
T239	0	5217	0	0
T240	0	4166	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	190221597	47002	0	0
T38	266467	1870	0	0
T39	930481	0	0	0
T43	3797	0	0	0
T50	2114	0	0	0
T59	1502	0	0	0
T71	137873	1470	0	0
T79	1753	0	0	0
T101	4464	0	0	0
T106	4229	0	0	0
T107	5185	0	0	0
T231	0	5934	0	0
T233	0	2679	0	0
T235	0	4389	0	0
T236	0	6990	0	0
T237	0	2237	0	0
T238	0	2380	0	0
T239	0	5834	0	0
T240	0	4359	0	0