Unified Coverage Report :: Module :: edn

Module : edn

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	94.44		83.33	100.00			100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.39	98.25	93.91	97.02	93.02	96.37	99.77

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
edn_csr_assert	100.00						100.00
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_edn_core	94.31	99.92	92.66	82.54	93.02	98.83	98.88
u_edn_cov_if	25.00	50.00	0.00
u_reg	96.95	95.02	97.57	100.00		92.16	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Cond Coverage for Module : edn

	Total	Covered	Percent
Conditions	6	5	83.33
Logical	6	5	83.33
Non-Logical	0	0
Event	0	0

 LINE       98
 EXPRESSION (alert[0] || intg_err_alert[0])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T3,T25,T11

 LINE       98
 EXPRESSION (alert[1] || intg_err_alert[1])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T17,T18,T19
1	0	Covered	T5,T15,T16

---

Toggle Coverage for Module : edn

	Total	Covered	Percent
Totals	69	69	100.00
Total Bits	1172	1172	100.00
Total Bits 0->1	586	586	100.00
Total Bits 1->0	586	586	100.00

Ports	69	69	100.00
Port Bits	1172	1172	100.00
Port Bits 0->1	586	586	100.00
Port Bits 1->0	586	586	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T4,T5,T6	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T25,T28,T4	Yes	T25,T28,T4	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T2,T3,T25	Yes	T2,T3,T25	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T4,T40,T41	Yes	T4,T40,T41	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i[0].edn_req	Yes	Yes	T1,T2,T10	Yes	T1,T2,T10	INPUT
edn_i[1].edn_req	Yes	Yes	T2,T10,T26	Yes	T2,T10,T26	INPUT
edn_i[2].edn_req	Yes	Yes	T2,T11,T26	Yes	T2,T11,T26	INPUT
edn_i[3].edn_req	Yes	Yes	T2,T10,T42	Yes	T2,T10,T42	INPUT
edn_i[4].edn_req	Yes	Yes	T2,T25,T10	Yes	T2,T25,T10	INPUT
edn_i[5].edn_req	Yes	Yes	T2,T10,T43	Yes	T2,T10,T43	INPUT
edn_i[6].edn_req	Yes	Yes	T2,T3,T10	Yes	T2,T3,T10	INPUT
edn_o[0].edn_bus[31:0]	Yes	Yes	T1,T2,T26	Yes	T1,T2,T10	OUTPUT
edn_o[0].edn_fips	Yes	Yes	T4,T6,T43	Yes	T1,T2,T10	OUTPUT
edn_o[0].edn_ack	Yes	Yes	T1,T2,T10	Yes	T1,T2,T10	OUTPUT
edn_o[1].edn_bus[31:0]	Yes	Yes	T2,T26,T44	Yes	T2,T10,T26	OUTPUT
edn_o[1].edn_fips	Yes	Yes	T44,T45,T46	Yes	T10,T26,T44	OUTPUT
edn_o[1].edn_ack	Yes	Yes	T2,T10,T26	Yes	T2,T10,T26	OUTPUT
edn_o[2].edn_bus[31:0]	Yes	Yes	T2,T11,T26	Yes	T2,T11,T26	OUTPUT
edn_o[2].edn_fips	Yes	Yes	T2,T26,T42	Yes	T2,T26,T33	OUTPUT
edn_o[2].edn_ack	Yes	Yes	T2,T11,T26	Yes	T2,T11,T26	OUTPUT
edn_o[3].edn_bus[31:0]	Yes	Yes	T2,T42,T44	Yes	T2,T10,T42	OUTPUT
edn_o[3].edn_fips	Yes	Yes	T44,T43,T47	Yes	T2,T44,T43	OUTPUT
edn_o[3].edn_ack	Yes	Yes	T2,T10,T42	Yes	T2,T10,T42	OUTPUT
edn_o[4].edn_bus[31:0]	Yes	Yes	T25,T10,T26	Yes	T2,T25,T10	OUTPUT
edn_o[4].edn_fips	Yes	Yes	T10,T26,T28	Yes	T10,T26,T28	OUTPUT
edn_o[4].edn_ack	Yes	Yes	T2,T25,T10	Yes	T2,T25,T10	OUTPUT
edn_o[5].edn_bus[31:0]	Yes	Yes	T2,T43,T45	Yes	T2,T10,T43	OUTPUT
edn_o[5].edn_fips	Yes	Yes	T2,T43,T22	Yes	T2,T43,T45	OUTPUT
edn_o[5].edn_ack	Yes	Yes	T2,T10,T43	Yes	T2,T10,T43	OUTPUT
edn_o[6].edn_bus[31:0]	Yes	Yes	T2,T3,T10	Yes	T2,T3,T10	OUTPUT
edn_o[6].edn_fips	Yes	Yes	T10,T43,T15	Yes	T3,T10,T11	OUTPUT
edn_o[6].edn_ack	Yes	Yes	T2,T3,T10	Yes	T2,T3,T10	OUTPUT
csrng_cmd_o.genbits_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_bus[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_i.genbits_bus[127:0]	Yes	Yes	T2,T10,T11	Yes	T1,T2,T25	INPUT
csrng_cmd_i.genbits_fips	Yes	Yes	T1,T2,T10	Yes	T1,T2,T10	INPUT
csrng_cmd_i.genbits_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_rsp_sts[2:0]	Yes	Yes	T3,T11,T48	Yes	T3,T11,T48	INPUT
csrng_cmd_i.csrng_rsp_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_req_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T3,T25,T11	Yes	T3,T25,T11	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T49,T5,T15	Yes	T49,T5,T15	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T3,T25,T11	Yes	T3,T25,T11	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T49,T5,T15	Yes	T49,T5,T15	OUTPUT
intr_edn_cmd_req_done_o	Yes	Yes	T4,T6,T40	Yes	T4,T6,T40	OUTPUT
intr_edn_fatal_err_o	Yes	Yes	T4,T6,T15	Yes	T4,T6,T15	OUTPUT

*Tests covering at least one bit in the range

---

Assert Coverage for Module : edn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	47	47	100.00	47	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	47	47	100.00	47	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxKnownO_A	233790812	233624410	0	0
CsrngAppIfOut_A	233790812	233624410	0	0
FpvSecCmCntAlertCheck_A	233790812	109	0	0
FpvSecCmGenCmdFifoRptrCheck_A	233790812	60	0	0
FpvSecCmGenCmdFifoWptrCheck_A	233790812	60	0	0
FpvSecCmMainFsmCheck_A	233790812	60	0	0
FpvSecCmRegWeOnehotCheck_A	233790812	60	0	0
FpvSecCmResCmdFifoRptrCheck_A	233790812	60	0	0
FpvSecCmResCmdFifoWptrCheck_A	233790812	60	0	0
IntrEdnCmdReqDoneKnownO_A	233790812	233624410	0	0
TlAReadyKnownO_A	233790812	233624410	0	0
TlDValidKnownO_A	233790812	233624410	0	0
gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A	233790812	60	0	0
gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A	233790812	60	0	0
gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A	233790812	60	0	0
gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A	233790812	60	0	0
gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A	233790812	60	0	0
gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A	233790812	60	0	0
gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A	233790812	60	0	0
gen_edn_if_asserts[0].EdnDataStableDisable_A	233790812	546298	0	314
gen_edn_if_asserts[0].EdnDataStable_A	233790812	22859	0	407
gen_edn_if_asserts[0].EdnEndPointOut_A	233790812	233624410	0	0
gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A	233790812	134622	0	0
gen_edn_if_asserts[1].EdnDataStableDisable_A	233790812	546298	0	314
gen_edn_if_asserts[1].EdnDataStable_A	233790812	7253	0	143
gen_edn_if_asserts[1].EdnEndPointOut_A	233790812	233624410	0	0
gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A	233790812	134622	0	0
gen_edn_if_asserts[2].EdnDataStableDisable_A	233790812	546298	0	314
gen_edn_if_asserts[2].EdnDataStable_A	233790812	3588	0	150
gen_edn_if_asserts[2].EdnEndPointOut_A	233790812	233624410	0	0
gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A	233790812	134622	0	0
gen_edn_if_asserts[3].EdnDataStableDisable_A	233790812	546298	0	314
gen_edn_if_asserts[3].EdnDataStable_A	233790812	3684	0	123
gen_edn_if_asserts[3].EdnEndPointOut_A	233790812	233624410	0	0
gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A	233790812	134622	0	0
gen_edn_if_asserts[4].EdnDataStableDisable_A	233790812	546298	0	314
gen_edn_if_asserts[4].EdnDataStable_A	233790812	3242	0	117
gen_edn_if_asserts[4].EdnEndPointOut_A	233790812	233624410	0	0
gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A	233790812	134622	0	0
gen_edn_if_asserts[5].EdnDataStableDisable_A	233790812	546298	0	314
gen_edn_if_asserts[5].EdnDataStable_A	233790812	53369	0	105
gen_edn_if_asserts[5].EdnEndPointOut_A	233790812	233624410	0	0
gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A	233790812	134622	0	0
gen_edn_if_asserts[6].EdnDataStableDisable_A	233790812	546298	0	314
gen_edn_if_asserts[6].EdnDataStable_A	233790812	2863	0	102
gen_edn_if_asserts[6].EdnEndPointOut_A	233790812	233624410	0	0
gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A	233790812	134622	0	0

AlertTxKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233790812	233624410	0	0
T1	2419	2360	0	0
T2	3293	3200	0	0
T3	2432	2376	0	0
T10	5856	5769	0	0
T11	2418	2355	0	0
T25	1962	1874	0	0
T26	4468	4417	0	0
T27	1645	1560	0	0
T28	3791	3738	0	0
T29	2470	2385	0	0

CsrngAppIfOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233790812	233624410	0	0
T1	2419	2360	0	0
T2	3293	3200	0	0
T3	2432	2376	0	0
T10	5856	5769	0	0
T11	2418	2355	0	0
T25	1962	1874	0	0
T26	4468	4417	0	0
T27	1645	1560	0	0
T28	3791	3738	0	0
T29	2470	2385	0	0

FpvSecCmCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233790812	109	0	0
T5	1761	1	0	0
T6	23666	0	0	0
T9	0	1	0	0
T15	1495	1	0	0
T16	666	1	0	0
T43	4154	0	0	0
T44	2321	0	0	0
T48	1821	0	0	0
T50	732	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	1839	0	0	0
T57	1601	0	0	0

FpvSecCmGenCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233790812	60	0	0
T17	21407	10	0	0
T18	0	20	0	0
T19	0	10	0	0
T31	1176	0	0	0
T58	0	10	0	0
T59	0	10	0	0
T60	865	0	0	0
T61	354390	0	0	0
T62	1391	0	0	0
T63	3077	0	0	0
T64	1498	0	0	0
T65	1671	0	0	0
T66	2296	0	0	0
T67	3037	0	0	0

FpvSecCmGenCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233790812	60	0	0
T17	21407	10	0	0
T18	0	20	0	0
T19	0	10	0	0
T31	1176	0	0	0
T58	0	10	0	0
T59	0	10	0	0
T60	865	0	0	0
T61	354390	0	0	0
T62	1391	0	0	0
T63	3077	0	0	0
T64	1498	0	0	0
T65	1671	0	0	0
T66	2296	0	0	0
T67	3037	0	0	0

FpvSecCmMainFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233790812	60	0	0
T17	21407	10	0	0
T18	0	20	0	0
T19	0	10	0	0
T31	1176	0	0	0
T58	0	10	0	0
T59	0	10	0	0
T60	865	0	0	0
T61	354390	0	0	0
T62	1391	0	0	0
T63	3077	0	0	0
T64	1498	0	0	0
T65	1671	0	0	0
T66	2296	0	0	0
T67	3037	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233790812	60	0	0
T17	21407	10	0	0
T18	0	20	0	0
T19	0	10	0	0
T31	1176	0	0	0
T58	0	10	0	0
T59	0	10	0	0
T60	865	0	0	0
T61	354390	0	0	0
T62	1391	0	0	0
T63	3077	0	0	0
T64	1498	0	0	0
T65	1671	0	0	0
T66	2296	0	0	0
T67	3037	0	0	0

FpvSecCmResCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233790812	60	0	0
T17	21407	10	0	0
T18	0	20	0	0
T19	0	10	0	0
T31	1176	0	0	0
T58	0	10	0	0
T59	0	10	0	0
T60	865	0	0	0
T61	354390	0	0	0
T62	1391	0	0	0
T63	3077	0	0	0
T64	1498	0	0	0
T65	1671	0	0	0
T66	2296	0	0	0
T67	3037	0	0	0

FpvSecCmResCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233790812	60	0	0
T17	21407	10	0	0
T18	0	20	0	0
T19	0	10	0	0
T31	1176	0	0	0
T58	0	10	0	0
T59	0	10	0	0
T60	865	0	0	0
T61	354390	0	0	0
T62	1391	0	0	0
T63	3077	0	0	0
T64	1498	0	0	0
T65	1671	0	0	0
T66	2296	0	0	0
T67	3037	0	0	0

IntrEdnCmdReqDoneKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233790812	233624410	0	0
T1	2419	2360	0	0
T2	3293	3200	0	0
T3	2432	2376	0	0
T10	5856	5769	0	0
T11	2418	2355	0	0
T25	1962	1874	0	0
T26	4468	4417	0	0
T27	1645	1560	0	0
T28	3791	3738	0	0
T29	2470	2385	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233790812	233624410	0	0
T1	2419	2360	0	0
T2	3293	3200	0	0
T3	2432	2376	0	0
T10	5856	5769	0	0
T11	2418	2355	0	0
T25	1962	1874	0	0
T26	4468	4417	0	0
T27	1645	1560	0	0
T28	3791	3738	0	0
T29	2470	2385	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233790812	233624410	0	0
T1	2419	2360	0	0
T2	3293	3200	0	0
T3	2432	2376	0	0
T10	5856	5769	0	0
T11	2418	2355	0	0
T25	1962	1874	0	0
T26	4468	4417	0	0
T27	1645	1560	0	0
T28	3791	3738	0	0
T29	2470	2385	0	0

gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233790812	60	0	0
T17	21407	10	0	0
T18	0	20	0	0
T19	0	10	0	0
T31	1176	0	0	0
T58	0	10	0	0
T59	0	10	0	0
T60	865	0	0	0
T61	354390	0	0	0
T62	1391	0	0	0
T63	3077	0	0	0
T64	1498	0	0	0
T65	1671	0	0	0
T66	2296	0	0	0
T67	3037	0	0	0

gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233790812	60	0	0
T17	21407	10	0	0
T18	0	20	0	0
T19	0	10	0	0
T31	1176	0	0	0
T58	0	10	0	0
T59	0	10	0	0
T60	865	0	0	0
T61	354390	0	0	0
T62	1391	0	0	0
T63	3077	0	0	0
T64	1498	0	0	0
T65	1671	0	0	0
T66	2296	0	0	0
T67	3037	0	0	0

gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233790812	60	0	0
T17	21407	10	0	0
T18	0	20	0	0
T19	0	10	0	0
T31	1176	0	0	0
T58	0	10	0	0
T59	0	10	0	0
T60	865	0	0	0
T61	354390	0	0	0
T62	1391	0	0	0
T63	3077	0	0	0
T64	1498	0	0	0
T65	1671	0	0	0
T66	2296	0	0	0
T67	3037	0	0	0

gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233790812	60	0	0
T17	21407	10	0	0
T18	0	20	0	0
T19	0	10	0	0
T31	1176	0	0	0
T58	0	10	0	0
T59	0	10	0	0
T60	865	0	0	0
T61	354390	0	0	0
T62	1391	0	0	0
T63	3077	0	0	0
T64	1498	0	0	0
T65	1671	0	0	0
T66	2296	0	0	0
T67	3037	0	0	0

gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233790812	60	0	0
T17	21407	10	0	0
T18	0	20	0	0
T19	0	10	0	0
T31	1176	0	0	0
T58	0	10	0	0
T59	0	10	0	0
T60	865	0	0	0
T61	354390	0	0	0
T62	1391	0	0	0
T63	3077	0	0	0
T64	1498	0	0	0
T65	1671	0	0	0
T66	2296	0	0	0
T67	3037	0	0	0

gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233790812	60	0	0
T17	21407	10	0	0
T18	0	20	0	0
T19	0	10	0	0
T31	1176	0	0	0
T58	0	10	0	0
T59	0	10	0	0
T60	865	0	0	0
T61	354390	0	0	0
T62	1391	0	0	0
T63	3077	0	0	0
T64	1498	0	0	0
T65	1671	0	0	0
T66	2296	0	0	0
T67	3037	0	0	0

gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233790812	60	0	0
T17	21407	10	0	0
T18	0	20	0	0
T19	0	10	0	0
T31	1176	0	0	0
T58	0	10	0	0
T59	0	10	0	0
T60	865	0	0	0
T61	354390	0	0	0
T62	1391	0	0	0
T63	3077	0	0	0
T64	1498	0	0	0
T65	1671	0	0	0
T66	2296	0	0	0
T67	3037	0	0	0

gen_edn_if_asserts[0].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233790812	546298	0	314
T1	2419	1019	0	2
T2	3293	51	0	0
T3	2432	506	0	0
T4	0	0	0	2
T10	5856	73	0	0
T11	2418	242	0	0
T25	1962	239	0	0
T26	4468	26	0	0
T27	1645	11	0	0
T28	3791	140	0	0
T29	2470	193	0	0
T41	0	0	0	2
T49	0	0	0	2
T68	0	0	0	2
T69	0	0	0	2
T70	0	0	0	2
T71	0	0	0	2
T72	0	0	0	2
T73	0	0	0	2

gen_edn_if_asserts[0].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233790812	22859	0	407
T1	2419	5	0	0
T2	3293	3	0	1
T3	2432	0	0	0
T4	0	111	0	0
T6	0	27	0	1
T10	5856	3	0	1
T11	2418	0	0	0
T20	0	0	0	1
T25	1962	0	0	0
T26	4468	21	0	1
T27	1645	0	0	0
T28	3791	0	0	0
T29	2470	0	0	0
T43	0	67	0	1
T56	0	15	0	1
T74	0	15	0	1
T75	0	41	0	1
T76	0	0	0	1

gen_edn_if_asserts[0].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233790812	233624410	0	0
T1	2419	2360	0	0
T2	3293	3200	0	0
T3	2432	2376	0	0
T10	5856	5769	0	0
T11	2418	2355	0	0
T25	1962	1874	0	0
T26	4468	4417	0	0
T27	1645	1560	0	0
T28	3791	3738	0	0
T29	2470	2385	0	0

gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233790812	134622	0	0
T5	1761	1074	0	0
T6	23666	0	0	0
T7	0	592	0	0
T8	0	533	0	0
T15	1495	625	0	0
T16	666	364	0	0
T43	4154	0	0	0
T44	2321	0	0	0
T48	1821	0	0	0
T50	732	397	0	0
T51	0	557	0	0
T56	1839	0	0	0
T57	1601	0	0	0
T77	0	1151	0	0
T78	0	420	0	0
T79	0	172	0	0

gen_edn_if_asserts[1].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233790812	546298	0	314
T1	2419	1019	0	2
T2	3293	51	0	0
T3	2432	506	0	0
T4	0	0	0	2
T10	5856	73	0	0
T11	2418	242	0	0
T25	1962	239	0	0
T26	4468	26	0	0
T27	1645	11	0	0
T28	3791	140	0	0
T29	2470	193	0	0
T41	0	0	0	2
T49	0	0	0	2
T68	0	0	0	2
T69	0	0	0	2
T70	0	0	0	2
T71	0	0	0	2
T72	0	0	0	2
T73	0	0	0	2

gen_edn_if_asserts[1].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233790812	7253	0	143
T2	3293	9	0	1
T3	2432	0	0	0
T10	5856	3	0	1
T11	2418	0	0	0
T25	1962	0	0	0
T26	4468	3	0	1
T27	1645	3	0	1
T28	3791	0	0	0
T29	2470	0	0	0
T33	942	0	0	0
T43	0	3	0	1
T44	0	37	0	1
T45	0	36	0	1
T48	0	4	0	1
T57	0	4	0	1
T80	0	4	0	1

gen_edn_if_asserts[1].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233790812	233624410	0	0
T1	2419	2360	0	0
T2	3293	3200	0	0
T3	2432	2376	0	0
T10	5856	5769	0	0
T11	2418	2355	0	0
T25	1962	1874	0	0
T26	4468	4417	0	0
T27	1645	1560	0	0
T28	3791	3738	0	0
T29	2470	2385	0	0

gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233790812	134622	0	0
T5	1761	1074	0	0
T6	23666	0	0	0
T7	0	592	0	0
T8	0	533	0	0
T15	1495	625	0	0
T16	666	364	0	0
T43	4154	0	0	0
T44	2321	0	0	0
T48	1821	0	0	0
T50	732	397	0	0
T51	0	557	0	0
T56	1839	0	0	0
T57	1601	0	0	0
T77	0	1151	0	0
T78	0	420	0	0
T79	0	172	0	0

gen_edn_if_asserts[2].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233790812	546298	0	314
T1	2419	1019	0	2
T2	3293	51	0	0
T3	2432	506	0	0
T4	0	0	0	2
T10	5856	73	0	0
T11	2418	242	0	0
T25	1962	239	0	0
T26	4468	26	0	0
T27	1645	11	0	0
T28	3791	140	0	0
T29	2470	193	0	0
T41	0	0	0	2
T49	0	0	0	2
T68	0	0	0	2
T69	0	0	0	2
T70	0	0	0	2
T71	0	0	0	2
T72	0	0	0	2
T73	0	0	0	2

gen_edn_if_asserts[2].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233790812	3588	0	150
T2	3293	36	0	1
T3	2432	0	0	0
T10	5856	0	0	0
T11	2418	4	0	0
T25	1962	0	0	0
T26	4468	29	0	1
T27	1645	0	0	0
T28	3791	0	0	0
T29	2470	4	0	1
T33	942	3	0	1
T42	0	4	0	0
T43	0	3	0	1
T44	0	3	0	1
T45	0	0	0	1
T47	0	0	0	1
T81	0	8	0	1
T82	0	4	0	0
T83	0	0	0	1

gen_edn_if_asserts[2].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233790812	233624410	0	0
T1	2419	2360	0	0
T2	3293	3200	0	0
T3	2432	2376	0	0
T10	5856	5769	0	0
T11	2418	2355	0	0
T25	1962	1874	0	0
T26	4468	4417	0	0
T27	1645	1560	0	0
T28	3791	3738	0	0
T29	2470	2385	0	0

gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233790812	134622	0	0
T5	1761	1074	0	0
T6	23666	0	0	0
T7	0	592	0	0
T8	0	533	0	0
T15	1495	625	0	0
T16	666	364	0	0
T43	4154	0	0	0
T44	2321	0	0	0
T48	1821	0	0	0
T50	732	397	0	0
T51	0	557	0	0
T56	1839	0	0	0
T57	1601	0	0	0
T77	0	1151	0	0
T78	0	420	0	0
T79	0	172	0	0

gen_edn_if_asserts[3].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233790812	546298	0	314
T1	2419	1019	0	2
T2	3293	51	0	0
T3	2432	506	0	0
T4	0	0	0	2
T10	5856	73	0	0
T11	2418	242	0	0
T25	1962	239	0	0
T26	4468	26	0	0
T27	1645	11	0	0
T28	3791	140	0	0
T29	2470	193	0	0
T41	0	0	0	2
T49	0	0	0	2
T68	0	0	0	2
T69	0	0	0	2
T70	0	0	0	2
T71	0	0	0	2
T72	0	0	0	2
T73	0	0	0	2

gen_edn_if_asserts[3].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233790812	3684	0	123
T2	3293	3	0	1
T3	2432	0	0	0
T10	5856	3	0	1
T11	2418	0	0	0
T22	0	20	0	1
T25	1962	0	0	0
T26	4468	0	0	0
T27	1645	0	0	0
T28	3791	0	0	0
T29	2470	0	0	0
T33	942	0	0	0
T42	0	4	0	1
T43	0	39	0	1
T44	0	40	0	1
T45	0	3	0	1
T47	0	35	0	1
T57	0	4	0	0
T84	0	4	0	1
T85	0	0	0	1

gen_edn_if_asserts[3].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233790812	233624410	0	0
T1	2419	2360	0	0
T2	3293	3200	0	0
T3	2432	2376	0	0
T10	5856	5769	0	0
T11	2418	2355	0	0
T25	1962	1874	0	0
T26	4468	4417	0	0
T27	1645	1560	0	0
T28	3791	3738	0	0
T29	2470	2385	0	0

gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233790812	134622	0	0
T5	1761	1074	0	0
T6	23666	0	0	0
T7	0	592	0	0
T8	0	533	0	0
T15	1495	625	0	0
T16	666	364	0	0
T43	4154	0	0	0
T44	2321	0	0	0
T48	1821	0	0	0
T50	732	397	0	0
T51	0	557	0	0
T56	1839	0	0	0
T57	1601	0	0	0
T77	0	1151	0	0
T78	0	420	0	0
T79	0	172	0	0

gen_edn_if_asserts[4].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233790812	546298	0	314
T1	2419	1019	0	2
T2	3293	51	0	0
T3	2432	506	0	0
T4	0	0	0	2
T10	5856	73	0	0
T11	2418	242	0	0
T25	1962	239	0	0
T26	4468	26	0	0
T27	1645	11	0	0
T28	3791	140	0	0
T29	2470	193	0	0
T41	0	0	0	2
T49	0	0	0	2
T68	0	0	0	2
T69	0	0	0	2
T70	0	0	0	2
T71	0	0	0	2
T72	0	0	0	2
T73	0	0	0	2

gen_edn_if_asserts[4].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233790812	3242	0	117
T2	3293	3	0	1
T3	2432	0	0	0
T10	5856	854	0	1
T11	2418	0	0	0
T25	1962	4	0	1
T26	4468	57	0	1
T27	1645	0	0	0
T28	3791	53	0	1
T29	2470	0	0	0
T33	942	0	0	0
T43	0	39	0	1
T45	0	3	0	1
T47	0	38	0	1
T85	0	31	0	1
T86	0	4	0	1

gen_edn_if_asserts[4].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233790812	233624410	0	0
T1	2419	2360	0	0
T2	3293	3200	0	0
T3	2432	2376	0	0
T10	5856	5769	0	0
T11	2418	2355	0	0
T25	1962	1874	0	0
T26	4468	4417	0	0
T27	1645	1560	0	0
T28	3791	3738	0	0
T29	2470	2385	0	0

gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233790812	134622	0	0
T5	1761	1074	0	0
T6	23666	0	0	0
T7	0	592	0	0
T8	0	533	0	0
T15	1495	625	0	0
T16	666	364	0	0
T43	4154	0	0	0
T44	2321	0	0	0
T48	1821	0	0	0
T50	732	397	0	0
T51	0	557	0	0
T56	1839	0	0	0
T57	1601	0	0	0
T77	0	1151	0	0
T78	0	420	0	0
T79	0	172	0	0

gen_edn_if_asserts[5].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233790812	546298	0	314
T1	2419	1019	0	2
T2	3293	51	0	0
T3	2432	506	0	0
T4	0	0	0	2
T10	5856	73	0	0
T11	2418	242	0	0
T25	1962	239	0	0
T26	4468	26	0	0
T27	1645	11	0	0
T28	3791	140	0	0
T29	2470	193	0	0
T41	0	0	0	2
T49	0	0	0	2
T68	0	0	0	2
T69	0	0	0	2
T70	0	0	0	2
T71	0	0	0	2
T72	0	0	0	2
T73	0	0	0	2

gen_edn_if_asserts[5].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233790812	53369	0	105
T2	3293	35	0	1
T3	2432	0	0	0
T10	5856	3	0	1
T11	2418	0	0	0
T22	0	49	0	1
T25	1962	0	0	0
T26	4468	0	0	0
T27	1645	0	0	0
T28	3791	0	0	0
T29	2470	0	0	0
T33	942	0	0	0
T43	0	20	0	1
T45	0	3	0	1
T46	0	23	0	1
T80	0	4	0	0
T85	0	3	0	1
T87	0	4	0	1
T88	0	3	0	1
T89	0	0	0	1

gen_edn_if_asserts[5].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233790812	233624410	0	0
T1	2419	2360	0	0
T2	3293	3200	0	0
T3	2432	2376	0	0
T10	5856	5769	0	0
T11	2418	2355	0	0
T25	1962	1874	0	0
T26	4468	4417	0	0
T27	1645	1560	0	0
T28	3791	3738	0	0
T29	2470	2385	0	0

gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233790812	134622	0	0
T5	1761	1074	0	0
T6	23666	0	0	0
T7	0	592	0	0
T8	0	533	0	0
T15	1495	625	0	0
T16	666	364	0	0
T43	4154	0	0	0
T44	2321	0	0	0
T48	1821	0	0	0
T50	732	397	0	0
T51	0	557	0	0
T56	1839	0	0	0
T57	1601	0	0	0
T77	0	1151	0	0
T78	0	420	0	0
T79	0	172	0	0

gen_edn_if_asserts[6].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233790812	546298	0	314
T1	2419	1019	0	2
T2	3293	51	0	0
T3	2432	506	0	0
T4	0	0	0	2
T10	5856	73	0	0
T11	2418	242	0	0
T25	1962	239	0	0
T26	4468	26	0	0
T27	1645	11	0	0
T28	3791	140	0	0
T29	2470	193	0	0
T41	0	0	0	2
T49	0	0	0	2
T68	0	0	0	2
T69	0	0	0	2
T70	0	0	0	2
T71	0	0	0	2
T72	0	0	0	2
T73	0	0	0	2

gen_edn_if_asserts[6].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233790812	2863	0	102
T2	3293	3	0	1
T3	2432	4	0	1
T10	5856	25	0	1
T11	2418	4	0	1
T15	0	1	0	0
T22	0	587	0	1
T25	1962	0	0	0
T26	4468	0	0	0
T27	1645	0	0	0
T28	3791	0	0	0
T29	2470	0	0	0
T33	942	0	0	0
T43	0	24	0	1
T45	0	57	0	1
T46	0	0	0	1
T47	0	3	0	1
T90	0	42	0	1

gen_edn_if_asserts[6].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233790812	233624410	0	0
T1	2419	2360	0	0
T2	3293	3200	0	0
T3	2432	2376	0	0
T10	5856	5769	0	0
T11	2418	2355	0	0
T25	1962	1874	0	0
T26	4468	4417	0	0
T27	1645	1560	0	0
T28	3791	3738	0	0
T29	2470	2385	0	0

gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233790812	134622	0	0
T5	1761	1074	0	0
T6	23666	0	0	0
T7	0	592	0	0
T8	0	533	0	0
T15	1495	625	0	0
T16	666	364	0	0
T43	4154	0	0	0
T44	2321	0	0	0
T48	1821	0	0	0
T50	732	397	0	0
T51	0	557	0	0
T56	1839	0	0	0
T57	1601	0	0	0
T77	0	1151	0	0
T78	0	420	0	0
T79	0	172	0	0