Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44		83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	234268306	10210119	0	0
boot_gen_cmd_rd_A	234268306	55295	0	0
boot_ins_cmd_rd_A	234268306	63404	0	0
ctrl_rd_A	234268306	55860	0	0
err_code_test_rd_A	234268306	63984	0	0
intr_enable_rd_A	234268306	61337	0	0
max_num_reqs_between_reseeds_rd_A	234268306	55499	0	0
regwen_rd_A	234268306	62780	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	234268306	10210119	0	0
T4	124836	717357	0	0
T5	1761	0	0	0
T6	23666	0	0	0
T15	1495	0	0	0
T40	0	30216	0	0
T41	0	68002	0	0
T42	1738	0	0	0
T43	4154	0	0	0
T44	2321	0	0	0
T48	1821	0	0	0
T49	1109	0	0	0
T56	1839	0	0	0
T69	0	76433	0	0
T70	0	230074	0	0
T71	0	185669	0	0
T224	0	129735	0	0
T225	0	100008	0	0
T226	0	62046	0	0
T227	0	175407	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	234268306	55295	0	0
T40	821714	464	0	0
T41	172017	0	0	0
T45	4894	0	0	0
T61	0	2172	0	0
T68	1033	0	0	0
T69	182755	0	0	0
T71	0	2558	0	0
T82	864	0	0	0
T84	2331	0	0	0
T98	15074	0	0	0
T224	0	4003	0	0
T225	0	1795	0	0
T228	0	6614	0	0
T229	0	5248	0	0
T230	0	6150	0	0
T231	0	2403	0	0
T232	0	2509	0	0
T233	3730	0	0	0
T234	2010	0	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	234268306	63404	0	0
T40	821714	588	0	0
T41	172017	0	0	0
T45	4894	0	0	0
T61	0	2441	0	0
T68	1033	0	0	0
T69	182755	0	0	0
T71	0	3188	0	0
T82	864	0	0	0
T84	2331	0	0	0
T98	15074	0	0	0
T224	0	4031	0	0
T225	0	1830	0	0
T228	0	7607	0	0
T229	0	5365	0	0
T230	0	7498	0	0
T231	0	2873	0	0
T232	0	3059	0	0
T233	3730	0	0	0
T234	2010	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	234268306	55860	0	0
T12	0	2	0	0
T15	1495	0	0	0
T16	666	0	0	0
T20	7863	0	0	0
T40	0	411	0	0
T43	4154	1	0	0
T48	1821	0	0	0
T50	732	0	0	0
T57	1601	0	0	0
T71	0	3108	0	0
T75	4505	0	0	0
T76	3874	0	0	0
T81	2447	0	0	0
T120	0	10	0	0
T224	0	3621	0	0
T225	0	1687	0	0
T228	0	6855	0	0
T235	0	8	0	0
T236	0	3	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	234268306	63984	0	0
T40	821714	414	0	0
T41	172017	0	0	0
T45	4894	0	0	0
T61	0	2447	0	0
T68	1033	0	0	0
T69	182755	0	0	0
T71	0	2978	0	0
T82	864	0	0	0
T84	2331	0	0	0
T98	15074	0	0	0
T224	0	4574	0	0
T225	0	1816	0	0
T228	0	7858	0	0
T229	0	5729	0	0
T230	0	7097	0	0
T231	0	2655	0	0
T232	0	3262	0	0
T233	3730	0	0	0
T234	2010	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	234268306	61337	0	0
T6	23666	79	0	0
T15	1495	0	0	0
T16	666	0	0	0
T20	7863	0	0	0
T40	0	591	0	0
T43	4154	0	0	0
T48	1821	0	0	0
T50	732	0	0	0
T57	1601	0	0	0
T61	0	2424	0	0
T71	0	3018	0	0
T75	4505	0	0	0
T76	3874	0	0	0
T224	0	3784	0	0
T225	0	1781	0	0
T228	0	7404	0	0
T229	0	5819	0	0
T230	0	6189	0	0
T234	0	25	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	234268306	55499	0	0
T40	821714	571	0	0
T41	172017	0	0	0
T45	4894	0	0	0
T61	0	1850	0	0
T68	1033	0	0	0
T69	182755	0	0	0
T71	0	2524	0	0
T82	864	0	0	0
T84	2331	0	0	0
T98	15074	0	0	0
T224	0	3771	0	0
T225	0	1695	0	0
T228	0	6995	0	0
T229	0	4865	0	0
T230	0	6450	0	0
T231	0	2300	0	0
T232	0	2637	0	0
T233	3730	0	0	0
T234	2010	0	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	234268306	62780	0	0
T40	821714	576	0	0
T41	172017	0	0	0
T45	4894	0	0	0
T61	0	2365	0	0
T68	1033	0	0	0
T69	182755	0	0	0
T71	0	3016	0	0
T82	864	0	0	0
T84	2331	0	0	0
T98	15074	0	0	0
T224	0	4434	0	0
T225	0	1756	0	0
T228	0	7622	0	0
T229	0	5641	0	0
T230	0	6955	0	0
T231	0	2865	0	0
T232	0	3296	0	0
T233	3730	0	0	0
T234	2010	0	0	0