Unified Coverage Report :: Module :: edn

Module : edn

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	94.44		83.33	100.00			100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.12	98.25	93.97	97.07	91.28	96.37	99.77

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
edn_csr_assert	100.00						100.00
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_edn_core	94.08	99.92	92.75	82.84	91.28	98.83	98.88
u_edn_cov_if	25.00	50.00	0.00
u_reg	96.95	95.02	97.57	100.00		92.16	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Cond Coverage for Module : edn

	Total	Covered	Percent
Conditions	6	5	83.33
Logical	6	5	83.33
Non-Logical	0	0
Event	0	0

 LINE       98
 EXPRESSION (alert[0] || intg_err_alert[0])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T8,T9,T20

 LINE       98
 EXPRESSION (alert[1] || intg_err_alert[1])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T15,T16
1	0	Covered	T2,T4,T5

---

Toggle Coverage for Module : edn

	Total	Covered	Percent
Totals	69	69	100.00
Total Bits	1172	1172	100.00
Total Bits 0->1	586	586	100.00
Total Bits 1->0	586	586	100.00

Ports	69	69	100.00
Port Bits	1172	1172	100.00
Port Bits 0->1	586	586	100.00
Port Bits 1->0	586	586	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T4,T5	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T2,T3,T8	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T8,T19	Yes	T1,T8,T19	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T34,T35,T36	Yes	T34,T35,T36	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i[0].edn_req	Yes	Yes	T2,T3,T9	Yes	T2,T3,T9	INPUT
edn_i[1].edn_req	Yes	Yes	T19,T21,T13	Yes	T19,T21,T13	INPUT
edn_i[2].edn_req	Yes	Yes	T1,T20,T21	Yes	T1,T20,T21	INPUT
edn_i[3].edn_req	Yes	Yes	T37,T38,T39	Yes	T37,T38,T39	INPUT
edn_i[4].edn_req	Yes	Yes	T8,T21,T38	Yes	T8,T21,T38	INPUT
edn_i[5].edn_req	Yes	Yes	T21,T18,T40	Yes	T21,T18,T40	INPUT
edn_i[6].edn_req	Yes	Yes	T4,T21,T22	Yes	T4,T21,T22	INPUT
edn_o[0].edn_bus[31:0]	Yes	Yes	T3,T9,T21	Yes	T3,T9,T21	OUTPUT
edn_o[0].edn_fips	Yes	Yes	T3,T5,T23	Yes	T3,T9,T21	OUTPUT
edn_o[0].edn_ack	Yes	Yes	T3,T9,T21	Yes	T3,T9,T21	OUTPUT
edn_o[1].edn_bus[31:0]	Yes	Yes	T21,T13,T41	Yes	T19,T21,T13	OUTPUT
edn_o[1].edn_fips	Yes	Yes	T21,T13,T42	Yes	T19,T21,T13	OUTPUT
edn_o[1].edn_ack	Yes	Yes	T19,T21,T13	Yes	T19,T21,T13	OUTPUT
edn_o[2].edn_bus[31:0]	Yes	Yes	T21,T13,T18	Yes	T1,T21,T37	OUTPUT
edn_o[2].edn_fips	Yes	Yes	T21,T13,T43	Yes	T21,T37,T13	OUTPUT
edn_o[2].edn_ack	Yes	Yes	T1,T20,T21	Yes	T1,T20,T21	OUTPUT
edn_o[3].edn_bus[31:0]	Yes	Yes	T38,T39,T43	Yes	T37,T38,T39	OUTPUT
edn_o[3].edn_fips	Yes	Yes	T38,T39,T44	Yes	T38,T39,T45	OUTPUT
edn_o[3].edn_ack	Yes	Yes	T37,T38,T39	Yes	T37,T38,T39	OUTPUT
edn_o[4].edn_bus[31:0]	Yes	Yes	T8,T21,T38	Yes	T8,T21,T38	OUTPUT
edn_o[4].edn_fips	Yes	Yes	T21,T38,T46	Yes	T21,T38,T46	OUTPUT
edn_o[4].edn_ack	Yes	Yes	T8,T21,T38	Yes	T8,T21,T38	OUTPUT
edn_o[5].edn_bus[31:0]	Yes	Yes	T21,T18,T47	Yes	T21,T18,T40	OUTPUT
edn_o[5].edn_fips	Yes	Yes	T21,T48,T39	Yes	T21,T47,T48	OUTPUT
edn_o[5].edn_ack	Yes	Yes	T21,T18,T40	Yes	T21,T18,T40	OUTPUT
edn_o[6].edn_bus[31:0]	Yes	Yes	T21,T49,T46	Yes	T21,T22,T49	OUTPUT
edn_o[6].edn_fips	Yes	Yes	T46,T39,T50	Yes	T21,T22,T38	OUTPUT
edn_o[6].edn_ack	Yes	Yes	T4,T21,T22	Yes	T4,T21,T22	OUTPUT
csrng_cmd_o.genbits_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_bus[31:0]	Yes	Yes	T1,T3,T8	Yes	T1,T3,T8	OUTPUT
csrng_cmd_o.csrng_req_valid	Yes	Yes	T1,T3,T8	Yes	T1,T3,T8	OUTPUT
csrng_cmd_i.genbits_bus[127:0]	Yes	Yes	T3,T21,T13	Yes	T1,T3,T21	INPUT
csrng_cmd_i.genbits_fips	Yes	Yes	T1,T3,T21	Yes	T1,T3,T21	INPUT
csrng_cmd_i.genbits_valid	Yes	Yes	T1,T3,T8	Yes	T1,T3,T8	INPUT
csrng_cmd_i.csrng_rsp_sts[2:0]	Yes	Yes	T9,T20,T47	Yes	T9,T20,T47	INPUT
csrng_cmd_i.csrng_rsp_ack	Yes	Yes	T1,T3,T8	Yes	T1,T3,T8	INPUT
csrng_cmd_i.csrng_req_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T8,T9,T20	Yes	T8,T9,T20	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T8,T9,T20	Yes	T8,T9,T20	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
intr_edn_cmd_req_done_o	Yes	Yes	T23,T34,T35	Yes	T23,T34,T35	OUTPUT
intr_edn_fatal_err_o	Yes	Yes	T4,T23,T34	Yes	T4,T23,T34	OUTPUT

*Tests covering at least one bit in the range

---

Assert Coverage for Module : edn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	47	47	100.00	47	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	47	47	100.00	47	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxKnownO_A	195977335	195785750	0	0
CsrngAppIfOut_A	195977335	195785750	0	0
FpvSecCmCntAlertCheck_A	195977335	117	0	0
FpvSecCmGenCmdFifoRptrCheck_A	195977335	80	0	0
FpvSecCmGenCmdFifoWptrCheck_A	195977335	80	0	0
FpvSecCmMainFsmCheck_A	195977335	80	0	0
FpvSecCmRegWeOnehotCheck_A	195977335	80	0	0
FpvSecCmResCmdFifoRptrCheck_A	195977335	80	0	0
FpvSecCmResCmdFifoWptrCheck_A	195977335	80	0	0
IntrEdnCmdReqDoneKnownO_A	195977335	195785750	0	0
TlAReadyKnownO_A	195977335	195785750	0	0
TlDValidKnownO_A	195977335	195785750	0	0
gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A	195977335	80	0	0
gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A	195977335	80	0	0
gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A	195977335	80	0	0
gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A	195977335	80	0	0
gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A	195977335	80	0	0
gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A	195977335	80	0	0
gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A	195977335	80	0	0
gen_edn_if_asserts[0].EdnDataStableDisable_A	195977335	601579	0	322
gen_edn_if_asserts[0].EdnDataStable_A	195977335	68714	0	414
gen_edn_if_asserts[0].EdnEndPointOut_A	195977335	195785750	0	0
gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A	195977335	144016	0	0
gen_edn_if_asserts[1].EdnDataStableDisable_A	195977335	601579	0	322
gen_edn_if_asserts[1].EdnDataStable_A	195977335	8075	0	143
gen_edn_if_asserts[1].EdnEndPointOut_A	195977335	195785750	0	0
gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A	195977335	144016	0	0
gen_edn_if_asserts[2].EdnDataStableDisable_A	195977335	601579	0	322
gen_edn_if_asserts[2].EdnDataStable_A	195977335	4045	0	122
gen_edn_if_asserts[2].EdnEndPointOut_A	195977335	195785750	0	0
gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A	195977335	144016	0	0
gen_edn_if_asserts[3].EdnDataStableDisable_A	195977335	601579	0	322
gen_edn_if_asserts[3].EdnDataStable_A	195977335	4587	0	106
gen_edn_if_asserts[3].EdnEndPointOut_A	195977335	195785750	0	0
gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A	195977335	144016	0	0
gen_edn_if_asserts[4].EdnDataStableDisable_A	195977335	601579	0	322
gen_edn_if_asserts[4].EdnDataStable_A	195977335	3001	0	104
gen_edn_if_asserts[4].EdnEndPointOut_A	195977335	195785750	0	0
gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A	195977335	144016	0	0
gen_edn_if_asserts[5].EdnDataStableDisable_A	195977335	601579	0	322
gen_edn_if_asserts[5].EdnDataStable_A	195977335	3613	0	105
gen_edn_if_asserts[5].EdnEndPointOut_A	195977335	195785750	0	0
gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A	195977335	144016	0	0
gen_edn_if_asserts[6].EdnDataStableDisable_A	195977335	601579	0	322
gen_edn_if_asserts[6].EdnDataStable_A	195977335	4268	0	92
gen_edn_if_asserts[6].EdnEndPointOut_A	195977335	195785750	0	0
gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A	195977335	144016	0	0

AlertTxKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195977335	195785750	0	0
T1	2914	2857	0	0
T2	46899	25807	0	0
T3	3206	3152	0	0
T4	755	592	0	0
T8	2729	2657	0	0
T9	2753	2669	0	0
T19	621	532	0	0
T20	2290	2201	0	0
T21	1679	1598	0	0
T22	1237	1166	0	0

CsrngAppIfOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195977335	195785750	0	0
T1	2914	2857	0	0
T2	46899	25807	0	0
T3	3206	3152	0	0
T4	755	592	0	0
T8	2729	2657	0	0
T9	2753	2669	0	0
T19	621	532	0	0
T20	2290	2201	0	0
T21	1679	1598	0	0
T22	1237	1166	0	0

FpvSecCmCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195977335	117	0	0
T2	46899	20	0	0
T3	3206	0	0	0
T4	755	0	0	0
T5	0	1	0	0
T8	2729	0	0	0
T9	2753	0	0	0
T14	0	1	0	0
T15	0	20	0	0
T19	621	0	0	0
T20	2290	0	0	0
T21	1679	0	0	0
T22	1237	0	0	0
T37	2459	0	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0

FpvSecCmGenCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195977335	80	0	0
T2	46899	20	0	0
T3	3206	0	0	0
T4	755	0	0	0
T8	2729	0	0	0
T9	2753	0	0	0
T15	0	20	0	0
T16	0	10	0	0
T19	621	0	0	0
T20	2290	0	0	0
T21	1679	0	0	0
T22	1237	0	0	0
T37	2459	0	0	0
T56	0	20	0	0
T57	0	10	0	0

FpvSecCmGenCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195977335	80	0	0
T2	46899	20	0	0
T3	3206	0	0	0
T4	755	0	0	0
T8	2729	0	0	0
T9	2753	0	0	0
T15	0	20	0	0
T16	0	10	0	0
T19	621	0	0	0
T20	2290	0	0	0
T21	1679	0	0	0
T22	1237	0	0	0
T37	2459	0	0	0
T56	0	20	0	0
T57	0	10	0	0

FpvSecCmMainFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195977335	80	0	0
T2	46899	20	0	0
T3	3206	0	0	0
T4	755	0	0	0
T8	2729	0	0	0
T9	2753	0	0	0
T15	0	20	0	0
T16	0	10	0	0
T19	621	0	0	0
T20	2290	0	0	0
T21	1679	0	0	0
T22	1237	0	0	0
T37	2459	0	0	0
T56	0	20	0	0
T57	0	10	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195977335	80	0	0
T2	46899	20	0	0
T3	3206	0	0	0
T4	755	0	0	0
T8	2729	0	0	0
T9	2753	0	0	0
T15	0	20	0	0
T16	0	10	0	0
T19	621	0	0	0
T20	2290	0	0	0
T21	1679	0	0	0
T22	1237	0	0	0
T37	2459	0	0	0
T56	0	20	0	0
T57	0	10	0	0

FpvSecCmResCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195977335	80	0	0
T2	46899	20	0	0
T3	3206	0	0	0
T4	755	0	0	0
T8	2729	0	0	0
T9	2753	0	0	0
T15	0	20	0	0
T16	0	10	0	0
T19	621	0	0	0
T20	2290	0	0	0
T21	1679	0	0	0
T22	1237	0	0	0
T37	2459	0	0	0
T56	0	20	0	0
T57	0	10	0	0

FpvSecCmResCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195977335	80	0	0
T2	46899	20	0	0
T3	3206	0	0	0
T4	755	0	0	0
T8	2729	0	0	0
T9	2753	0	0	0
T15	0	20	0	0
T16	0	10	0	0
T19	621	0	0	0
T20	2290	0	0	0
T21	1679	0	0	0
T22	1237	0	0	0
T37	2459	0	0	0
T56	0	20	0	0
T57	0	10	0	0

IntrEdnCmdReqDoneKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195977335	195785750	0	0
T1	2914	2857	0	0
T2	46899	25807	0	0
T3	3206	3152	0	0
T4	755	592	0	0
T8	2729	2657	0	0
T9	2753	2669	0	0
T19	621	532	0	0
T20	2290	2201	0	0
T21	1679	1598	0	0
T22	1237	1166	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195977335	195785750	0	0
T1	2914	2857	0	0
T2	46899	25807	0	0
T3	3206	3152	0	0
T4	755	592	0	0
T8	2729	2657	0	0
T9	2753	2669	0	0
T19	621	532	0	0
T20	2290	2201	0	0
T21	1679	1598	0	0
T22	1237	1166	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195977335	195785750	0	0
T1	2914	2857	0	0
T2	46899	25807	0	0
T3	3206	3152	0	0
T4	755	592	0	0
T8	2729	2657	0	0
T9	2753	2669	0	0
T19	621	532	0	0
T20	2290	2201	0	0
T21	1679	1598	0	0
T22	1237	1166	0	0

gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195977335	80	0	0
T2	46899	20	0	0
T3	3206	0	0	0
T4	755	0	0	0
T8	2729	0	0	0
T9	2753	0	0	0
T15	0	20	0	0
T16	0	10	0	0
T19	621	0	0	0
T20	2290	0	0	0
T21	1679	0	0	0
T22	1237	0	0	0
T37	2459	0	0	0
T56	0	20	0	0
T57	0	10	0	0

gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195977335	80	0	0
T2	46899	20	0	0
T3	3206	0	0	0
T4	755	0	0	0
T8	2729	0	0	0
T9	2753	0	0	0
T15	0	20	0	0
T16	0	10	0	0
T19	621	0	0	0
T20	2290	0	0	0
T21	1679	0	0	0
T22	1237	0	0	0
T37	2459	0	0	0
T56	0	20	0	0
T57	0	10	0	0

gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195977335	80	0	0
T2	46899	20	0	0
T3	3206	0	0	0
T4	755	0	0	0
T8	2729	0	0	0
T9	2753	0	0	0
T15	0	20	0	0
T16	0	10	0	0
T19	621	0	0	0
T20	2290	0	0	0
T21	1679	0	0	0
T22	1237	0	0	0
T37	2459	0	0	0
T56	0	20	0	0
T57	0	10	0	0

gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195977335	80	0	0
T2	46899	20	0	0
T3	3206	0	0	0
T4	755	0	0	0
T8	2729	0	0	0
T9	2753	0	0	0
T15	0	20	0	0
T16	0	10	0	0
T19	621	0	0	0
T20	2290	0	0	0
T21	1679	0	0	0
T22	1237	0	0	0
T37	2459	0	0	0
T56	0	20	0	0
T57	0	10	0	0

gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195977335	80	0	0
T2	46899	20	0	0
T3	3206	0	0	0
T4	755	0	0	0
T8	2729	0	0	0
T9	2753	0	0	0
T15	0	20	0	0
T16	0	10	0	0
T19	621	0	0	0
T20	2290	0	0	0
T21	1679	0	0	0
T22	1237	0	0	0
T37	2459	0	0	0
T56	0	20	0	0
T57	0	10	0	0

gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195977335	80	0	0
T2	46899	20	0	0
T3	3206	0	0	0
T4	755	0	0	0
T8	2729	0	0	0
T9	2753	0	0	0
T15	0	20	0	0
T16	0	10	0	0
T19	621	0	0	0
T20	2290	0	0	0
T21	1679	0	0	0
T22	1237	0	0	0
T37	2459	0	0	0
T56	0	20	0	0
T57	0	10	0	0

gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195977335	80	0	0
T2	46899	20	0	0
T3	3206	0	0	0
T4	755	0	0	0
T8	2729	0	0	0
T9	2753	0	0	0
T15	0	20	0	0
T16	0	10	0	0
T19	621	0	0	0
T20	2290	0	0	0
T21	1679	0	0	0
T22	1237	0	0	0
T37	2459	0	0	0
T56	0	20	0	0
T57	0	10	0	0

gen_edn_if_asserts[0].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195977335	601579	0	322
T1	2914	1457	0	2
T2	46899	20642	0	2
T3	3206	393	0	0
T4	755	333	0	0
T8	2729	207	0	0
T9	2753	560	0	0
T18	0	0	0	2
T19	621	52	0	0
T20	2290	135	0	0
T21	1679	20	0	0
T22	1237	84	0	0
T34	0	0	0	2
T35	0	0	0	2
T36	0	0	0	2
T40	0	0	0	2
T58	0	0	0	2
T59	0	0	0	2
T60	0	0	0	2

gen_edn_if_asserts[0].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195977335	68714	0	414
T3	3206	69	0	1
T4	755	0	0	0
T8	2729	0	0	0
T9	2753	4	0	1
T13	4166	3	0	1
T19	621	0	0	0
T20	2290	0	0	0
T21	1679	3	0	1
T22	1237	0	0	0
T23	0	13	0	0
T34	0	52	0	0
T37	2459	0	0	0
T61	0	3	0	1
T62	0	3	0	1
T63	0	57	0	1
T64	0	4	0	1
T65	0	0	0	1
T66	0	0	0	1

gen_edn_if_asserts[0].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195977335	195785750	0	0
T1	2914	2857	0	0
T2	46899	25807	0	0
T3	3206	3152	0	0
T4	755	592	0	0
T8	2729	2657	0	0
T9	2753	2669	0	0
T19	621	532	0	0
T20	2290	2201	0	0
T21	1679	1598	0	0
T22	1237	1166	0	0

gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195977335	144016	0	0
T2	46899	18973	0	0
T3	3206	0	0	0
T4	755	7	0	0
T5	0	184	0	0
T6	0	1102	0	0
T7	0	272	0	0
T8	2729	0	0	0
T9	2753	0	0	0
T14	0	454	0	0
T15	0	14209	0	0
T19	621	0	0	0
T20	2290	0	0	0
T21	1679	0	0	0
T22	1237	0	0	0
T28	0	240	0	0
T37	2459	0	0	0
T67	0	401	0	0
T68	0	260	0	0

gen_edn_if_asserts[1].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195977335	601579	0	322
T1	2914	1457	0	2
T2	46899	20642	0	2
T3	3206	393	0	0
T4	755	333	0	0
T8	2729	207	0	0
T9	2753	560	0	0
T18	0	0	0	2
T19	621	52	0	0
T20	2290	135	0	0
T21	1679	20	0	0
T22	1237	84	0	0
T34	0	0	0	2
T35	0	0	0	2
T36	0	0	0	2
T40	0	0	0	2
T58	0	0	0	2
T59	0	0	0	2
T60	0	0	0	2

gen_edn_if_asserts[1].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195977335	8075	0	143
T4	755	0	0	0
T9	2753	0	0	0
T13	4166	57	0	1
T19	621	3	0	1
T20	2290	0	0	0
T21	1679	9	0	1
T22	1237	0	0	0
T37	2459	0	0	0
T38	0	3	0	1
T41	0	4	0	1
T42	0	19	0	1
T43	0	3	0	1
T61	1070	0	0	0
T62	1687	0	0	0
T69	0	4	0	1
T70	0	4	0	0
T71	0	4	0	0
T72	0	0	0	1
T73	0	0	0	1

gen_edn_if_asserts[1].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195977335	195785750	0	0
T1	2914	2857	0	0
T2	46899	25807	0	0
T3	3206	3152	0	0
T4	755	592	0	0
T8	2729	2657	0	0
T9	2753	2669	0	0
T19	621	532	0	0
T20	2290	2201	0	0
T21	1679	1598	0	0
T22	1237	1166	0	0

gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195977335	144016	0	0
T2	46899	18973	0	0
T3	3206	0	0	0
T4	755	7	0	0
T5	0	184	0	0
T6	0	1102	0	0
T7	0	272	0	0
T8	2729	0	0	0
T9	2753	0	0	0
T14	0	454	0	0
T15	0	14209	0	0
T19	621	0	0	0
T20	2290	0	0	0
T21	1679	0	0	0
T22	1237	0	0	0
T28	0	240	0	0
T37	2459	0	0	0
T67	0	401	0	0
T68	0	260	0	0

gen_edn_if_asserts[2].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195977335	601579	0	322
T1	2914	1457	0	2
T2	46899	20642	0	2
T3	3206	393	0	0
T4	755	333	0	0
T8	2729	207	0	0
T9	2753	560	0	0
T18	0	0	0	2
T19	621	52	0	0
T20	2290	135	0	0
T21	1679	20	0	0
T22	1237	84	0	0
T34	0	0	0	2
T35	0	0	0	2
T36	0	0	0	2
T40	0	0	0	2
T58	0	0	0	2
T59	0	0	0	2
T60	0	0	0	2

gen_edn_if_asserts[2].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195977335	4045	0	122
T1	2914	4	0	0
T2	46899	0	0	0
T3	3206	0	0	0
T4	755	0	0	0
T8	2729	0	0	0
T9	2753	0	0	0
T13	0	483	0	1
T18	0	4	0	0
T19	621	0	0	0
T20	2290	4	0	1
T21	1679	44	0	1
T22	1237	0	0	0
T37	0	3	0	1
T38	0	3	0	1
T43	0	39	0	1
T73	0	0	0	1
T74	0	4	0	1
T75	0	15	0	1
T76	0	0	0	1

gen_edn_if_asserts[2].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195977335	195785750	0	0
T1	2914	2857	0	0
T2	46899	25807	0	0
T3	3206	3152	0	0
T4	755	592	0	0
T8	2729	2657	0	0
T9	2753	2669	0	0
T19	621	532	0	0
T20	2290	2201	0	0
T21	1679	1598	0	0
T22	1237	1166	0	0

gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195977335	144016	0	0
T2	46899	18973	0	0
T3	3206	0	0	0
T4	755	7	0	0
T5	0	184	0	0
T6	0	1102	0	0
T7	0	272	0	0
T8	2729	0	0	0
T9	2753	0	0	0
T14	0	454	0	0
T15	0	14209	0	0
T19	621	0	0	0
T20	2290	0	0	0
T21	1679	0	0	0
T22	1237	0	0	0
T28	0	240	0	0
T37	2459	0	0	0
T67	0	401	0	0
T68	0	260	0	0

gen_edn_if_asserts[3].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195977335	601579	0	322
T1	2914	1457	0	2
T2	46899	20642	0	2
T3	3206	393	0	0
T4	755	333	0	0
T8	2729	207	0	0
T9	2753	560	0	0
T18	0	0	0	2
T19	621	52	0	0
T20	2290	135	0	0
T21	1679	20	0	0
T22	1237	84	0	0
T34	0	0	0	2
T35	0	0	0	2
T36	0	0	0	2
T40	0	0	0	2
T58	0	0	0	2
T59	0	0	0	2
T60	0	0	0	2

gen_edn_if_asserts[3].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195977335	4587	0	106
T5	622	0	0	0
T13	4166	0	0	0
T18	2320	0	0	0
T23	14894	0	0	0
T37	2459	3	0	1
T38	0	36	0	1
T39	0	11	0	1
T43	0	3	0	1
T44	0	0	0	1
T45	0	4	0	1
T58	1526	0	0	0
T61	1070	0	0	0
T62	1687	0	0	0
T63	4074	0	0	0
T69	2075	0	0	0
T72	0	3	0	1
T73	0	3	0	1
T77	0	1	0	0
T78	0	3	0	1
T79	0	3	0	1

gen_edn_if_asserts[3].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195977335	195785750	0	0
T1	2914	2857	0	0
T2	46899	25807	0	0
T3	3206	3152	0	0
T4	755	592	0	0
T8	2729	2657	0	0
T9	2753	2669	0	0
T19	621	532	0	0
T20	2290	2201	0	0
T21	1679	1598	0	0
T22	1237	1166	0	0

gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195977335	144016	0	0
T2	46899	18973	0	0
T3	3206	0	0	0
T4	755	7	0	0
T5	0	184	0	0
T6	0	1102	0	0
T7	0	272	0	0
T8	2729	0	0	0
T9	2753	0	0	0
T14	0	454	0	0
T15	0	14209	0	0
T19	621	0	0	0
T20	2290	0	0	0
T21	1679	0	0	0
T22	1237	0	0	0
T28	0	240	0	0
T37	2459	0	0	0
T67	0	401	0	0
T68	0	260	0	0

gen_edn_if_asserts[4].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195977335	601579	0	322
T1	2914	1457	0	2
T2	46899	20642	0	2
T3	3206	393	0	0
T4	755	333	0	0
T8	2729	207	0	0
T9	2753	560	0	0
T18	0	0	0	2
T19	621	52	0	0
T20	2290	135	0	0
T21	1679	20	0	0
T22	1237	84	0	0
T34	0	0	0	2
T35	0	0	0	2
T36	0	0	0	2
T40	0	0	0	2
T58	0	0	0	2
T59	0	0	0	2
T60	0	0	0	2

gen_edn_if_asserts[4].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195977335	3001	0	104
T4	755	0	0	0
T8	2729	4	0	1
T9	2753	0	0	0
T13	4166	0	0	0
T19	621	0	0	0
T20	2290	0	0	0
T21	1679	13	0	1
T22	1237	0	0	0
T37	2459	0	0	0
T38	0	47	0	1
T46	0	43	0	1
T61	1070	0	0	0
T79	0	3	0	1
T80	0	4	0	0
T81	0	15	0	1
T82	0	4	0	1
T83	0	18	0	1
T84	0	3	0	1
T85	0	0	0	1

gen_edn_if_asserts[4].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195977335	195785750	0	0
T1	2914	2857	0	0
T2	46899	25807	0	0
T3	3206	3152	0	0
T4	755	592	0	0
T8	2729	2657	0	0
T9	2753	2669	0	0
T19	621	532	0	0
T20	2290	2201	0	0
T21	1679	1598	0	0
T22	1237	1166	0	0

gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195977335	144016	0	0
T2	46899	18973	0	0
T3	3206	0	0	0
T4	755	7	0	0
T5	0	184	0	0
T6	0	1102	0	0
T7	0	272	0	0
T8	2729	0	0	0
T9	2753	0	0	0
T14	0	454	0	0
T15	0	14209	0	0
T19	621	0	0	0
T20	2290	0	0	0
T21	1679	0	0	0
T22	1237	0	0	0
T28	0	240	0	0
T37	2459	0	0	0
T67	0	401	0	0
T68	0	260	0	0

gen_edn_if_asserts[5].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195977335	601579	0	322
T1	2914	1457	0	2
T2	46899	20642	0	2
T3	3206	393	0	0
T4	755	333	0	0
T8	2729	207	0	0
T9	2753	560	0	0
T18	0	0	0	2
T19	621	52	0	0
T20	2290	135	0	0
T21	1679	20	0	0
T22	1237	84	0	0
T34	0	0	0	2
T35	0	0	0	2
T36	0	0	0	2
T40	0	0	0	2
T58	0	0	0	2
T59	0	0	0	2
T60	0	0	0	2

gen_edn_if_asserts[5].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195977335	3613	0	105
T5	622	0	0	0
T13	4166	0	0	0
T18	2320	4	0	0
T21	1679	25	0	1
T22	1237	0	0	0
T23	14894	0	0	0
T37	2459	0	0	0
T39	0	10	0	1
T40	0	4	0	0
T47	0	4	0	1
T48	0	17	0	1
T58	1526	0	0	0
T61	1070	0	0	0
T62	1687	0	0	0
T70	0	4	0	1
T72	0	0	0	1
T78	0	0	0	1
T81	0	44	0	1
T86	0	4	0	1
T87	0	4	0	0
T88	0	0	0	1

gen_edn_if_asserts[5].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195977335	195785750	0	0
T1	2914	2857	0	0
T2	46899	25807	0	0
T3	3206	3152	0	0
T4	755	592	0	0
T8	2729	2657	0	0
T9	2753	2669	0	0
T19	621	532	0	0
T20	2290	2201	0	0
T21	1679	1598	0	0
T22	1237	1166	0	0

gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195977335	144016	0	0
T2	46899	18973	0	0
T3	3206	0	0	0
T4	755	7	0	0
T5	0	184	0	0
T6	0	1102	0	0
T7	0	272	0	0
T8	2729	0	0	0
T9	2753	0	0	0
T14	0	454	0	0
T15	0	14209	0	0
T19	621	0	0	0
T20	2290	0	0	0
T21	1679	0	0	0
T22	1237	0	0	0
T28	0	240	0	0
T37	2459	0	0	0
T67	0	401	0	0
T68	0	260	0	0

gen_edn_if_asserts[6].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195977335	601579	0	322
T1	2914	1457	0	2
T2	46899	20642	0	2
T3	3206	393	0	0
T4	755	333	0	0
T8	2729	207	0	0
T9	2753	560	0	0
T18	0	0	0	2
T19	621	52	0	0
T20	2290	135	0	0
T21	1679	20	0	0
T22	1237	84	0	0
T34	0	0	0	2
T35	0	0	0	2
T36	0	0	0	2
T40	0	0	0	2
T58	0	0	0	2
T59	0	0	0	2
T60	0	0	0	2

gen_edn_if_asserts[6].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195977335	4268	0	92
T4	755	1	0	0
T5	622	0	0	0
T13	4166	0	0	0
T21	1679	10	0	1
T22	1237	3	0	1
T23	14894	0	0	0
T37	2459	0	0	0
T38	0	3	0	1
T39	0	24	0	1
T46	0	61	0	1
T49	0	4	0	0
T50	0	1	0	0
T58	1526	0	0	0
T61	1070	0	0	0
T62	1687	0	0	0
T72	0	0	0	1
T78	0	0	0	1
T79	0	0	0	1
T89	0	4	0	1
T90	0	4	0	0
T91	0	0	0	1

gen_edn_if_asserts[6].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195977335	195785750	0	0
T1	2914	2857	0	0
T2	46899	25807	0	0
T3	3206	3152	0	0
T4	755	592	0	0
T8	2729	2657	0	0
T9	2753	2669	0	0
T19	621	532	0	0
T20	2290	2201	0	0
T21	1679	1598	0	0
T22	1237	1166	0	0

gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195977335	144016	0	0
T2	46899	18973	0	0
T3	3206	0	0	0
T4	755	7	0	0
T5	0	184	0	0
T6	0	1102	0	0
T7	0	272	0	0
T8	2729	0	0	0
T9	2753	0	0	0
T14	0	454	0	0
T15	0	14209	0	0
T19	621	0	0	0
T20	2290	0	0	0
T21	1679	0	0	0
T22	1237	0	0	0
T28	0	240	0	0
T37	2459	0	0	0
T67	0	401	0	0
T68	0	260	0	0