Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44		83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	196542504	8855627	0	0
boot_gen_cmd_rd_A	196542504	48207	0	0
boot_ins_cmd_rd_A	196542504	54028	0	0
ctrl_rd_A	196542504	48978	0	0
err_code_test_rd_A	196542504	55379	0	0
intr_enable_rd_A	196542504	53717	0	0
max_num_reqs_between_reseeds_rd_A	196542504	50257	0	0
regwen_rd_A	196542504	56279	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196542504	8855627	0	0
T6	2025	0	0	0
T28	624	0	0	0
T34	251615	87073	0	0
T35	182701	104631	0	0
T36	0	27214	0	0
T40	2441	0	0	0
T47	2394	0	0	0
T49	1045	0	0	0
T59	0	176493	0	0
T60	0	60380	0	0
T65	1296	0	0	0
T66	1505	0	0	0
T99	0	241274	0	0
T100	0	246948	0	0
T101	3096	0	0	0
T227	0	247509	0	0
T228	0	409157	0	0
T229	0	582415	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196542504	48207	0	0
T6	2025	0	0	0
T28	624	0	0	0
T34	251615	2596	0	0
T35	182701	0	0	0
T36	0	351	0	0
T40	2441	0	0	0
T47	2394	0	0	0
T49	1045	0	0	0
T60	0	873	0	0
T65	1296	0	0	0
T66	1505	0	0	0
T99	0	6549	0	0
T100	0	7274	0	0
T101	3096	0	0	0
T227	0	3885	0	0
T230	0	1225	0	0
T231	0	858	0	0
T232	0	888	0	0
T233	0	3973	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196542504	54028	0	0
T6	2025	0	0	0
T28	624	0	0	0
T34	251615	2697	0	0
T35	182701	0	0	0
T36	0	443	0	0
T40	2441	0	0	0
T47	2394	0	0	0
T49	1045	0	0	0
T60	0	1006	0	0
T65	1296	0	0	0
T66	1505	0	0	0
T99	0	7202	0	0
T100	0	8250	0	0
T101	3096	0	0	0
T227	0	3834	0	0
T230	0	1610	0	0
T231	0	809	0	0
T232	0	984	0	0
T233	0	4601	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196542504	48978	0	0
T6	2025	0	0	0
T10	0	3	0	0
T18	2320	4	0	0
T28	624	0	0	0
T34	251615	2621	0	0
T35	182701	0	0	0
T36	0	487	0	0
T60	0	973	0	0
T63	4074	0	0	0
T64	2252	0	0	0
T65	1296	2	0	0
T66	1505	0	0	0
T69	2075	0	0	0
T99	0	7004	0	0
T100	0	7137	0	0
T101	0	6	0	0
T227	0	3602	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196542504	55379	0	0
T6	2025	0	0	0
T28	624	0	0	0
T34	251615	2783	0	0
T35	182701	0	0	0
T36	0	560	0	0
T40	2441	0	0	0
T47	2394	0	0	0
T49	1045	0	0	0
T60	0	1156	0	0
T65	1296	0	0	0
T66	1505	0	0	0
T99	0	7673	0	0
T100	0	8347	0	0
T101	3096	0	0	0
T227	0	4231	0	0
T230	0	1594	0	0
T231	0	1042	0	0
T232	0	1022	0	0
T233	0	4770	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196542504	53717	0	0
T6	2025	0	0	0
T28	624	0	0	0
T34	251615	2740	0	0
T35	182701	0	0	0
T36	0	559	0	0
T40	2441	0	0	0
T47	2394	0	0	0
T49	1045	0	0	0
T60	0	949	0	0
T65	1296	0	0	0
T66	1505	0	0	0
T99	0	6736	0	0
T100	0	7379	0	0
T101	3096	0	0	0
T227	0	3923	0	0
T230	0	1461	0	0
T234	0	68	0	0
T235	0	12	0	0
T236	0	92	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196542504	50257	0	0
T6	2025	0	0	0
T28	624	0	0	0
T34	251615	2643	0	0
T35	182701	0	0	0
T36	0	377	0	0
T40	2441	0	0	0
T47	2394	0	0	0
T49	1045	0	0	0
T60	0	895	0	0
T65	1296	0	0	0
T66	1505	0	0	0
T99	0	6759	0	0
T100	0	7180	0	0
T101	3096	0	0	0
T227	0	3780	0	0
T230	0	1419	0	0
T231	0	787	0	0
T232	0	806	0	0
T233	0	4058	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196542504	56279	0	0
T6	2025	0	0	0
T28	624	0	0	0
T34	251615	3001	0	0
T35	182701	0	0	0
T36	0	565	0	0
T40	2441	0	0	0
T47	2394	0	0	0
T49	1045	0	0	0
T60	0	1031	0	0
T65	1296	0	0	0
T66	1505	0	0	0
T99	0	7392	0	0
T100	0	8137	0	0
T101	3096	0	0	0
T227	0	4252	0	0
T230	0	1219	0	0
T231	0	883	0	0
T232	0	1078	0	0
T233	0	4509	0	0