Unified Coverage Report :: Module :: edn

Module : edn

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	94.44		83.33	100.00			100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.21	98.25	93.97	97.02	91.86	96.37	99.77

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
edn_csr_assert	100.00						100.00
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_edn_core	94.13	99.92	92.75	82.54	91.86	98.83	98.88
u_edn_cov_if	25.00	50.00	0.00
u_reg	96.95	95.02	97.57	100.00		92.16	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Cond Coverage for Module : edn

	Total	Covered	Percent
Conditions	6	5	83.33
Logical	6	5	83.33
Non-Logical	0	0
Event	0	0

 LINE       98
 EXPRESSION (alert[0] || intg_err_alert[0])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T11,T26,T31

 LINE       98
 EXPRESSION (alert[1] || intg_err_alert[1])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T18,T19,T20
1	0	Covered	T5,T7,T16

---

Toggle Coverage for Module : edn

	Total	Covered	Percent
Totals	69	69	100.00
Total Bits	1172	1172	100.00
Total Bits 0->1	586	586	100.00
Total Bits 1->0	586	586	100.00

Ports	69	69	100.00
Port Bits	1172	1172	100.00
Port Bits 0->1	586	586	100.00
Port Bits 1->0	586	586	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T4,T5,T6	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T26	Yes	T1,T2,T26	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T39,T40,T41	Yes	T39,T40,T41	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T2,T4,T11	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T2,*T3,*T4	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i[0].edn_req	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
edn_i[1].edn_req	Yes	Yes	T2,T3,T11	Yes	T2,T3,T11	INPUT
edn_i[2].edn_req	Yes	Yes	T3,T12,T31	Yes	T3,T12,T31	INPUT
edn_i[3].edn_req	Yes	Yes	T13,T42,T43	Yes	T13,T42,T43	INPUT
edn_i[4].edn_req	Yes	Yes	T3,T26,T13	Yes	T3,T26,T13	INPUT
edn_i[5].edn_req	Yes	Yes	T3,T10,T5	Yes	T3,T10,T5	INPUT
edn_i[6].edn_req	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	INPUT
edn_o[0].edn_bus[31:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
edn_o[0].edn_fips	Yes	Yes	T3,T4,T27	Yes	T3,T4,T27	OUTPUT
edn_o[0].edn_ack	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
edn_o[1].edn_bus[31:0]	Yes	Yes	T2,T3,T11	Yes	T2,T3,T11	OUTPUT
edn_o[1].edn_fips	Yes	Yes	T2,T13,T44	Yes	T2,T3,T11	OUTPUT
edn_o[1].edn_ack	Yes	Yes	T2,T3,T11	Yes	T2,T3,T11	OUTPUT
edn_o[2].edn_bus[31:0]	Yes	Yes	T3,T12,T31	Yes	T3,T12,T31	OUTPUT
edn_o[2].edn_fips	Yes	Yes	T25,T44,T45	Yes	T25,T44,T45	OUTPUT
edn_o[2].edn_ack	Yes	Yes	T3,T12,T31	Yes	T3,T12,T31	OUTPUT
edn_o[3].edn_bus[31:0]	Yes	Yes	T13,T42,T43	Yes	T13,T42,T43	OUTPUT
edn_o[3].edn_fips	Yes	Yes	T13,T25,T46	Yes	T13,T42,T43	OUTPUT
edn_o[3].edn_ack	Yes	Yes	T13,T42,T43	Yes	T13,T42,T43	OUTPUT
edn_o[4].edn_bus[31:0]	Yes	Yes	T3,T26,T13	Yes	T3,T26,T13	OUTPUT
edn_o[4].edn_fips	Yes	Yes	T3,T46,T32	Yes	T3,T13,T46	OUTPUT
edn_o[4].edn_ack	Yes	Yes	T3,T26,T13	Yes	T3,T26,T13	OUTPUT
edn_o[5].edn_bus[31:0]	Yes	Yes	T3,T10,T5	Yes	T3,T10,T5	OUTPUT
edn_o[5].edn_fips	Yes	Yes	T5,T13,T25	Yes	T5,T13,T47	OUTPUT
edn_o[5].edn_ack	Yes	Yes	T3,T10,T5	Yes	T3,T10,T5	OUTPUT
edn_o[6].edn_bus[31:0]	Yes	Yes	T1,T3,T48	Yes	T1,T3,T48	OUTPUT
edn_o[6].edn_fips	Yes	Yes	T1,T48,T25	Yes	T1,T3,T48	OUTPUT
edn_o[6].edn_ack	Yes	Yes	T1,T3,T48	Yes	T1,T3,T48	OUTPUT
csrng_cmd_o.genbits_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_bus[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_i.genbits_bus[127:0]	Yes	Yes	T2,T3,T10	Yes	T2,T3,T10	INPUT
csrng_cmd_i.genbits_fips	Yes	Yes	T1,T2,T3	Yes	T2,T3,T4	INPUT
csrng_cmd_i.genbits_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_rsp_sts[2:0]	Yes	Yes	T11,T31,T42	Yes	T11,T31,T42	INPUT
csrng_cmd_i.csrng_rsp_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_req_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T11,T26,T31	Yes	T11,T26,T31	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T5,T7,T16	Yes	T5,T7,T16	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T11,T26,T31	Yes	T11,T26,T31	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T5,T7,T16	Yes	T5,T7,T16	OUTPUT
intr_edn_cmd_req_done_o	Yes	Yes	T4,T6,T49	Yes	T4,T6,T49	OUTPUT
intr_edn_fatal_err_o	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT

*Tests covering at least one bit in the range

---

Assert Coverage for Module : edn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	47	47	100.00	47	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	47	47	100.00	47	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxKnownO_A	220604048	220402625	0	0
CsrngAppIfOut_A	220604048	220402625	0	0
FpvSecCmCntAlertCheck_A	220604048	137	0	0
FpvSecCmGenCmdFifoRptrCheck_A	220604048	90	0	0
FpvSecCmGenCmdFifoWptrCheck_A	220604048	90	0	0
FpvSecCmMainFsmCheck_A	220604048	90	0	0
FpvSecCmRegWeOnehotCheck_A	220604048	90	0	0
FpvSecCmResCmdFifoRptrCheck_A	220604048	90	0	0
FpvSecCmResCmdFifoWptrCheck_A	220604048	90	0	0
IntrEdnCmdReqDoneKnownO_A	220604048	220402625	0	0
TlAReadyKnownO_A	220604048	220402625	0	0
TlDValidKnownO_A	220604048	220402625	0	0
gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A	220604048	90	0	0
gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A	220604048	90	0	0
gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A	220604048	90	0	0
gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A	220604048	90	0	0
gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A	220604048	90	0	0
gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A	220604048	90	0	0
gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A	220604048	90	0	0
gen_edn_if_asserts[0].EdnDataStableDisable_A	220604048	618354	0	320
gen_edn_if_asserts[0].EdnDataStable_A	220604048	76146	0	426
gen_edn_if_asserts[0].EdnEndPointOut_A	220604048	220402625	0	0
gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A	220604048	162781	0	0
gen_edn_if_asserts[1].EdnDataStableDisable_A	220604048	618354	0	320
gen_edn_if_asserts[1].EdnDataStable_A	220604048	3354	0	130
gen_edn_if_asserts[1].EdnEndPointOut_A	220604048	220402625	0	0
gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A	220604048	162781	0	0
gen_edn_if_asserts[2].EdnDataStableDisable_A	220604048	618354	0	320
gen_edn_if_asserts[2].EdnDataStable_A	220604048	4566	0	125
gen_edn_if_asserts[2].EdnEndPointOut_A	220604048	220402625	0	0
gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A	220604048	162781	0	0
gen_edn_if_asserts[3].EdnDataStableDisable_A	220604048	618354	0	320
gen_edn_if_asserts[3].EdnDataStable_A	220604048	2360	0	106
gen_edn_if_asserts[3].EdnEndPointOut_A	220604048	220402625	0	0
gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A	220604048	162781	0	0
gen_edn_if_asserts[4].EdnDataStableDisable_A	220604048	618354	0	320
gen_edn_if_asserts[4].EdnDataStable_A	220604048	2903	0	105
gen_edn_if_asserts[4].EdnEndPointOut_A	220604048	220402625	0	0
gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A	220604048	162781	0	0
gen_edn_if_asserts[5].EdnDataStableDisable_A	220604048	618354	0	320
gen_edn_if_asserts[5].EdnDataStable_A	220604048	5585	0	107
gen_edn_if_asserts[5].EdnEndPointOut_A	220604048	220402625	0	0
gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A	220604048	162781	0	0
gen_edn_if_asserts[6].EdnDataStableDisable_A	220604048	618354	0	320
gen_edn_if_asserts[6].EdnDataStable_A	220604048	1303	0	79
gen_edn_if_asserts[6].EdnEndPointOut_A	220604048	220402625	0	0
gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A	220604048	162781	0	0

AlertTxKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220604048	220402625	0	0
T1	806	722	0	0
T2	4067	3982	0	0
T3	3615	3534	0	0
T4	23127	22187	0	0
T5	814	652	0	0
T10	4071	3983	0	0
T11	2963	2872	0	0
T13	3515	3429	0	0
T26	2161	2071	0	0
T27	2137	2075	0	0

CsrngAppIfOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220604048	220402625	0	0
T1	806	722	0	0
T2	4067	3982	0	0
T3	3615	3534	0	0
T4	23127	22187	0	0
T5	814	652	0	0
T10	4071	3983	0	0
T11	2963	2872	0	0
T13	3515	3429	0	0
T26	2161	2071	0	0
T27	2137	2075	0	0

FpvSecCmCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220604048	137	0	0
T8	1360	1	0	0
T16	2209	1	0	0
T17	0	1	0	0
T47	2665	0	0	0
T48	1733	0	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	1419	0	0	0
T58	3033	0	0	0
T59	1695	0	0	0
T60	4247	0	0	0
T61	4683	0	0	0
T62	1869	0	0	0

FpvSecCmGenCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220604048	90	0	0
T18	47497	20	0	0
T19	0	20	0	0
T20	0	20	0	0
T63	0	20	0	0
T64	0	10	0	0
T65	7161	0	0	0
T66	2231	0	0	0
T67	3699	0	0	0
T68	4685	0	0	0
T69	1220	0	0	0
T70	2492	0	0	0
T71	857	0	0	0
T72	2693	0	0	0
T73	2248	0	0	0

FpvSecCmGenCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220604048	90	0	0
T18	47497	20	0	0
T19	0	20	0	0
T20	0	20	0	0
T63	0	20	0	0
T64	0	10	0	0
T65	7161	0	0	0
T66	2231	0	0	0
T67	3699	0	0	0
T68	4685	0	0	0
T69	1220	0	0	0
T70	2492	0	0	0
T71	857	0	0	0
T72	2693	0	0	0
T73	2248	0	0	0

FpvSecCmMainFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220604048	90	0	0
T18	47497	20	0	0
T19	0	20	0	0
T20	0	20	0	0
T63	0	20	0	0
T64	0	10	0	0
T65	7161	0	0	0
T66	2231	0	0	0
T67	3699	0	0	0
T68	4685	0	0	0
T69	1220	0	0	0
T70	2492	0	0	0
T71	857	0	0	0
T72	2693	0	0	0
T73	2248	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220604048	90	0	0
T18	47497	20	0	0
T19	0	20	0	0
T20	0	20	0	0
T63	0	20	0	0
T64	0	10	0	0
T65	7161	0	0	0
T66	2231	0	0	0
T67	3699	0	0	0
T68	4685	0	0	0
T69	1220	0	0	0
T70	2492	0	0	0
T71	857	0	0	0
T72	2693	0	0	0
T73	2248	0	0	0

FpvSecCmResCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220604048	90	0	0
T18	47497	20	0	0
T19	0	20	0	0
T20	0	20	0	0
T63	0	20	0	0
T64	0	10	0	0
T65	7161	0	0	0
T66	2231	0	0	0
T67	3699	0	0	0
T68	4685	0	0	0
T69	1220	0	0	0
T70	2492	0	0	0
T71	857	0	0	0
T72	2693	0	0	0
T73	2248	0	0	0

FpvSecCmResCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220604048	90	0	0
T18	47497	20	0	0
T19	0	20	0	0
T20	0	20	0	0
T63	0	20	0	0
T64	0	10	0	0
T65	7161	0	0	0
T66	2231	0	0	0
T67	3699	0	0	0
T68	4685	0	0	0
T69	1220	0	0	0
T70	2492	0	0	0
T71	857	0	0	0
T72	2693	0	0	0
T73	2248	0	0	0

IntrEdnCmdReqDoneKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220604048	220402625	0	0
T1	806	722	0	0
T2	4067	3982	0	0
T3	3615	3534	0	0
T4	23127	22187	0	0
T5	814	652	0	0
T10	4071	3983	0	0
T11	2963	2872	0	0
T13	3515	3429	0	0
T26	2161	2071	0	0
T27	2137	2075	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220604048	220402625	0	0
T1	806	722	0	0
T2	4067	3982	0	0
T3	3615	3534	0	0
T4	23127	22187	0	0
T5	814	652	0	0
T10	4071	3983	0	0
T11	2963	2872	0	0
T13	3515	3429	0	0
T26	2161	2071	0	0
T27	2137	2075	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220604048	220402625	0	0
T1	806	722	0	0
T2	4067	3982	0	0
T3	3615	3534	0	0
T4	23127	22187	0	0
T5	814	652	0	0
T10	4071	3983	0	0
T11	2963	2872	0	0
T13	3515	3429	0	0
T26	2161	2071	0	0
T27	2137	2075	0	0

gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220604048	90	0	0
T18	47497	20	0	0
T19	0	20	0	0
T20	0	20	0	0
T63	0	20	0	0
T64	0	10	0	0
T65	7161	0	0	0
T66	2231	0	0	0
T67	3699	0	0	0
T68	4685	0	0	0
T69	1220	0	0	0
T70	2492	0	0	0
T71	857	0	0	0
T72	2693	0	0	0
T73	2248	0	0	0

gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220604048	90	0	0
T18	47497	20	0	0
T19	0	20	0	0
T20	0	20	0	0
T63	0	20	0	0
T64	0	10	0	0
T65	7161	0	0	0
T66	2231	0	0	0
T67	3699	0	0	0
T68	4685	0	0	0
T69	1220	0	0	0
T70	2492	0	0	0
T71	857	0	0	0
T72	2693	0	0	0
T73	2248	0	0	0

gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220604048	90	0	0
T18	47497	20	0	0
T19	0	20	0	0
T20	0	20	0	0
T63	0	20	0	0
T64	0	10	0	0
T65	7161	0	0	0
T66	2231	0	0	0
T67	3699	0	0	0
T68	4685	0	0	0
T69	1220	0	0	0
T70	2492	0	0	0
T71	857	0	0	0
T72	2693	0	0	0
T73	2248	0	0	0

gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220604048	90	0	0
T18	47497	20	0	0
T19	0	20	0	0
T20	0	20	0	0
T63	0	20	0	0
T64	0	10	0	0
T65	7161	0	0	0
T66	2231	0	0	0
T67	3699	0	0	0
T68	4685	0	0	0
T69	1220	0	0	0
T70	2492	0	0	0
T71	857	0	0	0
T72	2693	0	0	0
T73	2248	0	0	0

gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220604048	90	0	0
T18	47497	20	0	0
T19	0	20	0	0
T20	0	20	0	0
T63	0	20	0	0
T64	0	10	0	0
T65	7161	0	0	0
T66	2231	0	0	0
T67	3699	0	0	0
T68	4685	0	0	0
T69	1220	0	0	0
T70	2492	0	0	0
T71	857	0	0	0
T72	2693	0	0	0
T73	2248	0	0	0

gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220604048	90	0	0
T18	47497	20	0	0
T19	0	20	0	0
T20	0	20	0	0
T63	0	20	0	0
T64	0	10	0	0
T65	7161	0	0	0
T66	2231	0	0	0
T67	3699	0	0	0
T68	4685	0	0	0
T69	1220	0	0	0
T70	2492	0	0	0
T71	857	0	0	0
T72	2693	0	0	0
T73	2248	0	0	0

gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220604048	90	0	0
T18	47497	20	0	0
T19	0	20	0	0
T20	0	20	0	0
T63	0	20	0	0
T64	0	10	0	0
T65	7161	0	0	0
T66	2231	0	0	0
T67	3699	0	0	0
T68	4685	0	0	0
T69	1220	0	0	0
T70	2492	0	0	0
T71	857	0	0	0
T72	2693	0	0	0
T73	2248	0	0	0

gen_edn_if_asserts[0].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220604048	618354	0	320
T1	806	54	0	0
T2	4067	39	0	0
T3	3615	13	0	0
T4	23127	7212	0	2
T5	814	295	0	0
T10	4071	1456	0	2
T11	2963	607	0	0
T12	0	0	0	2
T13	3515	197	0	0
T21	0	0	0	2
T22	0	0	0	2
T26	2161	218	0	0
T27	2137	12	0	0
T39	0	0	0	2
T40	0	0	0	2
T41	0	0	0	2
T57	0	0	0	2
T74	0	0	0	2

gen_edn_if_asserts[0].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220604048	76146	0	426
T2	4067	3	0	1
T3	3615	42	0	1
T4	23127	15	0	0
T5	814	0	0	0
T6	0	25	0	1
T10	4071	0	0	0
T11	2963	0	0	0
T12	2908	0	0	0
T13	3515	5	0	1
T16	0	1	0	0
T26	2161	0	0	0
T27	2137	60	0	1
T58	0	0	0	1
T60	0	0	0	1
T75	0	53	0	1
T76	0	8	0	1
T77	0	4	0	1

gen_edn_if_asserts[0].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220604048	220402625	0	0
T1	806	722	0	0
T2	4067	3982	0	0
T3	3615	3534	0	0
T4	23127	22187	0	0
T5	814	652	0	0
T10	4071	3983	0	0
T11	2963	2872	0	0
T13	3515	3429	0	0
T26	2161	2071	0	0
T27	2137	2075	0	0

gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220604048	162781	0	0
T5	814	19	0	0
T6	21288	0	0	0
T7	0	912	0	0
T8	0	434	0	0
T9	0	1112	0	0
T12	2908	0	0	0
T13	3515	0	0	0
T16	0	1132	0	0
T17	0	1104	0	0
T31	2540	0	0	0
T35	0	22	0	0
T42	1539	0	0	0
T43	2385	0	0	0
T50	0	1074	0	0
T75	4255	0	0	0
T76	2260	0	0	0
T77	2101	0	0	0
T78	0	332	0	0
T79	0	373	0	0

gen_edn_if_asserts[1].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220604048	618354	0	320
T1	806	54	0	0
T2	4067	39	0	0
T3	3615	13	0	0
T4	23127	7212	0	2
T5	814	295	0	0
T10	4071	1456	0	2
T11	2963	607	0	0
T12	0	0	0	2
T13	3515	197	0	0
T21	0	0	0	2
T22	0	0	0	2
T26	2161	218	0	0
T27	2137	12	0	0
T39	0	0	0	2
T40	0	0	0	2
T41	0	0	0	2
T57	0	0	0	2
T74	0	0	0	2

gen_edn_if_asserts[1].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220604048	3354	0	130
T2	4067	27	0	1
T3	3615	3	0	1
T4	23127	0	0	0
T5	814	0	0	0
T10	4071	0	0	0
T11	2963	4	0	1
T12	2908	0	0	0
T13	3515	15	0	1
T25	0	3	0	1
T26	2161	0	0	0
T27	2137	0	0	0
T44	0	4	0	1
T45	0	1097	0	1
T46	0	8	0	1
T80	0	7	0	1
T81	0	3	0	1

gen_edn_if_asserts[1].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220604048	220402625	0	0
T1	806	722	0	0
T2	4067	3982	0	0
T3	3615	3534	0	0
T4	23127	22187	0	0
T5	814	652	0	0
T10	4071	3983	0	0
T11	2963	2872	0	0
T13	3515	3429	0	0
T26	2161	2071	0	0
T27	2137	2075	0	0

gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220604048	162781	0	0
T5	814	19	0	0
T6	21288	0	0	0
T7	0	912	0	0
T8	0	434	0	0
T9	0	1112	0	0
T12	2908	0	0	0
T13	3515	0	0	0
T16	0	1132	0	0
T17	0	1104	0	0
T31	2540	0	0	0
T35	0	22	0	0
T42	1539	0	0	0
T43	2385	0	0	0
T50	0	1074	0	0
T75	4255	0	0	0
T76	2260	0	0	0
T77	2101	0	0	0
T78	0	332	0	0
T79	0	373	0	0

gen_edn_if_asserts[2].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220604048	618354	0	320
T1	806	54	0	0
T2	4067	39	0	0
T3	3615	13	0	0
T4	23127	7212	0	2
T5	814	295	0	0
T10	4071	1456	0	2
T11	2963	607	0	0
T12	0	0	0	2
T13	3515	197	0	0
T21	0	0	0	2
T22	0	0	0	2
T26	2161	218	0	0
T27	2137	12	0	0
T39	0	0	0	2
T40	0	0	0	2
T41	0	0	0	2
T57	0	0	0	2
T74	0	0	0	2

gen_edn_if_asserts[2].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220604048	4566	0	125
T3	3615	3	0	1
T4	23127	0	0	0
T5	814	0	0	0
T10	4071	0	0	0
T11	2963	0	0	0
T12	2908	4	0	0
T13	3515	0	0	0
T25	0	55	0	1
T26	2161	0	0	0
T27	2137	0	0	0
T31	0	4	0	1
T44	0	33	0	1
T45	0	45	0	1
T46	0	3	0	1
T62	0	4	0	1
T75	4255	0	0	0
T81	0	3	0	1
T82	0	3	0	1
T83	0	0	0	1

gen_edn_if_asserts[2].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220604048	220402625	0	0
T1	806	722	0	0
T2	4067	3982	0	0
T3	3615	3534	0	0
T4	23127	22187	0	0
T5	814	652	0	0
T10	4071	3983	0	0
T11	2963	2872	0	0
T13	3515	3429	0	0
T26	2161	2071	0	0
T27	2137	2075	0	0

gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220604048	162781	0	0
T5	814	19	0	0
T6	21288	0	0	0
T7	0	912	0	0
T8	0	434	0	0
T9	0	1112	0	0
T12	2908	0	0	0
T13	3515	0	0	0
T16	0	1132	0	0
T17	0	1104	0	0
T31	2540	0	0	0
T35	0	22	0	0
T42	1539	0	0	0
T43	2385	0	0	0
T50	0	1074	0	0
T75	4255	0	0	0
T76	2260	0	0	0
T77	2101	0	0	0
T78	0	332	0	0
T79	0	373	0	0

gen_edn_if_asserts[3].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220604048	618354	0	320
T1	806	54	0	0
T2	4067	39	0	0
T3	3615	13	0	0
T4	23127	7212	0	2
T5	814	295	0	0
T10	4071	1456	0	2
T11	2963	607	0	0
T12	0	0	0	2
T13	3515	197	0	0
T21	0	0	0	2
T22	0	0	0	2
T26	2161	218	0	0
T27	2137	12	0	0
T39	0	0	0	2
T40	0	0	0	2
T41	0	0	0	2
T57	0	0	0	2
T74	0	0	0	2

gen_edn_if_asserts[3].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220604048	2360	0	106
T6	21288	0	0	0
T7	1623	0	0	0
T12	2908	0	0	0
T13	3515	36	0	1
T25	0	35	0	1
T31	2540	0	0	0
T42	1539	4	0	1
T43	2385	4	0	1
T44	0	10	0	1
T45	0	3	0	1
T46	0	49	0	1
T75	4255	0	0	0
T76	2260	0	0	0
T77	2101	0	0	0
T81	0	3	0	1
T84	0	3	0	1
T85	0	4	0	0
T86	0	0	0	1

gen_edn_if_asserts[3].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220604048	220402625	0	0
T1	806	722	0	0
T2	4067	3982	0	0
T3	3615	3534	0	0
T4	23127	22187	0	0
T5	814	652	0	0
T10	4071	3983	0	0
T11	2963	2872	0	0
T13	3515	3429	0	0
T26	2161	2071	0	0
T27	2137	2075	0	0

gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220604048	162781	0	0
T5	814	19	0	0
T6	21288	0	0	0
T7	0	912	0	0
T8	0	434	0	0
T9	0	1112	0	0
T12	2908	0	0	0
T13	3515	0	0	0
T16	0	1132	0	0
T17	0	1104	0	0
T31	2540	0	0	0
T35	0	22	0	0
T42	1539	0	0	0
T43	2385	0	0	0
T50	0	1074	0	0
T75	4255	0	0	0
T76	2260	0	0	0
T77	2101	0	0	0
T78	0	332	0	0
T79	0	373	0	0

gen_edn_if_asserts[4].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220604048	618354	0	320
T1	806	54	0	0
T2	4067	39	0	0
T3	3615	13	0	0
T4	23127	7212	0	2
T5	814	295	0	0
T10	4071	1456	0	2
T11	2963	607	0	0
T12	0	0	0	2
T13	3515	197	0	0
T21	0	0	0	2
T22	0	0	0	2
T26	2161	218	0	0
T27	2137	12	0	0
T39	0	0	0	2
T40	0	0	0	2
T41	0	0	0	2
T57	0	0	0	2
T74	0	0	0	2

gen_edn_if_asserts[4].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220604048	2903	0	105
T3	3615	31	0	1
T4	23127	0	0	0
T5	814	0	0	0
T10	4071	0	0	0
T11	2963	0	0	0
T12	2908	0	0	0
T13	3515	3	0	1
T15	0	0	0	1
T22	0	4	0	0
T26	2161	4	0	1
T27	2137	0	0	0
T32	0	1	0	0
T35	0	1	0	0
T46	0	15	0	1
T75	4255	0	0	0
T86	0	0	0	1
T87	0	3	0	1
T88	0	24	0	1
T89	0	8	0	1
T90	0	0	0	1

gen_edn_if_asserts[4].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220604048	220402625	0	0
T1	806	722	0	0
T2	4067	3982	0	0
T3	3615	3534	0	0
T4	23127	22187	0	0
T5	814	652	0	0
T10	4071	3983	0	0
T11	2963	2872	0	0
T13	3515	3429	0	0
T26	2161	2071	0	0
T27	2137	2075	0	0

gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220604048	162781	0	0
T5	814	19	0	0
T6	21288	0	0	0
T7	0	912	0	0
T8	0	434	0	0
T9	0	1112	0	0
T12	2908	0	0	0
T13	3515	0	0	0
T16	0	1132	0	0
T17	0	1104	0	0
T31	2540	0	0	0
T35	0	22	0	0
T42	1539	0	0	0
T43	2385	0	0	0
T50	0	1074	0	0
T75	4255	0	0	0
T76	2260	0	0	0
T77	2101	0	0	0
T78	0	332	0	0
T79	0	373	0	0

gen_edn_if_asserts[5].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220604048	618354	0	320
T1	806	54	0	0
T2	4067	39	0	0
T3	3615	13	0	0
T4	23127	7212	0	2
T5	814	295	0	0
T10	4071	1456	0	2
T11	2963	607	0	0
T12	0	0	0	2
T13	3515	197	0	0
T21	0	0	0	2
T22	0	0	0	2
T26	2161	218	0	0
T27	2137	12	0	0
T39	0	0	0	2
T40	0	0	0	2
T41	0	0	0	2
T57	0	0	0	2
T74	0	0	0	2

gen_edn_if_asserts[5].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220604048	5585	0	107
T3	3615	3	0	1
T4	23127	0	0	0
T5	814	1	0	0
T10	4071	4	0	0
T11	2963	0	0	0
T12	2908	0	0	0
T13	3515	26	0	1
T25	0	615	0	1
T26	2161	0	0	0
T27	2137	0	0	0
T46	0	18	0	1
T47	0	4	0	1
T59	0	4	0	1
T75	4255	0	0	0
T81	0	0	0	1
T91	0	4	0	1
T92	0	4	0	1
T93	0	0	0	1

gen_edn_if_asserts[5].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220604048	220402625	0	0
T1	806	722	0	0
T2	4067	3982	0	0
T3	3615	3534	0	0
T4	23127	22187	0	0
T5	814	652	0	0
T10	4071	3983	0	0
T11	2963	2872	0	0
T13	3515	3429	0	0
T26	2161	2071	0	0
T27	2137	2075	0	0

gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220604048	162781	0	0
T5	814	19	0	0
T6	21288	0	0	0
T7	0	912	0	0
T8	0	434	0	0
T9	0	1112	0	0
T12	2908	0	0	0
T13	3515	0	0	0
T16	0	1132	0	0
T17	0	1104	0	0
T31	2540	0	0	0
T35	0	22	0	0
T42	1539	0	0	0
T43	2385	0	0	0
T50	0	1074	0	0
T75	4255	0	0	0
T76	2260	0	0	0
T77	2101	0	0	0
T78	0	332	0	0
T79	0	373	0	0

gen_edn_if_asserts[6].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220604048	618354	0	320
T1	806	54	0	0
T2	4067	39	0	0
T3	3615	13	0	0
T4	23127	7212	0	2
T5	814	295	0	0
T10	4071	1456	0	2
T11	2963	607	0	0
T12	0	0	0	2
T13	3515	197	0	0
T21	0	0	0	2
T22	0	0	0	2
T26	2161	218	0	0
T27	2137	12	0	0
T39	0	0	0	2
T40	0	0	0	2
T41	0	0	0	2
T57	0	0	0	2
T74	0	0	0	2

gen_edn_if_asserts[6].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220604048	1303	0	79
T1	806	3	0	1
T2	4067	0	0	0
T3	3615	3	0	1
T4	23127	0	0	0
T5	814	0	0	0
T10	4071	0	0	0
T11	2963	0	0	0
T13	3515	0	0	0
T21	0	4	0	0
T25	0	25	0	1
T26	2161	0	0	0
T27	2137	0	0	0
T46	0	3	0	1
T48	0	24	0	1
T85	0	4	0	1
T94	0	4	0	1
T95	0	4	0	1
T96	0	4	0	1
T97	0	0	0	1

gen_edn_if_asserts[6].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220604048	220402625	0	0
T1	806	722	0	0
T2	4067	3982	0	0
T3	3615	3534	0	0
T4	23127	22187	0	0
T5	814	652	0	0
T10	4071	3983	0	0
T11	2963	2872	0	0
T13	3515	3429	0	0
T26	2161	2071	0	0
T27	2137	2075	0	0

gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220604048	162781	0	0
T5	814	19	0	0
T6	21288	0	0	0
T7	0	912	0	0
T8	0	434	0	0
T9	0	1112	0	0
T12	2908	0	0	0
T13	3515	0	0	0
T16	0	1132	0	0
T17	0	1104	0	0
T31	2540	0	0	0
T35	0	22	0	0
T42	1539	0	0	0
T43	2385	0	0	0
T50	0	1074	0	0
T75	4255	0	0	0
T76	2260	0	0	0
T77	2101	0	0	0
T78	0	332	0	0
T79	0	373	0	0